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Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10)
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Description of operation
The PWM output cycle is specified by using the compare register CM100. When the value of this
register matches the value of TMENC10, the INTCM10 interrupt is generated, and TMENC10 is
cleared at the next count clock after the match.
The required PWM output duty is set by using the compare register CM101.
Figure 12-14: PWM Signal Output Example (When ALVT10 Bit = 0 Is Set)
Cautions: 1. Changing the values of the CM100 and CM101 registers is prohibited during
TMENC10 operation (TM1CE bit of TMC10 register = 1).
2. Changing the value of the ALVT1 bit of the TUM register is prohibited during
TMENC10 operation.
3. PWM signal output is performed from the second PWM cycle after the TM1CE bit
is set (1).
CM10 set value
TMENC1
CM11 set value
TO1
INTCM10
INTCM11
User's Manual U16580EE3V1UD00
557
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