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(5)
Basic operation in high-accuracy T-PWM mode
The Figure 10-59 shows the timing chart when TRnCCR0 = 0010H, TRnDTC0 = 0002H,
TRnDTC1 = 0004H, and the TRnCCR1 register is set from 0000H to 0010H (one part only
shown). In this example, TRnOL6 to TRnOL1 = 000000B is set.
If TRnCCR1 > TRnDTC0, pin TORn2 changes with the following compare match.
Since TRnCCR1 = (TRnDTC0-0001H) is an additional pulse, compared to when
TRnCCR1 = (TRnDTC0 - 0002H), pin TORn2 changes with an 1 count clock delay.
Figure 10-59: Timer Output Example When TRnCE = 1 Is Set (Initial)
Counter
Sub-counter
TRnCE
TRnCUF
TRnSUF
TRnCCR0
TRnDTC0
TRnDTC1
[TRnCCR1 = 0000H]
TORn1
TORn2
[TRnCCR1 = 0001H]
TORn1
TORn2
[TRnCCR1 = 0002H]
TORn1
TORn2
[TRnCCR1 = 0004H]
TORn1
TORn2
[TRnCCR1 = 0008H]
TORn1
TORn2
[TRnCCR1 = 000AH]
TORn1
TORn2
[TRnCCR1 = 000CH]
TORn1
TORn2
[TRnCCR1 = 000EH]
TORn1
TORn2
[TRnCCR1 = 0010H]
TORn1
TORn2
Remarks: 1. TRnCCR0 = 0010H, TRnDTC0 = 0002H, TRnDTC1 = 0004H
2. TD0: Time depends on dead time setting of TRnDTC0 register
TD1: Time depends on dead time setting of TRnDTC1 register
TS1: Time is determined through sub-counter compare, when
sub-counter value > counter value
3. n = 0, 1
Chapter 10 16-bit Inverter Timer/Counter R
(High-Accuracy T-PWM Mode)
FFFE
00020004
0006
0008
FFFE
0002
00000002000400060008
0010H (for cycle setting)
002H (for dead time setting)
004H (for dead time setting)
T
D0
T
D0
"L"
"L"
"L"
User's Manual U16580EE3V1UD00
0008000600040002 0004
000A 000C 000A
0010
000E
000E 000C 000A
T
D0
T
T
D1
T
D1
T
S1
0000
D1
425
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