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Chapter 5 Memory Access Control Function (μPD70F3187 only)
Figure 5-2: SRAM, External ROM, External I/O Access Timing (5/8)
Bus clock
A0 to A21
(output)
CSn (output)
RD (output)
WR (output)
BEN0
to
BEN3
(output)
D0 to D31
(input)
WAIT (input)
Notes: 1. CSn output levels depend on the accessed area when enabled by BCT0 and BCT1
registers.
2. BEN0 to BEN3 output levels depend on the accessed type (byte, half-word, or word) and
the external bus size (8, 16, or 32 bits) specified by the BSC register
Remarks: 1. n = 0, 1, 3, 4
2. Bus clock = f
3. The circle indicates the sampling timing.
4. The dashed line indicates the high impedance state.
188
T1
T2
Address
Note 1
H
Note 2
Data
without data wait insertion
/2
XX
User's Manual U16580EE3V1UD00
(e) Write
T1
with data wait insertion
TW
T2
Address
Note 1
Note 2
Data
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