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9.4 Control Registers
(1)
TMPn control register 0 (TPnCTL0)
The TPnCTL0 register is an 8-bit register that controls the operation of timer P.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
The same value can always be written to the TPnCTL0 register by software.
After reset:
00H
7
TPnCTL0
TPnCE
(n = 0 to 8)
TPnCE
0
1
• Internal operating clock control and TMPn asynchronous reset are performed with the
TPnCE bit. When the TPnCE bit is cleared to 0, the internal operating clock of TMPn
stops (fixed to low level) and TMPn is reset asynchronously.
• When the TPnCE bit is set to 1, the internal operating clock is enabled and count-up
operation starts within 2 input clocks after the TPnCE bit was set to 1
TPnCKS2 TPnCKS1 TPnCKS0
0
0
0
0
1
1
1
1
Caution:
Set the TPnCKS2 to TPnCKS0 bits when TPnCE = 0. When the value of the TPnCE bit
is changed from 0 to 1, the TPnCKS2 to TPnCKS0 bits can be set simultaneously.
Remark:
n = 0 to 8
264
Chapter 9 16-Bit Timer/Event Counter P
Figure 9-5: TMPn Control Register 0 (TPnCTL0)
R/W
Address:
6
5
0
0
Internal operating clock operation disabled (TMPn reset asynchronously)
Internal operating clock operation enabled
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
User's Manual U16580EE3V1UD00
TP0CTL0 FFFFF600H, TP1CTL0 FFFFF610H,
TP2CTL0 FFFFF620H, TP3CTL0 FFFFF630H,
TP4CTL0 FFFFF640H, TP5CTL0 FFFFF650H,
TP6CTL0 FFFFF660H, TP7CTL0 FFFFF670H,
TP8CTL0 FFFFF680H
4
3
0
0
TPnCKS2 TPnCKS1 TPnCKS0
Timer Pn Operation Control
Internal Count Clock Selection
f
XX
f
XX
f
XX
f
XX
f
XX
f
XX
f
XX
f
XX
2
1
0
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