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17.6.12 Consecutive mode (in slave mode and transmission/reception mode)
Figure 17-33: Consecutive Mode (Slave Mode, Transmission/Reception Mode)
Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B)
Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B)
CTXEn bit,
CRXEn bit
SFDB3n
register write
SFEMPn flag
CSIBUF3n [0]
CSIBUF3n [1]
CSIBUF3n [2]
SCK3n pin
SO3n pin
SI3n pin
SCS3n0 to
H (inactive)
SCS3n3 pins
CSOTn flag
INTC3n signal
SIRB3n
register read
SFN3 to
SFN0 bits
SFP3 to
0H
SFP0 bits
<1>
<5>
<6>
<2>
<3>
<4>
Note: During this period a transmission/reception from the master will be ignored until at least one
transmit data is loaded to the CSIBUFn register by writing the SFDB3n register (SFEMPn flag of
SFA3n register = 0).
μPD70F3187:
Remark:
μPD70F3447:
736
Chapter 17 Clocked Serial Interface 3 (CSI3)
MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 1
INTC3n Interrupt Not Delayed (CSIT bit = 0),
Transfer Wait: Disabled (CSWE bit = 0),
55H
CCH
AAH
0
1
0
1
0
1
0
1 1
1
1
0 0
1 1
0 0
3H
<7>
<7>
n = 0, 1
n = 0
User's Manual U16580EE3V1UD00
96H
0
1
0
1
0
1
0
1
0 0
1
0
1 1
0
1H
2H
<7>
Note
33H
0 0
1
1
0 0
1
1
1
0
0
1 1
0 0
1
3H
<8>
99H
0H
<8>
<11>
<8>
<9>
<10>
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