Page 1 User’s Manual V850ES/ST2 32-bit Single-Chip Microcontroller Hardware μ PD703220 Document No. U17031EJ2V0UD00 (2nd edition) Date Published December 2006 N CP(K) 2004 Printed in Japan...
Page 2 [MEMO] User’s Manual U17031EJ2V0UD...
Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 PREFACE Readers This manual is intended for users who wish to understand the functions of the μ V850ES/ST2 ( PD703220) and design application systems using this product. Purpose This manual is intended to give users an understanding of the hardware functions of μ...
Page 6 The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note with caution that if “xxx.yyy” is described as is in a program, however, the compiler/assembler cannot recognize it correctly. The mark <R> shows major revised points. The revised points can be easily searched by copying an “<R>”...
Page 7 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/ST2 Document Name Document No. V850ES Architecture User’s Manual U15943E V850ES/ST2 Hardware User’s Manual This manual Documents related to development tools Document Name Document No.
Page 8: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION........................14 General ............................14 Features.............................14 Application Fields........................15 Ordering Information........................15 Pin Configuration (Top View) ....................16 Function Block Configuration ....................19 1.6.1 Internal block diagram .........................19 1.6.2 Internal units..........................20 CHAPTER 2 PIN FUNCTIONS ........................22 List of Pin Functions ........................22 Pin States ..........................29 Pin I/O Circuit Types, I/O Buffer Power Supply and Recommended Connection of Unused Pins ..........................30 CHAPTER 3 CPU FUNCTION .........................35...
Page 9 4.3.8 Port CM ............................89 4.3.9 Port CS ............................91 4.3.10 Port CT............................93 4.3.11 Port DH ............................95 Block Diagrams ........................97 Port Register Settings When Alternate Function Is Used ..........120 Cautions ..........................125 4.6.1 Cautions on setting port pins..................... 125 4.6.2 Cautions on bit manipulation instruction for port n register (Pn)..........
Page 10 Configuration ..........................160 Registers ..........................162 Operation..........................173 7.5.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000)............... 180 7.5.2 External event count mode (TPnMD2 to TPnMD0 bits = 001)...........189 7.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010)........197 7.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) ..........209 7.5.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100)..............
Page 11 11.7 How to Read A/D Converter Characteristics Table.............290 CHAPTER 12 D/A CONVERTER ......................294 12.1 Functions ..........................294 12.2 Configuration ..........................294 12.3 Control Registers ........................295 12.4 Operation..........................297 12.4.1 Operation in normal mode......................297 12.4.2 Operation in real-time output mode................... 297 12.4.3 Cautions ............................ 298 CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ..........299 13.1 CSIB4 and UARTA0 Mode Switching ...................299 13.2 Features...........................300...
Page 12 15.2 Non-Maskable Interrupts .......................355 15.2.1 Operation...........................357 15.2.2 Restore............................358 15.2.3 NP flag............................359 15.3 Maskable Interrupts........................360 15.3.1 Operation...........................360 15.3.2 Restore............................362 15.3.3 Priorities of maskable interrupts ....................363 15.3.4 Interrupt control register (xxICn)....................367 15.3.5 Interrupt mask registers 0 to 2 (IMR0 to IMR2) .................369 15.3.6 In-service priority register (ISPR) ....................370 15.3.7...
Page 13 18.2 Operation..........................404 CHAPTER 19 ELECTRICAL SPECIFICATIONS..................405 CHAPTER 20 PACKAGE DRAWINGS....................454 <R> CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS............456 APPENDIX A CAUTIONS........................457 Restriction on Conflict Between sld Instruction and Interrupt Request ......457 A.1.1 Description ..........................457 A.1.2 Countermeasure ........................457 Restrictions on Generation Timing of Re-conversion Sources During Operation <R>...
Page 14: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION The V850ES/ST2 is one of the products in NEC Electronics’ V850 single-chip microcontrollers designed for low- power operation for real-time control applications. General The V850ES/ST2 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions such as RAM, a timer/counter, serial interfaces, an A/D converter, and a D/A converter.
Page 15: Application Fields
CHAPTER 1 INTRODUCTION 6 bits × 1 channel or 4 bits × 1 channel and 2 bits × 1 channel Real-time output function: Serial interface: Asynchronous serial interface A (UARTA) 3-wire variable-length serial interface B (CSIB) UARTA/CSIB: 1 channel UARTA: 1 channel CSIB: 1 channel...
Page 16: Pin Configuration (Top View)
CHAPTER 1 INTRODUCTION Pin Configuration (Top View) 120-pin plastic TQFP (fine pitch) (14 × 14) <R> μ PD703220GC-9EB-A P38/TXDA2 REF0 P39/RXDA2 P10/ANO0 PCM3/HLDRQ P11/ANO1 PCM2/HLDAK PCM1/CLKOUT REF1 PCM0/WAIT P92/TIP41/TOP41 P93/TIP40 P94/TIP31/TOP31 P95/TIP30 P96/TIP21/TOP21 P97/TIP20 P910 P911 AD10 P912 AD11 P913/INTP4 P914/INTP5/TIP51/TOP51 P915/INTP6/TIP50 AD12...
Page 17 CHAPTER 1 INTRODUCTION 144-pin plastic LQFP (fine pitch) (20 × 20) <R> μ PD703220GJ-UEN-A P38/TXDA2 REF0 P39/RXDA2 P10/ANO0 PCM3/HLDRQ P11/ANO1 PCM2/HLDAK REF1 Note PCM1/CLKOUT Note PCM0/WAIT P92/TIP41/TOP41 P93/TIP40 P94/TIP31/TOP31 P95/TIP30 P96/TIP21/TOP21 P97/TIP20 Note Note P910 AD10 P911 AD11 P912 P913/INTP4 P914/INTP5/TIP51/TOP51 P915/INTP6/TIP50 Note...
Page 18 CHAPTER 1 INTRODUCTION Pin names A0 to A21: Address bus PCS1 to PCS3: Port CS AD0 to AD15: Address/data bus PCT0, PCT1, ADTRG: A/D trigger input PCT4, PCT6: Port CT ANI0 to ANI7: Analog input PDH0 to PDH5: Port DH ANO0, ANO1: Analog output Read strobe...
Page 19: Function Block Configuration
CHAPTER 1 INTRODUCTION Function Block Configuration 1.6.1 Internal block diagram INTC INTP0 to INTP7 Instruction queue HLDRQ TIP00, TIP01, TIP10, TIP11, 32-bit Multiplier HLDAK TIP20, TP21, TIP30, TIP31, 16 × 16 → 32 barrel shifter ASTB TIP40, TIP41, TIP50, TIP51 16-bit timer/ 48 KB counter P: 6ch...
Page 20: Internal Units
CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing.
Page 21 CHAPTER 1 INTRODUCTION (10) A/D converter This 10-bit A/D converter includes 8 analog input pins. Conversion is performed using the successive approximation method. (11) D/A converter A two-channel, 8-bit-resolution D/A converter that uses the R-2R ladder method is provided on chip. (12) Ports There are general-purpose port functions and control pin functions, as listed below.
Page 22: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS List of Pin Functions The names and functions of the pins of the V850ES/ST2 are described below. There are four types of pin I/O buffer power supplies: AV , AV , EV , and BV . The relationship between REF0 REF1 these power supplies and the pins is described below.
Page 23 CHAPTER 2 PIN FUNCTIONS (1) Port pins (1/2) Pin Name Pin No. Function Alternate Function 112 134 Port 0 5-bit I/O port 111 133 INTP0/ADTRG Input/output can be specified in 1-bit units. 110 132 INTP1 109 131 INTP2 108 130 INTP3 Port 1 ANO0...
Page 24 CHAPTER 2 PIN FUNCTIONS (2/2) Pin Name Pin No. Function Alternate Function Port 9 TIP30 16-bit I/O port TIP21/TOP21 Input/output can be specified in 1-bit units. TIP20 − − − P910 − P911 − P912 P913 INTP4 P914 INTP5/TIP51/TOP51 P915 INTP6/TIP50 PCM0 Port CM...
Page 25 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/4) Pin Name Pin No. Function Alternate Function − Output Address bus used for external memory (when using separate bus) − − − − − − − − − − − − − −...
Page 26 CHAPTER 2 PIN FUNCTIONS (2/4) Pin Name Pin No. Function Alternate Function ANI0 Input Analog voltage input for A/D converter ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANO0 Output Analog voltage output for D/A converter ANO1 P32/SCKB4/TIP00 ASCKA0 Input UARTA0 baud rate clock input ASTB Output Address strobe signal output for external memory...
Page 27 CHAPTER 2 PIN FUNCTIONS (3/4) Pin Name Pin No. Function Alternate Function − − − <R> Internally connected pins <R> − − − <R> − − − − − − <R> − − − <R> − − − <R> INTP0 Input External interrupt request input (maskable, analog noise P03/ADTRG...
Page 28 CHAPTER 2 PIN FUNCTIONS (4/4) Pin Name Pin No. Function Alternate Function TIP20 Input Capture trigger input/external event count input/external trigger input (TMP2) TIP21 P96/TOP21 Capture trigger input (TMP2) TIP30 Capture trigger input/external event count input/external trigger input (TMP3) TIP31 P94/TOP31 Capture trigger input (TMP3) TIP40...
Page 29: Pin States
CHAPTER 2 PIN FUNCTIONS Pin States The operation states of pins in the various modes are described below. Table 2-2. Pin Operation States in Various Modes Note 1 Note 2 Operating Status Reset HALT Mode IDLE Mode/ Idle State Bus Hold STOP Mode AD0 to AD15 Hi-Z...
Page 30: Pin I/O Circuit Types, I/O Buffer Power Supply And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS Pin I/O Circuit Types, I/O Buffer Power Supply and Recommended Connection of Unused Pins (1/4) Alternate Function Pin No. I/O Circuit Type Recommended Connection <R> Input: Independently connect to EV or EV <R> INTP0/ADTRG via a resistor. <R>...
Page 31 CHAPTER 2 PIN FUNCTIONS (2/4) Alternate Function Pin No. I/O Circuit Type Recommended Connection <R> TIP31/TOP31 Input: Independently connect to EV or EV <R> via a resistor. TIP30 Output: Leave open. <R> TIP21/TOP21 <R> TIP20 − − − P910 − P911 −...
Page 32 CHAPTER 2 PIN FUNCTIONS (3/4) Alternate Function Pin No. I/O Circuit Type Recommended Connection − Leave open. − − − − − − − Leave open. − − − − − − − − − − AD10 − AD11 − AD12 −...
Page 33 CHAPTER 2 PIN FUNCTIONS (4/4) Alternate Function Pin No. I/O Circuit Type Recommended Connection − − Directly connect to V REF0 − − Directly connect to V REF1 − − Directly connect to V − − − Note 1 Note 1 −...
Page 34 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits Type 2 Type 9 Comparator P-ch N-ch (Threshold voltage) REF0 Schmitt-triggered input with hysteresis characteristics Input enable Type 5 Type 12-D REF1 Data P-ch IN/OUT Data Output N-ch IN/OUT disable Output disable Input P-ch...
Page 35: Chapter 3 Cpu Function
CHAPTER 3 CPU FUNCTION The CPU of the V850ES/ST2 is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. Features Minimum instruction execution time: 29.4 ns (at 34 MHz (max.) operation while internal RAM is executed) Memory space Program (physical address) space: 64 MB linear Data (logical address) space:...
Page 36: Cpu Register Set
CHAPTER 3 CPU FUNCTION CPU Register Set The registers of the V850ES/ST2 can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User’s Manual. (1) Program register set (2) System register set (Zero register)
Page 37: Program Register Set
CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a data variable or an address variable.
Page 38: System Register Set
CHAPTER 3 CPU FUNCTION 3.2.2 System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below. Table 3-2.
Page 39 CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs. If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC, and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to the NMI status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs).
Page 40 CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs. If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status word (PSW) are saved to FEPSW.
Page 41 CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are validated immediately after completion of LDSR instruction execution.
Page 42 CHAPTER 3 CPU FUNCTION (2/2) Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is performed.
Page 43 CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers. If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the program status word (PSW) are saved to DBPSW.
Page 44: Operation Modes
CHAPTER 3 CPU FUNCTION Operation Modes The V850ES/ST2 has the following operation modes. The MODE pin is used to specify modes. (1) Normal operation mode (ROM-less mode) In this mode, each pin related to the bus interface is set to the port mode after system reset has been released. An instruction is fetched from the external memory and processing is started.
Page 45: Address Space
CHAPTER 3 CPU FUNCTION Address Space 3.4.1 CPU address space For instruction addressing, up to 12 MB of external memory area and an internal RAM area are supported in a linear address space (program space) of up to 64 MB. For operand addressing (data access), up to 4 GB of a linear address space (data space) is supported.
Page 46: Wrap-Around Of Cpu Address Space
CHAPTER 3 CPU FUNCTION 3.4.2 Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. Therefore, the highest address of the program space, 03FFFFFFH, and the lowest address, 00000000H, are contiguous addresses.
Page 47: Memory Map
CHAPTER 3 CPU FUNCTION 3.4.3 Memory map The areas shown below are reserved in the V850ES/ST2. Figure 3-2. Data Memory Map (Physical Addresses) 3 F F F F F F H 3 F F F F F F H On-chip peripheral I/O area (4 KB) 3 F F F 0 0 0 H (80 KB)
Page 48 CHAPTER 3 CPU FUNCTION Figure 3-3. Program Memory Map 0 3 F F F F F F H Use prohibited (program fetch prohibited area) 0 3 F F F 0 0 0 H 0 3 F F E F F F H Internal RAM area (48 KB) 3 F F 3 0 0 0 H 3 F F 2 F F F H...
Page 49: Areas
CHAPTER 3 CPU FUNCTION 3.4.4 Areas (1) Internal RAM area 60 KB of addresses 3FF0000H to 3FFEFFFH are reserved as the internal RAM area. 48 KB of addresses 3FF3000H to 3FFEFFFH are mapped in the V850ES/ST2 as physical internal RAM. Figure 3-4.
Page 50 CHAPTER 3 CPU FUNCTION (2) On-chip peripheral I/O area 4 KB of addresses 3FFF000H to 3FFFFFFH are allocated as the on-chip peripheral I/O area. Figure 3-5. On-Chip Peripheral I/O Area Logical address space Physical address space 3 F F F F F F H F F F F F F F H On-chip peripheral I/O area (4 KB)
Page 51: Recommended Use Of Address Space
CHAPTER 3 CPU FUNCTION 3.4.5 Recommended use of address space The architecture of the V850ES/ST2 requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer ±32 KB can be directly accessed by an instruction for operand data.
Page 52 CHAPTER 3 CPU FUNCTION Figure 3-6. Recommended Memory Map Program space Data space F F F F F F F F H On-chip peripheral I/O F F F F F 0 0 0 H F F F F E F F F H Internal RAM x F F F F F F F H F F F F 3 0 0 0 H...
Page 53: Peripheral I/O Registers
CHAPTER 3 CPU FUNCTION 3.4.6 Peripheral I/O registers (1/6) Address Function Register Name Symbol Default Manipulatable Bits Value √ √ Note 1 FFFFF006H Port DH register √ √ Note 2 FFFFF008H Port CS register Undefined √ √ Note 1 FFFFF00AH Port CT register √...
Page 54 CHAPTER 3 CPU FUNCTION (2/6) Address Function Register Name Symbol Default Manipulatable Bits Value √ √ FFFFF12EH Interrupt control register TP2OVIC √ √ FFFFF130H Interrupt control register TP2CCIC0 √ √ FFFFF132H Interrupt control register TP2CCIC1 √ √ FFFFF134H Interrupt control register TP3OVIC √...
Page 55 CHAPTER 3 CPU FUNCTION (3/6) Address Function Register Name Symbol Default Manipulatable Bits Value √ FFFFF21EH A/D conversion result register 7 ADA0CR7 Undefined √ FFFFF21FH A/D conversion result register 7H ADA0CR7H Undefined √ FFFFF280H D/A converter conversion value setting register 0 DA0CS0 √...
Page 56 CHAPTER 3 CPU FUNCTION (4/6) Address Function Register Name Symbol Default Manipulatable Bits Value √ FFFFF472H Port 9 function control register PFC9 0000H √ √ FFFFF472H Port 9 function control register L PFC9L √ √ FFFFF473H Port 9 function control register H PFC9H √...
Page 57 CHAPTER 3 CPU FUNCTION (5/6) Address Function Register Name Symbol Default Manipulatable Bits Value √ √ FFFFF5D0H TMP4 control register 0 TP4CTL0 √ √ FFFFF5D1H TMP4 control register 1 TP4CTL1 √ √ FFFFF5D2H TMP4 I/O control register 0 TP4IOC0 √ √...
Page 58 CHAPTER 3 CPU FUNCTION (6/6) Address Function Register Name Symbol Default Manipulatable Bits Value √ FFFFFA07H UARTA0 transmit data register UA0TX √ √ FFFFFA20H UARTA2 control register 0 UA2CTL0 √ FFFFFA21H UARTA2 control register 1 UA2CTL1 √ FFFFFA22H UARTA2 control register 2 UA2CTL2 √...
Page 59: Special Registers
CHAPTER 3 CPU FUNCTION 3.4.7 Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850ES/ST2 has the following three special registers. • Power save control register (PSC) • Processor clock control register (PCC) •...
Page 60 CHAPTER 3 CPU FUNCTION (2) Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The first write access to a special register is valid after data has been written in advance to the PRCMD register.
Page 61 CHAPTER 3 CPU FUNCTION (3) System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: Address: FFFFF802H...
Page 62: Notes
CHAPTER 3 CPU FUNCTION 3.4.8 Notes (1) System wait control register (VSWC) Be sure to set the VSWC register first when using the V850ES/ST2. After setting the VSWC register, set the other registers as necessary. When using the external bus, set each pin as the alternate-function bus control pin by using the port-related registers after setting the above register.
Page 63: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS Features Input-only port: 8 I/O ports: 57 Input/output specifiable in 1-bit units Basic Port Configuration The V850ES/ST2 features a total of 65 I/O ports (including 8 input-only ports) consisting of ports 0, 1, 3 to 5, 7, 9, CM, CS, CT, and DH.
Page 64: Port Configuration
CHAPTER 4 PORT FUNCTIONS Port Configuration Table 4-2. Port Configuration Item Configuration Control registers Port n mode register (PMn: n = 0, 1, 3 to 5, 9, CM, CS, CT, DH) Port n mode control register (PMCn: n = 0, 3 to 5, 9, CM, CS, CT, DH) Port n function control register (PFCn: n = 0, 3, 5, 9) Port n function control expansion register (PFCEn: n = 3, 5, 9) Ports...
Page 65 CHAPTER 4 PORT FUNCTIONS (2) Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit units.
Page 66 CHAPTER 4 PORT FUNCTIONS (4) Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units.
Page 67 CHAPTER 4 PORT FUNCTIONS (6) Port setting Set a port as illustrated below. Figure 4-2. Setting of Each Register and Pin Function Port mode Output mode "0" PMn register Input mode "1" Alternate function (when two alternate functions are available) "0"...
Page 68 CHAPTER 4 PORT FUNCTIONS (7) Cautions for controlling ports (a) Write the same value as the fixed value to the bits fixed to 0 or 1 in the control registers. (b) To control a port where port function control register n (PFCn) and port function control expansion register m (PFCEm) exist, set as follows so as to avoid entering a setting prohibited status.
Page 69: Port 0
CHAPTER 4 PORT FUNCTIONS 4.3.1 Port 0 Port 0 is a 5-bit port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate functions. Table 4-4. Port 0 Alternate-Function Pins Pin Name Pin No. Alternate Function Remark Block Type...
Page 70 CHAPTER 4 PORT FUNCTIONS (3) Port 0 mode control register (PMC0) After reset: 00H Address: FFFFF440H PMC0 PMC06 PMC05 PMC04 PMC03 PMC02 PMC06 P06 pin operation mode specification I/O port INTP3 input PMC05 P05 pin operation mode specification I/O port INTP2 input PMC04 P04 pin operation mode specification...
Page 71: Port 1
CHAPTER 4 PORT FUNCTIONS 4.3.2 Port 1 Port 1 is a 2-bit port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate functions. Table 4-5. Port 1 Alternate-Function Pins Pin Name Pin No. Alternate Function Remark Block Type...
Page 72: Port 3
CHAPTER 4 PORT FUNCTIONS 4.3.3 Port 3 Port 3 is an 8-bit port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate functions. Table 4-6. Port 3 Alternate-Function Pins Pin Name Pin No. Alternate Function Remark Block Type...
Page 73 CHAPTER 4 PORT FUNCTIONS (2) Port 3 mode register (PM3) After reset: FFFFH Address: PM3 FFFFF426H, PM3L FFFFF426H, PM3H FFFFF427H Note PM3 (PM3H PM39 PM38 (PM3L) PM35 PM34 PM33 PM32 PM31 PM30 PM3n I/O mode control (n = 0 to 5, 8, 9) Output mode Input mode Note To read/write bits 8 to 15 of the PM3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of...
Page 74 CHAPTER 4 PORT FUNCTIONS (3) Port 3 mode control register (PMC3) After reset: 0000H Address: PMC3 FFFFF446H, PMC3L FFFFF446H, PMC3H FFFFF447H Note PMC3 (PMC3H PMC39 PMC38 (PMC3L) PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PMC39 Specification of P39 pin operation mode I/O port RXDA2 input PMC38...
Page 75 CHAPTER 4 PORT FUNCTIONS (4) Port 3 function control register (PFC3) After reset: 0000H Address: PFC3 FFFFF466H, PFC3L FFFFF466H PFC3 PFC35 PFC33 PFC32 PFC31 PFC30 (PFC3L) Remarks 1. The PFC3 register can be read or written only in 16-bit units. However, when using the lower 8 bits of the PFC3 register as the PFC3L register, they can be read or written in 8-bit and 1-bit units.
Page 76 CHAPTER 4 PORT FUNCTIONS (6) Port 3 alternate function specification PFC35 P35 Pin Alternate Function Specification TIP11 input TOP11 output PFC33 P33 Pin Alternate Function Specification TIP01 input TOP01 output PFCE32 PFC32 P32 Pin Alternate Function Specification ASCKA0 input SCKB4 I/O TIP00 input Setting prohibited PFC31...
Page 77: Port 4
CHAPTER 4 PORT FUNCTIONS 4.3.4 Port 4 Port 4 is a 3-bit port that controls I/O in 1-bit units. Port 4 includes the following alternate functions. Table 4-7. Port 4 Alternate-Function Pins Pin Name Pin No. Alternate Function Remark Block Type SIB0 Input <R>...
Page 78 CHAPTER 4 PORT FUNCTIONS (3) Port 4 mode control register (PMC4) After reset: 00H Address: FFFFF448H PMC4 PMC42 PMC41 PMC40 PMC42 P42 pin operation mode specification I/O port SCKB0 I/O PMC41 P41 pin operation mode specification I/O port SOB0 output PMC40 P40 pin operation mode specification I/O port...
Page 79: Port 5
CHAPTER 4 PORT FUNCTIONS 4.3.5 Port 5 Port 5 is a 6-bit port that controls I/O in 1-bit units. Port 5 includes the following alternate functions. Table 4-8. Port 5 Alternate-Function Pins Pin Name Pin No. Alternate Function Remark Block Type RTP00 Output RTP01...
Page 80 CHAPTER 4 PORT FUNCTIONS (3) Port 5 mode control register (PMC5) After reset: 00H Address: FFFFF44AH PMC5 PMC55 PMC54 PMC53 PMC52 PMC51 PMC50 PMC55 P55 pin operation mode specification I/O port Select alternate function PMC54 P54 pin operation mode specification I/O port Select alternate function PMC53...
Page 81 CHAPTER 4 PORT FUNCTIONS (5) Port 5 function control expansion register (PFCE5) After reset: 00H Address: FFFFF70AH PFCE5 PFCE55 PFCE54 PFCE53 PFCE52 PFCE51 PFCE50 Remark For details of alternate function specification, see 4.3.5 (6) Port 5 alternate function specification. User’s Manual U17031EJ2V0UD...
Page 82 CHAPTER 4 PORT FUNCTIONS (6) Port 5 alternate function specification PFCE55 PFC55 P55 Pin Alternate Function Specification Setting prohibited Setting prohibited Setting prohibited RTP05 output PFCE54 PFC54 P54 Pin Alternate Function Specification Setting prohibited Setting prohibited Setting prohibited RTP04 output PFCE53 PFC53 P53 Pin Alternate Function Specification...
Page 83: Port 7
CHAPTER 4 PORT FUNCTIONS 4.3.6 Port 7 Port 7 is an 8-bit port for which input settings can be controlled in 1-bit units. Port 7 includes the following alternate functions. Table 4-9. Port 7 Alternate-Function Pins Pin Name Pin No. Alternate Function Remark Block Type...
Page 84: Port 9
CHAPTER 4 PORT FUNCTIONS 4.3.7 Port 9 Port 9 is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate functions. Table 4-10. Port 9 Alternate-Function Pins Pin Name Pin No. Alternate Function Remark Block Type...
Page 85 CHAPTER 4 PORT FUNCTIONS (1) Port 9 register (P9) After reset: 0000H (output latch) Address: P9 FFFFF412H, P9L FFFFF412H, P9H FFFFF413H Note P9 (P9H P915 P914 P913 P912 P911 P910 (P9L) Output data control (in output mode) (n = 0 to 15) Outputs 0 Outputs 1 Note To read/write bits 8 to 15 of the P9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of...
Page 86 CHAPTER 4 PORT FUNCTIONS (3) Port 9 mode control register (PMC9) After reset: 0000H Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H Note PMC9 (PMC9H PMC915 PMC914 PMC913 (PMC9L) PMC97 PMC96 PMC95 PMC94 PMC93 PMC92 PMC915 P915 pin operation mode specification I/O port INTP6/TIP50 input PMC914...
Page 87 CHAPTER 4 PORT FUNCTIONS (4) Port 9 function control register (PFC9) After reset: 0000H Address: PFC9 FFFFF472H, PFC9L FFFFF472H, PFC9H FFFFF473H Note PFC9 (PFC9H PFC915 PFC914 PFC913 (PFC9L) PFC97 PFC96 PFC95 PFC94 PFC93 PFC92 Note To read/write bits 8 to 15 of the PFC9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PFC9H register.
Page 88 CHAPTER 4 PORT FUNCTIONS (6) Port 9 alternate function specification PFCE915 PFC915 P915 Pin Alternate Function Specification Setting prohibited INTP6 input TIP50 input Setting prohibited PFCE914 PFC914 P914 Pin Alternate Function Specification Setting prohibited INTP5 input TIP51 input TOP51 output PFC913 P913 Pin Alternate Function Specification Setting prohibited...
Page 89: Port Cm
CHAPTER 4 PORT FUNCTIONS 4.3.8 Port CM Port CM is a 4-bit port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate functions. Table 4-11. Port CM Alternate-Function Pins Pin Name Pin No. Alternate Function Remark Block Type...
Page 90 CHAPTER 4 PORT FUNCTIONS (3) Port CM mode control register (PMCCM) After reset: 00H Address: FFFFF04CH PMCCM PMCCM3 PMCCM2 PMCCM1 PMCCM0 PMCCM3 PCM3 pin operation mode specification I/O port HLDRQ input PMCCM2 PCM2 pin operation mode specification I/O port HLDAK output PMCCM1 PCM1 pin operation mode specification I/O port...
Page 91: Port Cs
CHAPTER 4 PORT FUNCTIONS 4.3.9 Port CS Port CS is a 3-bit port that can be set to the input or output mode in 1-bit units. Port CS includes the following alternate functions. Table 4-12. Port CS Alternate-Function Pins Pin Name Pin No.
Page 92 CHAPTER 4 PORT FUNCTIONS (3) Port CS mode control register (PMCCS) After reset: Address: FFFFF048H PMCCS PMCCS3 PMCCS2 PMCCS1 PMCCSn PCSn pin operation mode specification (n = 1 to 3) I/O port CSn output User’s Manual U17031EJ2V0UD...
Page 93: Port Ct
CHAPTER 4 PORT FUNCTIONS 4.3.10 Port CT Port CT is a 4-bit port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate functions. Table 4-13. Port CT Alternate-Function Pins Pin Name Pin No. Alternate Function Remark Block Type...
Page 94 CHAPTER 4 PORT FUNCTIONS (3) Port CT mode control register (PMCCT) After reset: 13H Address: FFFFF04AH PMCCT PMCCT6 PMCCT4 PMCCT1 PMCCT0 PMCCT6 PCT6 pin operation mode specification I/O port ASTB output PMCCT4 PCT4 pin operation mode specification I/O port RD output PMCCT1 PCT1 pin operation mode specification I/O port...
Page 95: Port Dh
CHAPTER 4 PORT FUNCTIONS 4.3.11 Port DH Port DH is a 6-bit port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate functions. Table 4-14. Port DH Alternate-Function Pins Pin Name Pin No. Alternate Function Remark Block Type...
Page 96 CHAPTER 4 PORT FUNCTIONS (3) Port DH mode control register (PMCDH) After reset: 3FH Address: FFFFF046H PMCDH PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 PMCDHn PDHn pin operation mode specification (n = 0 to 5) I/O port Am output (address bus output) (m = 16 to 21) User’s Manual U17031EJ2V0UD...
Page 97: Block Diagrams
CHAPTER 4 PORT FUNCTIONS Block Diagrams Figure 4-3. Block Diagram of Type A-1 A/D input signal Figure 4-4. Block Diagram of Type A-2 PMmn PORT Output latch (Pmn) Address D/A output signal User’s Manual U17031EJ2V0UD...
Page 98 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of Type B-1 PMmn PORT Output latch (Pmn) Address User’s Manual U17031EJ2V0UD...
Page 99 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of Type C-1 PMCmn PMmn PORT Output latch (Pmn) Address Input signal when alternate function is used User’s Manual U17031EJ2V0UD...
Page 100 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of Type C-2 PMCmn PMmn Output signal when alternate function is used PORT Output latch (Pmn) Address User’s Manual U17031EJ2V0UD...
Page 101 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of Type C-3 PMCmn Output buffer off signal PMmn Output signal when alternate function is used PORT Output latch (Pmn) Address User’s Manual U17031EJ2V0UD...
Page 102 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of Type D-1 PMCmn PMmn PORT Output latch (Pmn) Address Input signal when alternate function is used User’s Manual U17031EJ2V0UD...
Page 103 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of Type D-2 PMCmn PMmn Output signal when alternate function is used PORT Output latch (Pmn) Address User’s Manual U17031EJ2V0UD...
Page 104 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of Type D-3 PMCmn Output enable signal when alternate function is used PMmn Output signal when alternate function is used PORT Output latch (Pmn) Address Input signal when alternate function is used User’s Manual U17031EJ2V0UD...
Page 105 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of Type E-1 PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used PORT Output latch (Pmn) Address User’s Manual U17031EJ2V0UD...
Page 106 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of Type E-2 PFCmn PMCmn PMmn Output signal when alternate function is used PORT Output latch (Pmn) Address Input signal when alternate function is used User’s Manual U17031EJ2V0UD...
Page 107 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of Type E-3 PFCmn PMCmn PMmn PORT Output latch (Pmn) Address Input signal when alternate function is used User’s Manual U17031EJ2V0UD...
Page 108 CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of Type F-1 INTR Note INTRmn INTF Note INTFmn PMCmn PMmn PORT Output latch (Pmn) Address Noise Input signal when eliminator/ alternate function is used edge detector Note Refer to 15.4 External Interrupt Request Input Pins (NMI and INTP0 to INTP7). User’s Manual U17031EJ2V0UD...
Page 109 CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of Type F-2 PFCE PFCEmn PFCmn PMCmn Output enable signal when alternate function is used PMmn Output signal when alternate function is used PORT Output latch (Pmn) Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used...
Page 110 CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of Type F-3 PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT Output latch (Pmn) Address User’s Manual U17031EJ2V0UD...
Page 111 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of Type F-4 PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT Output latch (Pmn) Address Input signal when alternate function is used User’s Manual U17031EJ2V0UD...
Page 112 CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of Type F-5 PFCE PFCEmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT Output latch (Pmn) Address Input signal when alternate function is used User’s Manual U17031EJ2V0UD...
Page 113 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of Type F-6 PFCE PFCEmn PFCmn PMCmn PMmn PORT Output latch (Pmn) Address Input signal when alternate function is used User’s Manual U17031EJ2V0UD...
Page 114 CHAPTER 4 PORT FUNCTIONS Figure 4-21. Block Diagram of Type F-7 INTR Note INTRmn INTF Note INTFmn PFCmn PMCmn PMmn PORT Output latch (Pmn) Address Sampling Input signal 1 when Noise circuit eliminator/ alternate function is used edge detector Note Refer to 15.4 External Interrupt Request Input Pins (NMI and INTP0 to INTP7). User’s Manual U17031EJ2V0UD...
Page 115 CHAPTER 4 PORT FUNCTIONS Figure 4-22. Block Diagram of Type G-1 INTR Note INTRmn INTF Note INTFmn PFCmn PMCmn PMmn PORT Output latch (Pmn) Address Input signal 1 when Noise eliminator/ alternate function is used edge detector Input signal 2 when alternate function is used Note Refer to 15.4 External Interrupt Request Input Pins (NMI and INTP0 to INTP7).
Page 116 CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of Type G-2 INTR Note INTRmn INTF Note INTFmn PFCmn PMCmn PMmn PORT Output latch (Pmn) Address Input signal 1-1 when Noise eliminator/ alternate function is used edge detector Input signal 1-2 when alternate function is used Input signal 2 when alternate function is used...
Page 117 CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of Type G-3 INTR Note INTRmn INTF Note INTFmn PFCmn PMCmn PMmn PORT Output latch (Pmn) Address Input signal when Noise eliminator/ alternate function is used edge detector Note Refer to 15.4 External Interrupt Request Input Pins (NMI and INTP0 to INTP7). User’s Manual U17031EJ2V0UD...
Page 118 CHAPTER 4 PORT FUNCTIONS Figure 4-25. Block Diagram of Type H-1 INTR Note INTRmn INTF Note INTFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used PORT Output latch (Pmn) Address Input signal 1 when Noise eliminator/ alternate function is used edge detector...
Page 119 CHAPTER 4 PORT FUNCTIONS Figure 4-26. Block Diagram of Type H-2 INTR Note INTRmn INTF Note INTFmn PFCE PFCEmn PFCmn PMCmn PMmn PORT Output latch (Pmn) Address Input signal 1 when Noise eliminator/ alternate function is used edge detector Input signal 2 when alternate function is used Note Refer to 15.4 External Interrupt Request Input Pins (NMI and INTP0 to INTP7).
Page 120: Port Register Settings When Alternate Function Is Used
CHAPTER 4 PORT FUNCTIONS Port Register Settings When Alternate Function Is Used Table 4-15 shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of each pin. User’s Manual U17031EJ2V0UD...
Page 121 Table 4-15. Using Port Pin as Alternate-Function Pin (1/4) Pin Name Alternate Function Other Bits PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Pnx Bit of PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Pn Register Name −...
Page 122 Table 4-15. Using Port Pin as Alternate-Function Pin (2/4) Pin Name Alternate Function Other Bits PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Pnx Bit of PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Pn Register Name −...
Page 123 Table 4-15. Using Port Pin as Alternate-Function Pin (3/4) Pin Name Alternate Function Other Bits Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of (Registers) Pn Register PMn Register PMCn Register PFCEn Register PFCn Register Name TIP41 Input...
Page 124 Table 4-15. Using Port Pin as Alternate-Function Pin (4/4) Pin Name Alternate Function Other Bits Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of (Registers) PMn Register PMCn Register PFCEn Register PFCn Register Pn Register Name −...
Page 125: Cautions
CHAPTER 4 PORT FUNCTIONS Cautions 4.6.1 Cautions on setting port pins (1) Set the registers of a port in the following sequence. <1> Set PFCn and PFCEn registers. <2> Set PMCn register. <3> Set INTFn and INTRn registers. If the PFCn and PFCEn registers are set after the PMCn register is set, an unexpected peripheral function may be selected while the PFCn and PFCEn registers are being set.
Page 126: Cautions On Bit Manipulation Instruction For Port N Register (Pn)
CHAPTER 4 PORT FUNCTIONS 4.6.2 Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
Page 127: Chapter 5 Bus Control Function
CHAPTER 5 BUS CONTROL FUNCTION The V850ES/ST2 is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. Features Output is selectable from a multiplexed bus with a minimum of 3 bus cycles and a separate bus with a minimum of 2 bus cycles.
Page 128: Bus Control Pins
CHAPTER 5 BUS CONTROL FUNCTION Bus Control Pins The pins used to connect an external device are listed in the table below. Table 5-1. Bus Control Pins (Multiplexed Bus) Bus Control Pin Alternate-Function Pin Function − AD0 to AD15 Address/data bus A16 to A21 PDH0 to PDH5 Output...
Page 129: Pin Status When Internal Ram, On-Chip Peripheral I/O, Or Cs0 To Cs3 Is Accessed
CHAPTER 5 BUS CONTROL FUNCTION 5.2.1 Pin status when internal RAM, on-chip peripheral I/O, or CS0 to CS3 is accessed When the internal RAM, on-chip peripheral I/O, or CS0 to CS3 is accessed, the status of each pin is as follows. Table 5-3.
Page 130: Memory Block Function
CHAPTER 5 BUS CONTROL FUNCTION Memory Block Function The 12 MB external memory space is divided into memory blocks of (lower) 2 MB, 2 MB, 4 MB, and 4 MB. The programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units.
Page 131: Chip Select Control Function
CHAPTER 5 BUS CONTROL FUNCTION 5.3.1 Chip select control function Of the 64 MB (linear) address space, the lower 12 MB (0000000H to 0BFFFFFH) control four chip select signals, CS0 to CS3. The areas that can be selected by CS0 to CS3 are fixed. By using these chip select control functions, the memory block can be divided to enable effective use of the memory space.
Page 132: Bus Access
CHAPTER 5 BUS CONTROL FUNCTION Bus Access 5.5.1 Number of clocks for access The following table shows the number of basic clocks required for accessing each resource. Area (Bus Width) Internal RAM (32 Bits) External Memory (16 Bits) Bus Cycle Type Note 1 Note 2 Instruction fetch (normal access)
Page 133: Access By Bus Size
CHAPTER 5 BUS CONTROL FUNCTION 5.5.3 Access by bus size The V850ES/ST2 accesses the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. • The bus size of the on-chip peripheral I/O is fixed to 16 bits. •...
Page 134 CHAPTER 5 BUS CONTROL FUNCTION (2) Byte access (8 bits) (a) 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address Address 2n + 1 Byte data External data Byte data External data (b) 8-bit data bus width <1>...
Page 135 CHAPTER 5 BUS CONTROL FUNCTION (3) Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) First access Second access Address Address Address 2n + 1 2n + 1 2n + 2 Halfword data...
Page 136 CHAPTER 5 BUS CONTROL FUNCTION (4) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Second access Address Address 4n + 1 4n + 3 4n + 2 Word data External data Word data External data <2>...
Page 137 CHAPTER 5 BUS CONTROL FUNCTION (a) 16-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External data Word data External data <4>...
Page 138 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access Second access Third access Fourth access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External data Word data External data Word data...
Page 139 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Third access Fourth access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External data Word data...
Page 140: Wait Function
CHAPTER 5 BUS CONTROL FUNCTION Wait Function 5.6.1 Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle that is executed for each CSn space. The number of wait states can be programmed by using the DWC0 register.
Page 141: External Wait Function
CHAPTER 5 BUS CONTROL FUNCTION 5.6.2 External wait function To synchronize an extremely slow memory, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). Access to each area of the internal RAM and on-chip peripheral I/O is not subject to control by the external wait function, in the same manner as the programmable wait function.
Page 142 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-3. Example of Inserting Wait (a) Multiplexed bus CLKOUT WAIT pin Wait via WAIT pin Programmable wait Wait control (b) Separate bus CLKOUT WAIT pin Wait via WAIT pin Programmable wait Wait control Remark The circles indicate the sampling timing.
Page 143: Programmable Address Wait Function
CHAPTER 5 BUS CONTROL FUNCTION 5.6.4 Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address wait insertion is set for each chip select area (CS0 to CS3). If an address setup wait is inserted, it seems that the high-clock period of T1 state is extended by 1 clock.
Page 144: Idle State Insertion Function
CHAPTER 5 BUS CONTROL FUNCTION Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by the CS0 to CS3 in the multiplexed address/data bus mode. In the separate bus mode, one idle state (TI) can be inserted after the T2 state.
Page 145: Bus Hold Function
CHAPTER 5 BUS CONTROL FUNCTION Bus Hold Function 5.8.1 Functional outline The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set in the control mode. When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status).
Page 146: Bus Hold Procedure
CHAPTER 5 BUS CONTROL FUNCTION 5.8.2 Bus hold procedure The bus hold status transition procedure is shown below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited Normal status <3> End of current bus cycle <4> Shift to bus idle status <5>...
Page 147: Bus Priority
CHAPTER 5 BUS CONTROL FUNCTION Bus Priority Bus hold, instruction fetch (branch), instruction fetch (successive), and operand data accesses are executed in the external bus cycle. Bus hold has the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (successive).
Page 148: Bus Timing
CHAPTER 5 BUS CONTROL FUNCTION 5.10 Bus Timing Figure 5-4. Multiplexed Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) TASW TASW CLKOUT A21 to A16 ASTB WAIT AD15 to AD0 Idle state Programmable External wait wait 8-bit access Odd address Even address AD15 to AD8 data input Active...
Page 149 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-6. Multiplexed Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) TASW TASW CLKOUT A21 to A16 ASTB WAIT AD15 to AD0 WR1, WR0 Programmable External Idle state wait wait 8-bit access Odd address Even address AD15 to AD8 data output Active...
Page 150 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-8. Multiplexed Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT HLDRQ HLDAK A21 to A16 Undefined Undefined AD15 to AD0 Undefined Undefined ASTB 1111 1111 Note This idle state (TI) does not depend on the BCC register settings. Remarks 1.
Page 151 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-10. Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT CS3 to CS0 WAIT A21 to A0 AD15 to AD0 External Programmable Idle state wait wait 8-bit access Odd address Even address AD15 to AD8 data input Active Hi-Z...
Page 152 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-12. Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT CS3 to CS0 WAIT A21 to A0 WR1, WR0 AD15 to AD0 Programmable External Idle state wait wait 8-bit access Odd address Even address AD15 to AD8 data input Active...
Page 153 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-14. Separate Bus Hold Timing (Bus Size: 8 Bits, Write) Note Note CLKOUT HLDRQ HLDAK A21 to A0 Undefined Undefined AD7 to AD0 WR1, WR0 CS3 to CS0 1111 1111 Note This idle state (TI) does not depend on the BCC register settings. Remark The broken lines indicate high impedance.
Page 154: Chapter 6 Clock Generator
CHAPTER 6 CLOCK GENERATOR Overview The following clock generation functions are available. Clock oscillator = 10 to 17 MHz (f = 20 to 34 MHz) External clock input (X1, X2 pin input) Multiplication function (×2) by PLL (Phase Locked Loop) Internal system clock generation •...
Page 155 CHAPTER 6 CLOCK GENERATOR (1) Clock oscillator The main resonator oscillates the following frequencies (f • f = 10 to 17 MHz (2) Clock oscillator stop control This circuit generates a control signal that stops oscillation of the oscillator. Oscillation of the clock oscillator is stopped in the STOP mode. (3) Prescaler 1 This prescaler generates the clock (f to f...
Page 156: Control Registers
CHAPTER 6 CLOCK GENERATOR Control Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (refer to 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 03H.
Page 157: Operation
CHAPTER 6 CLOCK GENERATOR Operation 6.4.1 Operation of each clock The following table shows the operation status of each clock. Table 6-1. Operation Status of Each Clock During During During PLL HALT IDLE Mode STOP Operation Status Reset Oscillation Lockup Mode Mode Stabilization...
Page 158: External Clock Input Function
CHAPTER 6 CLOCK GENERATOR 6.4.3 External clock input function An external clock can be directly input to the clock oscillator. Input the clock to the X1 pin and its inverse signal to the X2 pin. Set the PCC.MFRC bit to 1 (not to use the on-chip feedback resistor). Note, however, that oscillation stabilization time is inserted even in the external clock mode.
Page 159: Chapter 7 16-Bit Timer/Event Counter P (Tmp)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Timer P (TMP) is a 16-bit timer/event counter. The V850ES/ST2 has six timer/event counter channels, TMP0 to TMP5. Overview An outline of TMPn is shown below. • Clock selection: 8 ways • Capture/trigger input pins: 2 •...
Page 160: Configuration
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Configuration TMPn includes the following hardware. Table 7-1. Configuration of TMPn Item Configuration Timer register 16-bit counter Registers TMPn capture/compare registers 0, 1 (TPnCCR0, TPnCCR1) TMPn counter read buffer register (TPnCNT) CCR0, CCR1 buffer registers Note Timer inputs 2 (TIPn0...
Page 161 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TPnCNT register. When the TPnCTL0.TPnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TPnCNT register is read at this time, 0000H is read.
Page 162: Registers
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Registers (1) TMPn control register 0 (TPnCTL0) The TPnCTL0 register is an 8-bit register that controls the operation of TMPn. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. The same value can always be written to the TPnCTL0 register by software.
Page 163 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) TMPn control register 1 (TPnCTL1) The TPnCTL1 register is an 8-bit register that controls the operation of TMPn. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: TP0CTL1 FFFFF591H, TP1CTL1 FFFFF5A1H, TP2CTL1 FFFFF5B1H, TP3CTL1 FFFFF5C1H,...
Page 164 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (3) TMPnI/O control register 0 (TPnIOC0) The TPnIOC0 register is an 8-bit register that controls the timer output (TOPn0, TOPn1 pins). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 165 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (4) TMPnI/O control register 1 (TPnIOC1) The TPnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIPn0, TIPn1 pins). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 166 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (5) TMPnI/O control register 2 (TPnIOC2) The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIPn0 pin) and external trigger input signal (TIPn0 pin). This register can be read or written in 8-bit or 1-bit units.
Page 167 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (6) TMPn option register 0 (TPnOPT0) The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 168 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (7) TMPn capture/compare register 0 (TPnCCR0) The TPnCCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS0 bit.
Page 169 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR0 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTPnCC0) is generated.
Page 170 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (8) TMPn capture/compare register 1 (TPnCCR1) The TPnCCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS1 bit.
Page 171 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR1 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is generated.
Page 172 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (9) TMPn counter read buffer register (TPnCNT) The TPnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TPnCTL0.TPnCE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units.
Page 173: Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Operation TMPn can perform the following operations. TPnCTL1.TPnEST Bit TIPn0 Pin Capture/Compare Compare Register Operation (Software Trigger Bit) (External Trigger Input) Register Setting Write Interval timer mode Invalid Invalid Compare only Anytime write Note 1 External event count mode Invalid...
Page 174 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Counter basic operation This section explains the basic operation of the 16-bit counter. For details, refer to the description of the operation in each mode. Remark n = 0 to 5 (a) Counter start operation The 16-bit counter of TMPn starts counting from the default value FFFFH in all modes.
Page 175 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Anytime write and batch write The TPnCCR0 and TPnCCR1 registers in TMPn can be rewritten during timer operation (the TPnCTL0.TPnCE bit = 1), but the write method (anytime write, batch write) of the CCR0 and CCR1 buffer registers differs depending on the mode.
Page 176 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-3. Timing of Anytime Write TPnCE bit = 1 FFFFH 16-bit counter 0000H TPnCCR0 register CCR0 buffer register 0000H TPnCCR1 register CCR1 buffer register 0000H INTTPnCC0 signal INTTPnCC1 signal Remarks 1. D : Setting values of TPnCCR0 register : Setting values of TPnCCR1 register 2.
Page 177 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Batch write In this mode, data is transferred all at once from the TPnCCR0 and TPnCCR1 registers to the CCR0 and CCR1 buffer registers during timer operation. This data is transferred upon a match between the value of the CCR0 buffer register and the value of the 16-bit counter.
Page 178 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-4. Flowchart of Basic Operation for Batch Write START Initial settings • Set values to TPnCCR0 and TPnCCR1 registers • Timer operation enable (TPnCE bit = 1) → Transfer of values of TPnCCR0 and TPnCCR1 registers to CCR0 and CCR1 buffer registers...
Page 179 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-5. Timing of Batch Write TPnCE bit = 1 FFFFH 16-bit counter 0000H TPnCCR0 register CCR0 buffer register 0000H Note 1 Note 1 Same value write TPnCCR1 register Note 2 Note 3 CCR1 buffer register 0000H Note 1...
Page 180: Interval Timer Mode (Tpnmd2 To Tpnmd0 Bits = 000)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTPnCC0) is generated at the specified interval if the TPnCTL0.TPnCE bit is set to 1. Usually, the TPnCCR1 register is not used in the interval timer mode.
Page 181 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOPn1 pin is inverted. Additionally, the set value of the TPnCCRm register is transferred to the CCRm buffer register.
Page 182 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-8. Register Setting for Interval Timer Mode Operation (2/2) (e) TMPn capture/compare register 0 (TPnCCR0) If the TPnCCR0 register is set to D , the interval is as follows. + 1) × Count clock cycle Interval = (D (f) TMPn capture/compare register 1 (TPnCCR1) The set value of the TPnCCR1 register is transferred to the CCR1 buffer register.
Page 183 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Interval timer mode operation flow Figure 7-9. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0, TPnCCR1 registers TOPn1 pin output INTTPnCC0, INTTPnCC1 signals <1> <2> <1> Count operation start flow START Initial setting of these registers is performed Register initial setting...
Page 184 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Interval timer mode operation timing (a) Operation if TPnCCR0 and TPnCCR1 registers are set to 0000H If the TPnCCR0 and TPnCCR1 registers are set to 0000H, the INTTPnCC0 and INTTPnCC1 signals are generated at each count clock, and the output of the TOPn1 pin is inverted.
Page 185 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Operation if TPnCCR0 and TPnCCR1 registers are set to FFFFH If the TPnCCR0 and TPnCCR1 registers are set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTPnCC0 and INTTPnCC1 signals are generated and the output of the TOPn1 pin is inverted.
Page 186 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Notes on rewriting TPnCCR0 and TPnCCR1 registers To change the values of the TPnCCR0 and TPnCCR1 registers to a smaller value, stop counting once and then change the set value. If the values of the TPnCCR0 and TPnCCR1 registers are rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 187 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Operation of TPnCCR1 register The following shows the operation when the TPnCCR1 register is set to a value other than the set value of the TPnCCR0 register. If the set value of the TPnCCR1 register is less than the set value of the TPnCCR0 register, the INTTPnCC1 signal is generated once per cycle.
Page 188 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the count value of the 16-bit counter does not match the value of the TPnCCR1 register. Consequently, the INTTPnCC1 signal is not generated, nor is the output of the TOPn1 pin changed.
Page 189: External Event Count Mode (Tpnmd2 To Tpnmd0 Bits = 001)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TPnCTL0.TPnCE bit is set to 1, and an interrupt request signal (INTTPnCC0) is generated each time the specified number of edges have been counted.
Page 190 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TPnCCR0 register is transferred to the CCR0 buffer register.
Page 191 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-14. Register Setting for Operation in External Event Count Mode (2/2) (e) TMPn counter read buffer register (TPnCNT) The count value of the 16-bit counter can be read by reading the TPnCNT register. (f) TMPn capture/compare register 0 (TPnCCR0) If D is set to the TPnCCR0 register, the counter is cleared and a compare match interrupt request...
Page 192 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) External event count mode operation flow Figure 7-15. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers...
Page 193 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in external event count mode Caution In the external event count mode, setting the TPnCCR0 and TPnCCR1 registers to 0000H is prohibited. (a) Operation if TPnCCR0 register is set to FFFFH If the TPnCCR0 register is set to FFFFH, the 16-bit counter counts to FFFFH each time the valid edge of the external event count signal has been detected.
Page 194 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Notes on rewriting TPnCCR0 register To change the value of the TPnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 195 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Operation of TPnCCR1 register Figure 7-16. Configuration of TPnCCR1 Register TPnCCR1 register Output TOPn1 pin CCR1 buffer register controller Match signal INTTPnCC1 signal Clear Edge TIPn0 pin 16-bit counter detector Match signal INTTPnCC0 signal TPnCE bit CCR0 buffer register...
Page 196 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the INTTPnCC1 signal is not generated because the count value of the 16-bit counter and the value of the TPnCCR1 register do not match.
Page 197: External Trigger Pulse Output Mode (Tpnmd2 To Tpnmd0 Bits = 010)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter P starts counting, and outputs a PWM waveform from the TOPn1 pin.
Page 198 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-20. Basic Timing in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TPnCCR1 register INTTPnCC1 signal TOPn1 pin output Wait Active level Active level...
Page 199 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-21. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1.
Page 200 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-21. Setting of Registers in External Trigger Pulse Output Mode (2/2) (d) TMPnI/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 Select valid edge of external trigger input Select valid edge of external event count input (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register.
Page 201 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in external trigger pulse output mode Figure 7-22. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register CCR0 buffer register INTTPnCC0 signal...
Page 202 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-22. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <3> PnCCR0, TPnCCR1 register setting change flow Only writing of the TPnCCR1 START register must be performed when the set duty factor is changed.
Page 203 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 register last. Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC0 signal is detected. FFFFH 16-bit counter 0000H...
Page 204 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) In order to transfer data from the TPnCCRm register to the CCRm buffer register, the TPnCCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TPnCCR0 register and then set the active level width to the TPnCCR1 register.
Page 205 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is FFFFH, the INTTPnCC1 signal is generated periodically. Count clock −...
Page 206 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Conflict between trigger detection and match with TPnCCR1 register If the trigger is detected immediately after the INTTPnCC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOPn1 pin is asserted, and the counter continues counting.
Page 207 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Conflict between trigger detection and match with TPnCCR0 register If the trigger is detected immediately after the INTTPnCC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOPn1 pin is extended by time from generation of the INTTPnCC0 signal to trigger detection.
Page 208 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the external trigger pulse output mode differs from the timing of other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 209: One-Shot Pulse Output Mode (Tpnmd2 To Tpnmd0 Bits = 011)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter P starts counting, and outputs a one-shot pulse from the TOPn1 pin.
Page 210 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-24. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TPnCCR1 register INTTPnCC1 signal TOPn1 pin output Delay Active Delay Active...
Page 211 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-25. Setting of Registers in One-Shot Pulse Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1. (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 212 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-25. Setting of Registers in One-Shot Pulse Output Mode (2/2) (d) TMPnI/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 Select valid edge of external trigger input Select valid edge of external event count input (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register.
Page 213 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in one-shot pulse output mode Figure 7-26. Software Processing Flow in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TPnCCR1 register INTTPnCC1 signal TOPn1 pin output...
Page 214 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TPnCCRm register To change the set value of the TPnCCRm register to a smaller value, stop counting once, and then change the set value.
Page 215 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Generation timing of compare match interrupt request signal (INTTPnCC1) The generation timing of the INTTPnCC1 signal in the one-shot pulse output mode is different from other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 216: Pwm Output Mode (Tpnmd2 To Tpnmd0 Bits = 100)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOPn1 pin when the TPnCTL0.TPnCE bit is set to 1. Figure 7-27. Configuration in PWM Output Mode TPnCCR1 register Transfer Output...
Page 217 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-28. Basic Timing in PWM Output Mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output Active period Cycle Inactive period −...
Page 218 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-29. Register Setting in PWM Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1. (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 219 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-29. Register Setting in PWM Output Mode (2/2) (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register. (f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1) If D is set to the TPnCCR0 register and D to the TPnCCR1 register, the cycle and active level of the...
Page 220 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in PWM output mode Figure 7-30. Software Processing Flow in PWM Output Mode (1/2) FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output <1>...
Page 221 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-30. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <3> TPnCCR0, TPnCCR1 register setting change flow (only duty is changed) START Only writing of the TPnCCR1 register must be performed when the set duty factor is changed.
Page 222 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 register last. Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC1 signal is detected. FFFFH 16-bit counter 0000H...
Page 223 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is FFFFH, the INTTPnCC1 signal is generated periodically. Count clock −...
Page 224 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the PWM output mode differs from the timing of other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 225: Free-Running Timer Mode (Tpnmd2 To Tpnmd0 Bits = 101)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. At this time, the TPnCCR0 and TPnCCR1 registers can be used as a compare register or a capture register, depending on the setting of the TPnOPT0.TPnCCS0 and TPnOPT0.TPnCCS1 bits.
Page 226 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signal of the TOPn1 pin is inverted. When the count value of the 16-bit counter later matches the set value of the TPnCCRm register, a compare match interrupt request signal (INTTPnCCm) is generated.
Page 227 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPnm pin is detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and a capture interrupt request signal (INTTPnCCm) is generated.
Page 228 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-34. Register Setting in Free-Running Timer Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1 (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 229 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-34. Register Setting in Free-Running Timer Mode (2/2) (e) TMPnI/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 Select valid edge of external event count input (f) TMPn option register 0 (TPnOPT0) TPnCCS1 TPnCCS0 TPnOVF...
Page 230 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 7-35. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal TPnCCR1 register...
Page 231 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-35. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TPnCTL0 register is performed before setting the (TPnCKS0 to TPnCKS2 bits) TPnCE bit to 1.
Page 232 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) When using capture/compare register as capture register Figure 7-36. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TPnCE bit TIPn0 pin input TPnCCR0 register 0000 0000 INTTPnCC0 signal TIPn1 pin input 0000...
Page 233 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-36. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TPnCTL0 register is performed before setting the (TPnCKS0 to TPnCKS2 bits) TPnCE bit to 1.
Page 234 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter P is used as an interval timer with the TPnCCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTPnCCm signal has been detected.
Page 235 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TPnCCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTPnCCm signal has been detected and for calculating an interval.
Page 236 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two capture registers are used FFFFH 16-bit counter...
Page 237 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TPnCE bit INTTPnOV signal TPnOVF bit Note TPnOVF0 flag TIPn0 pin input TPnCCR0 register Note TPnOVF1 flag TIPn1 pin input TPnCCR1 register <1>...
Page 238 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TPnCE bit INTTPnOV signal TPnOVF bit Note TPnOVF0 flag TIPn0 pin input TPnCCR0 register Note TPnOVF1 flag TIPn1 pin input TPnCCR1 register <1>...
Page 239 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
Page 240 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Example when capture trigger interval is long FFFFH 16-bit counter 0000H TPnCE bit TIPnm pin input TPnCCRm register INTTPnOV signal TPnOVF bit Overflow 2H 0H Note counter 1 cycle of 16-bit counter Pulse width <1>...
Page 241: Pulse Width Measurement Mode (Tpnmd2 To Tpnmd0 Bits = 110)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. Each time the valid edge input to the TIPnm pin has been detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and the 16-bit counter is cleared to 0000H.
Page 242 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-38. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPnCE bit TIPnm pin input 0000H TPnCCRm register INTTPnCCm signal INTTPnOV signal Cleared to 0 by CLR instruction TPnOVF bit Remark n = 0 to 5 m = 0, 1...
Page 243 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-39. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note Setting is invalid when the TPnCTL1.TPnEEE bit = 1. (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 244 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-39. Register Setting in Pulse Width Measurement Mode (2/2) (e) TMPn option register 0 (TPnOPT0) TPnCCS1 TPnCCS0 TPnOVF TPnOPT0 Overflow flag (f) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register. (g) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1) These registers store the count value of the 16-bit counter when the valid edge input to the TIPn0 and TIPn1 pins is detected.
Page 245 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in pulse width measurement mode Figure 7-40. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPnCE bit TIPn0 pin input 0000H 0000H TPnCCR0 register INTTPnCC0 signal <1>...
Page 246: Timer Output Operations
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 using the CLR instruction after reading to confirm that the TPnOVF bit = 1 or by writing 8-bit data (bit 0 is 0) to the TPnOPT0 register after reading to confirm that the TPnOVF bit = 1.
Page 247: Cautions
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Cautions (1) Capture operation When using the capture operation and selecting the slow clock as the count clock, if the capture trigger is input immediately after the TP0CE bit is set to 1, FFFFH instead of 0000H may be captured to the TPnCCR0 and TPnCCR1 registers.
Page 248: Chapter 8 16-Bit Interval Timer M (Tmm)
CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) Outline • Interval function • 8 clocks selectable • 16-bit counter × 1 (The 16-bit counter cannot be read during timer count operation.) • Compare register × 1 (The compare register cannot be written during timer counter operation.) •...
Page 249 CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) (1) 16-bit counter This is a 16-bit counter that counts the internal clock. The 16-bit counter cannot be read or written. (2) TMM0 compare register 0 (TM0CMP0) The TM0CMP0 register is a 16-bit compare register. This register can be read or written in 16-bit units.
Page 250: Control Register
CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) Control Register (1) TMM0 control register (TM0CTL0) The TM0CTL0 register is an 8-bit register that controls the TMM0 operation. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. The same value can always be written to the TM0CTL0 register by software.
Page 251: Operation
CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) Operation 8.4.1 Interval timer mode In the interval timer mode, an interrupt request signal (INTTM0EQ0) is generated at the specified interval if the TM0CTL0.TM0CE bit is set to 1. Figure 8-2. Configuration of Interval Timer Clear Count clock INTTM0EQ0 signal...
Page 252 CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) When the TM0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. When the count value of the 16-bit counter matches the value of the TM0CMP0 register, the 16-bit counter is cleared to 0000H, and a compare match interrupt request signal (INTTM0EQ0) is generated.
Page 253 CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) (1) Interval timer mode operation flow Figure 8-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TM0CE bit TM0CMP0 register INTTM0EQ0 signal <1> <2> <1> Count operation start flow START Initial setting of these registers is performed before setting the TM0CE bit to 1.
Page 254 CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) (2) Interval timer mode operation timing (a) Operation if TM0CMP0 register is set to 0000H If the TM0CMP0 register is set to 0000H, the INTTM0EQ0 signal is generated at each count clock. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter FFFFH...
Page 255: Cautions
CHAPTER 8 16-BIT INTERVAL TIMER M (TMM) Cautions (1) Error on starting timer It takes one clock to generate the first compare match interrupt request signal (INTTM0EQ0) after the TM0CTL0.TM0CE bit is changed from 0 to 1 and TMM0 is started. This is because the value of the 16-bit counter is FFFFH when the TM0CE bit = 0 and TMM0 is started asynchronously to the count clock.
Page 256: Chapter 9 Watchdog Timer Functions
CHAPTER 9 WATCHDOG TIMER FUNCTIONS Functions The watchdog timer has the following operation modes. • Watchdog timer • Interval timer The following functions are realized from the above-listed operation modes. • Generation of non-maskable interrupt request signal (INTWDT) upon overflow of watchdog timer •...
Page 257: Configuration
CHAPTER 9 WATCHDOG TIMER FUNCTIONS Configuration The block diagram of the watchdog timer is shown below. Figure 9-1. Block Diagram of Watchdog Timer Clear 13-bit division circuit Clear 8-bit counter INTWDTM Output INTWDT control WDTRES WDCS0 to WDCS2 WDTM3, WDTM4 Remark INTWDTM: Request signal for maskable interrupt through WDT overflow INTWDT:...
Page 258: Control Registers
CHAPTER 9 WATCHDOG TIMER FUNCTIONS Control Registers (1) Watchdog timer clock selection register (WDCS) The WDCS register sets the overflow time of the watchdog timer and the interval timer. This register can be read or written in 8-bit units. Reset input clears WDCS to 00H. After reset: Address: FFFF6C1H...
Page 259 CHAPTER 9 WATCHDOG TIMER FUNCTIONS (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operation mode and enables/disables count operations. This register is a special register that can be written only in a special sequence (refer to 3.4.7 Special registers).
Page 260: Operation
CHAPTER 9 WATCHDOG TIMER FUNCTIONS Operation 9.4.1 Operation as watchdog timer Watchdog timer operation to detect a program loop is selected by setting the WDTM.WDTM4 bit to 1. The count clock (program loop detection time interval) of the watchdog timer can be selected with bits WDCS.WDCS0 to WDCS.WDCS2.
Page 261: Operation As Interval Timer
CHAPTER 9 WATCHDOG TIMER FUNCTIONS 9.4.2 Operation as interval timer The watchdog timer can be made to operate as an interval timer that repeatedly generates interrupts using the count value set in advance as the interval, by setting the WDTM.WDTM4 bit to 0. When the watchdog timer operates as an interval timer, the WDTIC.WDTMK flag and priority specification flags (WDTIC.WDTPR0 to WDTIC.WDTPR2 bits) are valid and maskable interrupt request signal (INTWDTM) can be generated.
Page 262: Chapter 10 Real-Time Output Function (Rto)
CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) 10.1 Function The real-time output function transfers preset data to the RTBL0 and RTBH0 registers, and then transfers this data by hardware to an external device via the output latches, upon occurrence of a timer interrupt. The pins through which the data is output to an external device constitute a port called the real-time output function (RTO).
Page 263: Configuration
CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) 10.2 Configuration The block diagram of RTO is shown below. Figure 10-1. Block Diagram of RTO Real-time output Real-time output buffer register 0H RTP04, latch 0H (RTBH0) RTP05 Real-time output Real-time output buffer register 0L RTP00 to latch 0L (RTBL0)
Page 264 CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) (1) Real-time output buffer registers 0L, 0H (RTBL0, RTBH0) The RTBL0 and RTBH0 registers are 4-bit registers that hold preset output data. These registers are mapped to independent addresses in the peripheral I/O register area. These registers can be read or written in 8-bit or 1-bit units.
Page 265: Control Registers
CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) 10.3 Control Registers RTO is controlled using the following two registers. • Real-time output port mode register 0 (RTPM0) • Real-time output port control register 0 (RTPC0) Remark When using the RTP00 to RTP05 pin function, refer to Table 4-15 Using Port Pin as Alternate- Function Pin.
Page 266 CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register 0 (RTPC0) The RTPC0 register is a register that sets the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Table 10-3.
Page 267: Operation
CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) 10.4 Operation If the real-time output operation is enabled by setting the RTPC0.RTPOE0 bit to 1, the data of the RTBH0 and RTBL0 registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the RTPC0.EXTR0 and RTPC0.BYTE0 bits).
Page 268: Usage
CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) 10.5 Usage (1) Disable real-time output. Clear the RTPC0.RTPOE0 bit to 0. (2) Perform initialization as follows. • Set the alternate-function pins of port 5 Set the PFC5.PFC5n bit and PFCE5.PFCE5n bit to 1, and then set the PMC5.PMC5n bit to 1 (n = 0 to 5). •...
Page 269: Chapter 11 A/D Converter
CHAPTER 11 A/D CONVERTER 11.1 Overview The A/D converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 8 channels of analog input signals (ANI0 to ANI7). The A/D converter has the following features. 10-bit resolution 8 channels Successive approximation method...
Page 270: Configuration
CHAPTER 11 A/D CONVERTER 11.3 Configuration The block diagram of the A/D converter is shown below. Figure 11-1. Block Diagram of A/D Converter REF0 ADA0CE bit ANI0 Sample & hold circuit ANI1 ANI2 ANI3 ANI4 ANI5 ADA0CE bit ANI6 Voltage ANI7 comparator ADA0CR0...
Page 271 CHAPTER 11 A/D CONVERTER (1) Successive approximation register (SAR) This register compares the voltage value of the analog input signal with the voltage tap (compare voltage) value from the series resistor string, and holds the comparison result starting from the most significant bit (MSB).
Page 272 CHAPTER 11 A/D CONVERTER (10) AV REF0 This is the pin used to input the reference voltage of the A/D converter. The signals input to the ANI0 to ANI7 pins are converted to digital signals based on the voltage applied between the AV and AV pins.
Page 273: Registers
CHAPTER 11 A/D CONVERTER 11.4 Registers The A/D converter is controlled by the following registers. • A/D converter mode registers 0, 1 (ADA0M0, ADA0M1) • A/D converter channel specification register (ADA0S) In addition, the following register is also used. • A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH) User’s Manual U17031EJ2V0UD...
Page 274 CHAPTER 11 A/D CONVERTER (1) A/D converter mode register 0 (ADA0M0) This is an 8-bit register used to specify the operation mode and to control conversion operation. This register can be read or written in 8-bit or 1-bit units. However, the ADA0EF bit is a read-only bit. Reset input clears this register to 00H.
Page 275 CHAPTER 11 A/D CONVERTER (2) A/D converter mode register 1 (ADA0M1) This is an 8-bit register used to specify the conversion time. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFF201H ADA0M1...
Page 276 CHAPTER 11 A/D CONVERTER Table 11-3. High-Speed Conversion Mode Setting Examples ADA0FR3 ADA0FR2 ADA0FR1 ADA0FR0 = 34 MHz = 32 MHz = 20 MHz A/D Conversion A/D Conversion Note 1 Note 2 Time Time 26/f 13/f Setting prohibited Setting prohibited Setting prohibited μ...
Page 277 CHAPTER 11 A/D CONVERTER (4) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH) The ADA0CRn and ADA0CRnH registers store the A/D conversion results. These registers are read-only, in 16-bit or 8-bit units. However, specify the ADA0CRn register for 16-bit access and the ADA0CRnH register for 8-bit access.
Page 278 CHAPTER 11 A/D CONVERTER The relationship between the analog voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (ADA0CRn register) is as follows. × 1,024 + 0.5) SAR = INT ( REF0 = SAR × 64 Note ADA0CR REF0...
Page 279: Operation
CHAPTER 11 A/D CONVERTER 11.5 Operation 11.5.1 Basic operation <1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADA0M0, ADA0M1, and ADA0S registers. When the ADA0M0.ADA0CE bit is set, conversion is started in the software trigger mode and the A/D converter waits for a trigger in the external trigger mode.
Page 280 CHAPTER 11 A/D CONVERTER Figure 11-3. A/D Converter Basic Operation Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADA0CRn result INTAD User’s Manual U17031EJ2V0UD...
Page 281: Trigger Mode
CHAPTER 11 A/D CONVERTER 11.5.2 Trigger mode The timing of starting the conversion operation is specified by setting a trigger mode. The trigger mode includes a software trigger mode and external trigger modes. The ADA0M0.ADA0TMD bit is used to set the trigger mode. (1) Software trigger mode When the ADA0M0.ADA0CE bit is set to 1, the signal of the analog input pin (ANI0 to ANI7 pins) specified by the ADA0S register is converted.
Page 282: Operation Mode
CHAPTER 11 A/D CONVERTER 11.5.3 Operation mode Four operation modes are available as the modes in which to set the ANI0 to ANI7 pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. The operation mode is selected by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits. (1) Continuous select mode In this mode, the voltage of one analog input pin selected by the ADA0S register is continuously converted into a digital value.
Page 283 CHAPTER 11 A/D CONVERTER Figure 11-5. Timing Example of Continuous Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data 1 Data ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7...
Page 284 CHAPTER 11 A/D CONVERTER (3) One-shot select mode In this mode, the voltage on the analog input pin specified by the ADA0S register is converted into a digital value only once. The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an analog input pin and an ADA0CRn register correspond on a one-to-one basis.
Page 285 CHAPTER 11 A/D CONVERTER Figure 11-7. Timing Example of One-Shot Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data Data 1 ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 conversion (ANI0) (ANI1)
Page 286: Cautions
CHAPTER 11 A/D CONVERTER 11.6 Cautions (1) When A/D converter is not used When the A/D converter is not used, the power consumption can be reduced by clearing the ADA0M0.ADA0CE bit to 0. (2) Input range of ANI0 to ANI7 pins Input the voltage within the specified range to the ANI0 to ANI7 pins.
Page 287 CHAPTER 11 A/D CONVERTER (5) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the ADA0S register are changed. If the analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ADA0S register is rewritten.
Page 288 CHAPTER 11 A/D CONVERTER (6) AV REF0 (a) The AV pin is used as the power supply pin of the A/D converter and also supplies power to the REF0 alternate-function ports. In an application where a backup power supply is used, be sure to supply the same voltage as V to the AV pin as shown in Figure 11-10.
Page 289 CHAPTER 11 A/D CONVERTER <R> (10) A/D conversion result hysteresis characteristics Successive comparison type A/D converters hold an analog input voltage in an internal sample & hold capacitor and then perform A/D conversion. After the A/D conversion has finished, the analog input voltage remains in the internal sample &...
Page 290: How To Read A/D Converter Characteristics Table
CHAPTER 11 A/D CONVERTER 11.7 How to Read A/D Converter Characteristics Table This section describes the terms related to the A/D converter. (1) Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit).
Page 291 CHAPTER 11 A/D CONVERTER (3) Quantization error This is an error of ±1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because the A/D converter converts analog input voltages in a range of ±1/2 LSB into the same digital codes, a quantization error is unavoidable.
Page 292 CHAPTER 11 A/D CONVERTER (5) Full-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1…110 to 1…111 (full scale − 3/2 LSB). Figure 11-14. Full-Scale Error Full-scale error 2 AV REF0 −...
Page 293 CHAPTER 11 A/D CONVERTER (7) Integral linearity error This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0.
Page 294: Chapter 12 D/A Converter
CHAPTER 12 D/A CONVERTER 12.1 Functions The D/A converter has the following functions. 8-bit resolution × 2 channels (DA0CS0, DA0CS1) R-2R ladder method μ <R> Conversion time: 3 s max. (AV = 3.0 to 3.6 V) REF1 × m/256 (m = 0 to 255; value set to DA0CSn register) Analog output voltage: AV REF1 Operation modes: Normal mode, real-time output mode...
Page 295: Control Registers
CHAPTER 12 D/A CONVERTER The D/A converter consists of the following hardware. Table 12-1. Configuration of D/A Converter Item Configuration Control registers D/A converter mode register (DA0M) D/A conversion value setting registers 0, 1 (DA0CS0, DA0CS1) 12.3 Control Registers The registers that control the D/A converter are as follows. •...
Page 296 CHAPTER 12 D/A CONVERTER (2) D/A conversion value setting registers 0, 1 (DA0CS0, DA0CS1) The DA0CS0 and DA0CS1 registers set the analog voltage value output to the ANO0 and ANO1 pins. These registers can be read or written in 8-bit units. Reset input clears these registers to 00H.
Page 297: Operation
CHAPTER 12 D/A CONVERTER 12.4 Operation 12.4.1 Operation in normal mode D/A conversion is performed using a write operation to the DA0CSn register as the trigger. The setting method is described below. <1> Set the DA0MDn bit of the DA0M register to 0 (normal mode). <2>...
Page 298: Cautions
CHAPTER 12 D/A CONVERTER 12.4.3 Cautions Observe the following cautions when using the D/A converter of the V850ES/ST2. (1) Do not change the set value of the DA0CSn register while the trigger signal is being issued in the real-time output mode. (2) Before changing the operation mode, be sure to clear the DA0M.DA0CEn bit to 0.
Page 299: Chapter 13 Asynchronous Serial Interface A (Uarta)
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 13.1 CSIB4 and UARTA0 Mode Switching In the V850ES/ST2, CSIB4 and UARTA0 are alternate functions of the same pin and therefore cannot be used simultaneously. CSIB4 and UARTA0 switching must be set in advance using PMC3, PFC3, and PFCE3L registers. Cautions 1.
Page 300: Features
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 13.2 Features Transfer speed: 300 bps to 312.5 kbps (using internal system clock of 34 MHz and dedicated baud rate generator) Full-duplex communication: Internal UARTA receive data register n (UAnRX) Internal UARTA transmit data register n (UAnTX) 2-pin configuration: TXDAn: Transmit data output pin RXDAn: Receive data input pin...
Page 301: Configuration
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 13.3 Configuration The block diagram of the UARTAn is shown below. Figure 13-2. Block Diagram of Asynchronous Serial Interface An Internal bus INTUAnT INTUAnR Transmission Reception unit UAnRX UAnTX unit Receive Transmit Transmission Reception shift register shift register...
Page 302 CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register used to specify the UARTAn operation. (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register used to select the base clock for the UARTAn. (3) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is an 8-bit register used to control the baud rate for the UARTAn.
Page 303: Control Registers
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 13.4 Control Registers (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register that controls the UARTAn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 10H.
Page 304 CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2/2) UAnDIR Transfer direction selection MSB-first transfer LSB-first transfer This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit = the UAnRXE bit = 0. UAnPS1 UAnPS0 Parity selection during transmission Parity selection during reception No parity output Reception with no parity...
Page 305 CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2) UARTAn control register 1 (UAnCTL1) For details, see 13.7 (2) UARTAn control register 1 (UAnCTL1). (3) UARTAn control register 2 (UAnCTL2) For details, see 13.7 (3) UARTAn control register 2 (UAnCTL2). (4) UARTAn option control register 0 (UAnOPT0) The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTAn register.
Page 306 CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) After reset: 00H Address: UA0STR FFFFFA04H, UA2STR FFFFFA24H <2> <1> <7> <0> UAnSTR UAnTSF UAnPE UAnFE UAnOVE (n = 0, 2) UAnTSF Transfer status flag • When the UAnPWR bit = 0 or the UAnTXE bit = 0 has been set. •...
Page 307 CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) UARTAn receive data register (UAnRX) The UAnRX register is an 8-bit buffer register that stores parallel data converted by the receive shift register. The data stored in the receive shift register is transferred to the UAnRX register upon completion of reception of 1 byte of data.
Page 308: Interrupt Request Signals
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 13.5 Interrupt Request Signals The following two interrupt request signals are generated from UARTAn. • Reception complete interrupt request signal (INTUAnR) • Transmission enable interrupt request signal (INTUAnT) The default priority for these two interrupt request signals is reception complete interrupt request signal then transmission enable interrupt request signal.
Page 309: Operation
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 13.6 Operation 13.6.1 Data format Full-duplex serial data reception and transmission is performed. As shown in Figure 13-3, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s).
Page 310 CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 13-3. UARTA Transmit/Receive Data Format (a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start Parity Stop (b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start Parity...
Page 311: Uart Transmission
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 13.6.2 UART transmission A high level is output to the TXDAn pin by setting the UAnCTL0.UAnPWR bit to 1. Next, the transmission enabled status is set by setting the UAnCTL0.UAnTXE bit to 1, and transmission is started by writing transmit data to the UAnTX register.
Page 312: Continuous Transmission Procedure
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 13.6.3 Continuous transmission procedure UARTAn can write the next transmit data to the UAnTX register when the UARTAn transmit shift register starts the shift operation. The transmit timing of the UARTAn transmit shift register can be judged from the transmission enable interrupt request signal (INTUAnT).
Page 313 CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 13-6. Continuous Transmission Operation Timing (a) Transmission start Start Data (1) Parity Stop Start Data (2) Parity Stop Start TXDAn pin UAnTX register Data (1) Data (2) Data (3) Transmission Data (2) Data (1) shift register INTUAnT signal...
Page 314: Uart Reception
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 13.6.4 UART reception The reception wait status is set by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1. In the reception wait status, the RXDAn pin is monitored and start bit detection is performed. Start bit detection is performed using a two-step detection routine.
Page 315: Reception Errors
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 13.6.5 Reception errors Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. Data reception result error flags are set in the UAnSTR register and a reception complete interrupt request signal (INTUAnR) is output when an error occurs.
Page 316: Parity Types And Operations
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 13.6.6 Parity types and operations The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side. In the case of even parity and odd parity, it is possible to detect odd-count bit errors. In the case of 0 parity and no parity, errors cannot be detected.
Page 317: Receive Data Noise Filter
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 13.6.7 Receive data noise filter This filter samples the RXDAn pin using the base clock of the prescaler output. When the same sampling value is read twice, the match detector output changes and the RXDAn signal is sampled as the input data.
Page 318: Dedicated Baud Rate Generator
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 13.7 Dedicated Baud Rate Generator The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel.
Page 319 CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register that selects the UARTAn base clock. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Caution Clear the UAnCTL0.UAnPWR bit to 0 before rewriting the UAnCTL1 register.
Page 320 CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (3) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTAn. This register can be read or written in 8-bit units. Reset input sets this register to FFH.
Page 321 CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (4) Baud rate The baud rate is obtained by the following equation. UCLK Baud rate = [bps] 2 × k = Frequency of base clock selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits UCLK k = Value set using the UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (k = 4, 5, 6, ..., 255) (5) Baud rate error The baud rate error is obtained by the following equation.
Page 322 CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) Baud rate setting example <R> Table 13-3. Baud Rate Generator Setting Data Baud Rate = 34 MHz = 33.8 MHz = 20 MHz (bps) UAnCTL1 UAnCTL2 ERR (%) UAnCTL1 UAnCTL2 ERR (%) UAnCTL1 UAnCTL2 ERR (%)
Page 323 CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (7) Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below. Caution The baud rate error during reception must be set within the allowable error range using the following equation.
Page 324 CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Therefore, the maximum baud rate that can be received by the destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, obtaining the following maximum allowable transfer rate yields the following. 21k −...
Page 325: Cautions
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (8) Baud rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result.
Page 326: Chapter 14 3-Wire Variable-Length Serial I/O (Csib)
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 14.1 CSIB4 and UARTA0 Mode Switching In the V850ES/ST2, CSIB4 and UARTA0 are alternate functions of the same pin and therefore cannot be used simultaneously. CSIB4 and UARTA0 switching must be set in advance using the PMC3, PFC3, and PFCE3L registers. Cautions 1.
Page 327: Features
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 14.2 Features Transfer rate: 8.5 Mbps to 265.6 kbps (f = 34 MHz, using internal clock) Master mode and slave mode selectable 8-bit to 16-bit transfer, 3-wire serial interface Interrupt request signals (INTCBnT, INTCBnR) × 2 Serial clock and data phase switchable Transfer data length selectable in 1-bit units between 8 and 16 bits Transfer data MSB-first/LSB-first switchable...
Page 328: Configuration
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 14.3 Configuration The following shows the block diagram of CSIBn. Figure 14-2. Block Diagram of CSIBn Internal bus CBnCTL1 CBnCTL0 CBnCTL2 CBnSTR INTCBnT Controller INTCBnR Phase control /128 CBnTX SCKBn Phase SO latch SOBn control SIBn...
Page 329 CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) CSIBn receive data register (CBnRX) The CBnRX register is a 16-bit buffer register that holds receive data. This register is read-only, in 16-bit units. The receive operation is started by reading the CBnRX register in the reception enabled status. If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CBnRXL register.
Page 330: Control Registers
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 14.4 Control Registers The following registers are used to control CSIBn. • CSIBn control register 0 (CBnCTL0) • CSIBn control register 1 (CBnCTL1) • CSIBn control register 2 (CBnCTL2) • CSIBn status register (CBnSTR) (1) CSIBn control register 0 (CBnCTL0) CBnCTL0 is a register that controls the CSIBn serial transfer operation.
Page 331 CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) Note 1 CBnDIR Specification of transfer direction mode (MSB/LSB) MSB first LSB first Note 1 CBnTMS Transfer mode specification Single transfer mode Continuous transfer mode CBnSCE Specification of start transfer disable/enable Communication start trigger invalid Communication start trigger valid •...
Page 332 CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) CSIBn control register 1 (CBnCTL1) CBnCTL1 is an 8-bit register that controls the CSIBn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Caution The CBnCTL1 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0.
Page 333 CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (3) CSIBn control register 2 (CBnCTL2) CBnCTL2 is an 8-bit register that controls the number of CSIBn serial transfer bits. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Caution The CBnCTL2 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0 or when both the CBnTXE and CBnRXE bits = 0.
Page 334 CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (a) Transfer data length change function The CSIBn transfer data length can be set in 1-bit units between 8 and 16 bits using the CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits. When the transfer bit length is set to a value other than 16 bits, set the data to the CBnTX or CBnRX register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB.
Page 335 CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (4) CSIBn status register (CBnSTR) CBnSTR is an 8-bit register that indicates the CSIBn status. This register can be read or written in 8-bit or 1-bit units, but the CBnTSF flag is read-only. Reset input clears this register to 00H.
Page 336: Operation
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 14.5 Operation 14.5.1 Single transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (refer to 14.4 (2) CSIBn control register 1 (CBnCTL1), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) CBnTX write (55H) CBnRX read (AAH) SCKBn pin...
Page 337: Single Transfer Mode (Master Mode, Reception Mode)
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 14.5.2 Single transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (refer to 14.4 (2) CSIBn control register 1 (CBnCTL1), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) CBnRX read (55H) CBnRX read (AAH) SCKBn pin...
Page 338: Continuous Mode (Master Mode, Transmission/Reception Mode)
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 14.5.3 Continuous mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 3 (refer to 14.4 (2) CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) CBnTX register SCKBn pin SOBn pin...
Page 339: Continuous Mode (Master Mode, Reception Mode)
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 14.5.4 Continuous mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 2 (refer to 14.4 (2) CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) SCKBn pin CBnSCE bit SIBn pin...
Page 340: Continuous Reception Mode (Error)
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 14.5.5 Continuous reception mode (error) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 2 (refer to 14.4 (2) CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) SCKBn pin SIBn pin INTCBnR signal...
Page 341: Continuous Mode (Slave Mode, Transmission/Reception Mode)
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 14.5.6 Continuous mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 2 (refer to 14.4 (2) CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CSnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) CBnTX register SCKBn pin SOBn pin...
Page 342: Continuous Mode (Slave Mode, Reception Mode)
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 14.5.7 Continuous mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (refer to 14.4 (2) CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) SCKBn pin SIBn pin INTCBnR signal...
Page 343: Clock Timing
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 14.5.8 Clock timing (1/2) (i) Communication type 1 (CBnCKP = 0, CBnDAP = 0) SCKBn SIBn capture SOBn Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2 interrupt CBnTSF (ii) Communication type 3 (CBnCKP = 1, CBnDAP = 0) SCKBn SIBn capture...
Page 344 CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) (iii) Communication type 2 (CBnCKP = 0, CBnDAP = 1) SCKBn SIBn capture SOBn Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2 interrupt CBnTSF (iv) Communication type 4 (CBnCKP = 1, CBnDAP = 1) SCKBn SIBn capture...
Page 345: Output Pins
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 14.6 Output Pins (1) SCKBn pin When CSIBn operation is disabled (CBnCTL0.CBnPWR bit = 0), the SCKBn pin output status is as follows. CBnCKP CBnCKS2 CBnCKS1 CBnCKS0 SCKBn Pin Output High impedance Other than above Fixed to high level High impedance Other than above...
Page 346: Operation Flow
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 14.7 Operation Flow (1) Single transmission START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnR bit = 1? Transfer data exists? CBnPWR bit = 0 (CBnCTL0) Note Set the CBnSCE bit to 1 in the initial setting. Caution In the slave mode, data cannot be correctly transmitted if the next transfer clock is input earlier than the CBnTX register is written.
Page 347 CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Single reception START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) CBnRX register dummy read (start reception) INTCBnR bit = 1? Last data? CBnRX register read CBnSCE bit = 0 (CBnCTL0) CBnRX register read CBnPWR bit = 0 (CBnCTL0) Note Set the CBnSCE bit to 1 in the initial setting.
Page 348 CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (3) Single transmission/reception START Note 1 Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnR bit = 1? Transmission/reception Reception Transmission Read CBnRX register. Read CBnRX register. Transfer end? Transfer end? Transfer end? Note 2 Note 2...
Page 349 CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (4) Continuous transmission START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnT bit = 1? Data to be transferred next exists? CBnTSF bit = 1? (CBnSTR) CBnPWR bit = 0 (CBnCTL0) Note Set the CBnSCE bit to 1 in the initial setting.
Page 350 CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (5) Continuous reception START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) CBnRX register dummy read (start reception) INTCBnR bit = 1? Is data being received last data? CBnSCE bit = 0 (CBnCTL0) CBnRX register read CBnOVE bit = 1? (CBnSTR) CBnOVE bit clear...
Page 351 CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (6) Continuous transmission/reception START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register. INTCBnT bit = 1? Is data being transferred last data? Write CBnTX register. INTCBnT bit = 1? CBnRX register read CBnOVE bit = 0? (CBnSTR) CBnOVE bit clear...
Page 352: Chapter 15 Interrupt/Exception Processing Function
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850ES/ST2 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 37 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 353 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 15-1. Interrupt/Exception Source List (1/2) Type Classification Default Name Trigger Generating Exception Handler Restored Interrupt Priority Unit Code Address Control Register − − Reset Interrupt RESET External source: RESET pin 0000H 00000000H Undefined input Internal source: WDT overflow −...
Page 354 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 15-1. Interrupt/Exception Source List (2/2) Type Classification Default Name Trigger Generating Exception Handler Restored Interrupt Priority Unit Code Address Control Register Maskable Interrupt INTTP3CC1 TMP3 capture 1/compare 1 TMP3 01C0H 000001C0H nextPC TP3CCIC1 match INTTP4OV TMP4 overflow TMP4...
Page 355: Non-Maskable Interrupts
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.2 Non-Maskable Interrupts A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupts. This product has the following two non-maskable interrupts.
Page 356 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 15-1. Non-Maskable Interrupt Request Acknowledgment Operation (2/2) (b) Non-maskable interrupt request generated during non-maskable interrupt servicing Non-maskable Non-maskable interrupt request generated during non-maskable interrupt servicing interrupt being INTWDT serviced • NMI request generated during NMI servicing •...
Page 357: Operation
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.2.1 Operation If a non-maskable interrupt is generated by NMI input, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3>...
Page 358: Restore
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.2.2 Restore (1) From NMI pin input Execution is restored from the NMI servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC.
Page 359: Np Flag
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt servicing is under execution. This flag is set when a non-maskable interrupt request has been acknowledged, and masks non-maskable interrupt requests to prohibit multiple interrupts from being acknowledged. Reset input sets this flag to 00000020H.
Page 360: Maskable Interrupts
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850ES/ST2 has 35 maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 361 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 15-4. Maskable Interrupt Servicing INT input INTC accepted xxIF = 1 Interrupt requested? xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently being serviced? Priority higher than that of other interrupt request? Highest default priority of interrupt requests...
Page 362: Restore
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. <1>...
Page 363: Priorities Of Maskable Interrupts
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.3.3 Priorities of maskable interrupts The INTC performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 364 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 15-6. Example of Processing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b (level 3) Interrupt request b is acknowledged because the (level 2) priority of b is higher than that of a and interrupts are...
Page 365 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 15-6. Example of Processing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i Servicing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k...
Page 366 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 15-7. Example of Servicing Interrupt Requests Simultaneously Generated Main routine Interrupt request a (level 2) Interrupt request b (level 1) Servicing of interrupt request b Interrupt request b and c are Interrupt request c (level 1) acknowledged first according to their priorities.
Page 367: Interrupt Control Register (Xxicn)
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read or written in 8-bit or 1-bit units. Reset input sets these registers to 47H.
Page 368 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 15-2. Interrupt Control Registers (xxICn) Address Register <7> <6> FFFFF110H WDTIC WDTIF WDTMK WDTPR2 WDTPR1 WDTPR0 FFFFF112H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF114H PIC1 PIF1 PMK1 PPR12 PPR11 PPR10 FFFFF116H PIC2 PIF2 PMK2 PPR22 PPR21 PPR20...
Page 369: Interrupt Mask Registers 0 To 2 (Imr0 To Imr2)
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.3.5 Interrupt mask registers 0 to 2 (IMR0 to IMR2) These registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR2 registers is equivalent to the xxMKn bit of the xxICn register. The IMRm register can be read or written in 14-bit units (m = 0 to 2).
Page 370: In-Service Priority Register (Ispr)
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced.
Page 371: Id Flag
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.3.7 ID flag This flag controls the maskable interrupt’s operating state, and stores control information regarding enabling or disabling of interrupt requests. An interrupt disable flag (ID) is incorporated, which is assigned to the PSW. Reset input sets this flag to 00000020H.
Page 372: Watchdog Timer Mode Register (Wdtm)
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.3.8 Watchdog timer mode register (WDTM) This register is a special register that can be written only in a special sequence. To make a maskable interrupt (INTWDTM) occur, clear the WDTM4 bit to 0. The WDTM1 register is read/written by an 8-bit or 1-bit memory manipulation instruction (refer to CHAPTER 9 WATCHDOG TIMER FUNCTIONS).
Page 373: External Interrupt Request Input Pins (Nmi, Intp0 To Intp7)
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.4 External Interrupt Request Input Pins (NMI, INTP0 to INTP7) 15.4.1 Noise elimination (1) Noise elimination for NMI pin The NMI pin includes a noise eliminator that operates using analog delay. Therefore, a signal input to the NMI pin is not detected as an edge unless it maintains its input level for a certain period.
Page 374 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt rising, falling edge specification register 0 (INTR0, INTF0) The INTR0 and INTF0 registers are 8-bit registers that specify detection of the rising and falling edges of the NMI and INTP0 to INTP3 pins. These registers can be read or written in 8-bit or 1-bit units.
Page 375 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 15-3. NMI and INTP0 to INTP3 Pin Valid Edge Specification INTF0n INTR0n Valid edge specification (n = 2 to 5) No edge detection Rising edge Falling edge Both edges Note PFC06 INTF06 INTR06 Valid edge specification No edge detection Rising edge Falling edge...
Page 376 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) External interrupt rising, falling edge specification register 3 (INTR3, INTF3) The INTF3 and INTR3 registers are 8-bit registers that specify detection of the rising and falling edges of the INTP7pin. These registers can be read or written in 8-bit or 1-bit units. Reset input clears these registers to 00H.
Page 377 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) External interrupt rising, falling edge specification register 9H (INTR9H, INTF9H) The INTF9H and INR9H registers are 8-bit registers that specify detection of the rising and falling edges of the INTP4 to INTP6 pins. These registers can be read or written in 8-bit or 1-bit units. Reset input clears these registers to 00H.
Page 378: Software Exception
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.5 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged. 15.5.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine.
Page 379: Restore
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.5.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. <1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 1. <2>...
Page 380: Ep Flag
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.5.3 EP flag The EP flag is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. Reset input sets this flag to 00000020H. After reset: 00000020H NP EP ID SAT CY OV...
Page 381: Exception Trap
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.6 Exception Trap An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850ES/ST2, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 15.6.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B, and a sub-opcode (bit 16) of 0B.
Page 382 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 15-10. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing DBPC Restored PC DBPSW PSW.NP PSW.EP PSW.ID 00000060H Exception processing (2) Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC.
Page 383: Debug Trap
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.6.2 Debug trap A debug trap is an exception that is generated when the DBTRAP instruction is executed and is always acknowledged. Upon occurrence of a debug trap, the CPU performs the following processing. (1) Operation <1>...
Page 384 CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restore Restoration from a debug trap is executed with the DBRET instruction. With the DBRET instruction, the CPU performs the following steps and transfers control to the address of the restored PC. <1> The restored PC and PSW are read from DBPC and DBPSW. <2>...
Page 385: Interrupt Acknowledge Time Of Cpu
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.7 Interrupt Acknowledge Time of CPU Except the following cases, the interrupt acknowledge time of the CPU is 4 clocks minimum. To input interrupt requests successively, input the next interrupt at least 4 clocks after the preceding interrupt. •...
Page 386: Periods In Which Interrupts Are Not Acknowledged By Cpu
CHAPTER 15 INTERRUPT/EXCEPTION PROCESSING FUNCTION 15.8 Periods in Which Interrupts Are Not Acknowledged by CPU An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending). The interrupt request non-sample instructions are as follows.
Page 387: Chapter 16 Standby Function
CHAPTER 16 STANDBY FUNCTION 16.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 16-1. Table 16-1.
Page 388 CHAPTER 16 STANDBY FUNCTION Figure 16-1. Status Transition Normal operation mode End of oscillation End of oscillation stabilization time count stabilization time count Setting of HALT mode Note 3 Interrupt request End of oscillation Note 2 stabilization time count Wait for stabilization Wait for stabilization Note 1 of oscillation...
Page 389: Control Registers
CHAPTER 16 STANDBY FUNCTION 16.2 Control Registers (1) Power save control register (PSC) This is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the IDLE/STOP mode. The PSC register is a special register that can be written only by the special sequence combinations (refer to 3.4.7 Special registers).
Page 390 CHAPTER 16 STANDBY FUNCTION (2) Power save mode register (PSMR) This is an 8-bit register that controls the operation status in the power save mode. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFF820H <...
Page 391 CHAPTER 16 STANDBY FUNCTION (3) Oscillation stabilization time select register (OSTS) The wait time until the oscillation stabilizes after the STOP mode is released is controlled by the oscillation stabilization time select register (OSTS). The OSTS register can be read or written only in 8-bit units. Reset input sets OSTS to 09H.
Page 392: Halt Mode
CHAPTER 16 STANDBY FUNCTION 16.3 HALT Mode 16.3.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to the other on-chip peripheral functions continues.
Page 393 CHAPTER 16 STANDBY FUNCTION (2) Releasing HALT mode by RESET pin input or WDTRES signal The same operation as the normal reset operation is performed. Table 16-3. Operation Status in HALT Mode Setting of HALT Mode Operation Status Item Clock oscillator Oscillation enabled Oscillation enabled Stops operation...
Page 394: Idle Mode
CHAPTER 16 STANDBY FUNCTION 16.4 IDLE Mode 16.4.1 Setting and operation status The IDLE mode is set by clearing the PSMR.PSM bit to 0 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE mode, the clock oscillator continues operation but clock supply to the CPU and other on-chip peripheral functions stops.
Page 395 CHAPTER 16 STANDBY FUNCTION (2) Releasing IDLE mode by RESET pin input The same operation as the normal reset operation is performed. Table 16-5. Operation Status in IDLE Mode Setting of HALT Mode Operation Status Item Clock oscillator Oscillation enabled Oscillation enabled Stops operation Interrupt controller...
Page 396: Stop Mode
CHAPTER 16 STANDBY FUNCTION 16.5 STOP Mode 16.5.1 Setting and operation status The STOP mode is set when the PSMR.PSM bit are set to 1 and the PSC.STP bit is set to 1 in the normal operation mode. In the STOP mode, the clock oscillator stops. Clock supply to the CPU and the on-chip peripheral functions is stopped.
Page 397 CHAPTER 16 STANDBY FUNCTION Table 16-6. Operation After Releasing STOP Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt request signal Execution branches to the handler address after the OSC oscillation stabilization time + PLL lockup time is secured Maskable interrupt request signal Execution branches to the handler...
Page 398: Securing Oscillation Stabilization Time
CHAPTER 16 STANDBY FUNCTION 16.6 Securing Oscillation Stabilization Time When the STOP mode is released, only the oscillation stabilization time set by the OSTS register + PLL lockup time (2 ) is secured. If the STOP mode has been released by RESET pin input, however, the reset value of the OSTS register (2 ) + PLL lockup time (2 ) elapses.
Page 399: Chapter 17 Reset Function
CHAPTER 17 RESET FUNCTION 17.1 Overview The following reset functions are available. • Reset function by RESET pin input • Reset function by WDT overflow (WDTRES) If the RESET pin goes high, the reset status is released, and the CPU starts executing the program. Initialize the contents of each register in the program as necessary.
Page 400: Operation
CHAPTER 17 RESET FUNCTION 17.3 Operation (1) Reset by RESET pin When a low level is input to the RESET pin, the system is reset, and each hardware unit is initialized. While a low level is being input to the RESET pin, the clock oscillator and PLL stop. Therefore, the overall power consumption of the system can be reduced.
Page 401 CHAPTER 17 RESET FUNCTION Figure 17-2. Timing of Reset Operation by RESET Pin Input Initialized to f /8 operation RESET Analog delay Analog Analog delay Analog (eliminated as noise) delay (eliminated as noise) delay Internal system reset signal OSC oscillation stabilization time + PLL lockup time count Overflow of timer for oscillation stabilization...
Page 402 CHAPTER 17 RESET FUNCTION (2) Reset by WDTRES signal When WDT is set to the reset operation mode due to overflow, upon WDT overflow (WDTRES signal occurrence), system reset is performed and the hardware is initialized to the initial status. Following WDT overflow, the reset status is entered and lasts the predetermined time (analog delay), and the reset status is then automatically released.
Page 403: Chapter 18 Regulator
CHAPTER 18 REGULATOR 18.1 Outline The V850ES/SG2 includes a regulator to reduce power consumption and noise. This regulator supplies a stepped-down V power supply voltage to the internal logic circuits (except the A/D converter, D/A converter, and I/O buffers). The regulator output voltage is set to 2.5 V (TYP.). <R>...
Page 404: Operation
CHAPTER 18 REGULATOR 18.2 Operation The regulator of this product always operates in any mode (normal operation mode, HALT mode, IDLE mode, STOP mode, or during reset). μ Be sure to connect a capacitor (4.7 F (recommended value)) to the REGC pin to stabilize the regulator output. A diagram of the regulator pin connection method is shown below.
Page 405: Chapter 19 Electrical Specifications
<R> CHAPTER 19 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) (1/2) Parameter Symbol Conditions Ratings Unit −0.5 to +4.6 Supply voltage = EV = BV = AV = AV REF0 REF1 −0.5 to +4.6 = EV = BV = AV = AV REF0 REF1...
Page 406 CHAPTER 19 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit Output current, low P02 to P06, P30 to P35, P38, P39, P40 to Per pin P42, P50 to P55, P90 to P915 Total PCM0 to PCM3, PCS1 to PCS3, PCT0, Per pin PCT1, PCT4, PCT6, PDH0 to PDH5, AD0 Total...
Page 407 CHAPTER 19 ELECTRICAL SPECIFICATIONS Main Clock Oscillator Characteristics = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V) (1/2) REF0 REF1 Resonator Recommended Circuit Parameter Conditions...
Page 408 CHAPTER 19 ELECTRICAL SPECIFICATIONS Regulator Characteristics = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V) REF0 REF1 Parameter Symbol Conditions MIN. TYP.
Page 409 CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V) (1/2) REF0 REF1 Parameter Symbol Conditions MIN.
Page 410 CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V) (2/2) REF0 REF1 Parameter Symbol Conditions MIN.
Page 411 CHAPTER 19 ELECTRICAL SPECIFICATIONS AC Characteristics AC Test Input Measurement Points (a) (PCM0 to PCM3, PCS1 to PCS3, PCT0, PCT1, PCT4, PCT6, PDH0 to PDH5, AD0 to AD15) 0.5BV 0.5BV (b) Other than (a) above , AV , AV REF0 REF1 Measurement points...
Page 412 CHAPTER 19 ELECTRICAL SPECIFICATIONS Load Conditions (Device under measurement) = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means. User’s Manual U17031EJ2V0UD...
Page 413 CHAPTER 19 ELECTRICAL SPECIFICATIONS X1 External Clock Input Timing = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0 REF1 = 50 pF) Parameter Symbol Conditions...
Page 414 CHAPTER 19 ELECTRICAL SPECIFICATIONS Bus Timing (1) Separate bus mode 1 Regardless of the CS1 space setting, the following specifications apply to all the CS0 to CS3 spaces. (a) Read cycle (CLKOUT asynchronous) (1/2): Separate access → Separate access → Separate access = −40 to +85°C, V = EV = BV...
Page 415 CHAPTER 19 ELECTRICAL SPECIFICATIONS (a) Read cycle (CLKOUT asynchronous) (2/2): Separate access → Separate access → Separate access TASW TAHW TWDW TWWT CLKOUT (output) A0-A21 (output) CSn (output) <6> <7> <8> <9> <10> AD0 to AD15 (output) <16> <11> <17> RD (output) <18>...
Page 416 CHAPTER 19 ELECTRICAL SPECIFICATIONS (b) Read cycle (CLKOUT synchronous) (1/2): Separate access → Separate access → Separate access = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0...
Page 417 CHAPTER 19 ELECTRICAL SPECIFICATIONS (b) Read cycle (CLKOUT synchronous) (2/2): Separate access → Separate access → Separate access TASW TAHW TWDW TWWT CLKOUT (output) <19> <20> A0 to A21 (output) CSn (output) <21> <22> AD0 to AD15 (output) <23> <24> RD (output) WR0 (output) WR1 (output)
Page 418 CHAPTER 19 ELECTRICAL SPECIFICATIONS (c) Write cycle (CLKOUT asynchronous) (1/2): Separate access → Separate access → Separate access = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0...
Page 419 CHAPTER 19 ELECTRICAL SPECIFICATIONS (c) Write cycle (CLKOUT asynchronous) (2/2): Separate access → Separate access → Separate access TASW TAHW TWDW TWWT CLKOUT (output) A0 to A21 (output) CSn (output) <27> <28> <29> <31> <32> <30> <33> AD0 to AD15 (output) RD (output) <37>...
Page 420 CHAPTER 19 ELECTRICAL SPECIFICATIONS (d) Write cycle (CLKOUT synchronous) (1/2): Separate access → Separate access → Separate access = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0...
Page 421 CHAPTER 19 ELECTRICAL SPECIFICATIONS (d) Write cycle (CLKOUT synchronous) (2/2): Separate access → Separate access → Separate access TASW TAHW TWDW TWWT CLKOUT (output) <19> <20> A0 to A21 (output) CSn (output) <39> <41> <40> <42> AD0 to AD15 (output) RD (output) <43>...
Page 422 CHAPTER 19 ELECTRICAL SPECIFICATIONS (2) Multiplexed bus mode (1) The following specifications apply to the CS0 to CS3 spaces when the CS1 space is set to multiplexed bus mode. (a) Read cycle (CLKOUT asynchronous) (1/3): Multiplexed access → Multiplexed access → Multiplexed access = −40 to +85°C, V = EV = BV...
Page 423 CHAPTER 19 ELECTRICAL SPECIFICATIONS (a) Read cycle (CLKOUT asynchronous) (2/3): Multiplexed access → Multiplexed access → Multiplexed access = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0...
Page 424 CHAPTER 19 ELECTRICAL SPECIFICATIONS (a) Read cycle (CLKOUT asynchronous) (3/3): Multiplexed access → Multiplexed access → Multiplexed access TASW TAHW TWDW TWWT CLKOUT (output) A0 to A21 (output) CSn (output) <51> <48> AD0 to AD15 (output) <45> <47> <55> <46> <52>...
Page 425 CHAPTER 19 ELECTRICAL SPECIFICATIONS (b) Read cycle (CLKOUT synchronous) (1/2): Multiplexed access → Multiplexed access → Multiplexed access = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0...
Page 426 CHAPTER 19 ELECTRICAL SPECIFICATIONS (b) Read cycle (CLKOUT synchronous) (2/2): Multiplexed access → Multiplexed access → Multiplexed access TASW TAHW TWDW TWWT CLKOUT (output) <67> <68> A0 to A21 (output) CSn (output) <70> <69> <71> <72> AD0 to AD15 (output) <73>...
Page 427 CHAPTER 19 ELECTRICAL SPECIFICATIONS (c) Write cycle (CLKOUT asynchronous) (1/2): Multiplexed access → Multiplexed access → Multiplexed access = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0...
Page 428 CHAPTER 19 ELECTRICAL SPECIFICATIONS (c) Write cycle (CLKOUT asynchronous) (2/2): Multiplexed access → Multiplexed access → Multiplexed access TASW TAHW TWDW TWWT CLKOUT (output) A0 to A21 (output) CSn (output) <79> AD0 to AD15 (output) <45> <47> <83> <84> <46> <81>...
Page 429 CHAPTER 19 ELECTRICAL SPECIFICATIONS (d) Write cycle (CLKOUT synchronous) (1/2): Multiplexed access → Multiplexed access → Multiplexed access = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0...
Page 430 CHAPTER 19 ELECTRICAL SPECIFICATIONS (d) Write cycle (CLKOUT synchronous) (2/2): Multiplexed access → Multiplexed access → Multiplexed access TASW TAHW TWDW TWWT CLKOUT (output) <67> <68> A0 to A21 (output) CSn (output) <91> <69> <92> AD0 to AD15 (output) <73> <74>...
Page 431 CHAPTER 19 ELECTRICAL SPECIFICATIONS (3) Separate bus mode (2) The following specifications apply to the CS0 to CS3 spaces when the CS1 space is set to multiplexed bus mode. (a) Read cycle (CLKOUT asynchronous) (1/2): Multiplexed access → Separate access → Multiplexed access = −40 to +85°C, V = EV = BV...
Page 432 CHAPTER 19 ELECTRICAL SPECIFICATIONS (a) Read cycle (CLKOUT asynchronous) (2/2): Multiplexed access → Separate access → Multiplexed access TASW TAHW TWDW TWWT TASW CLKOUT (output) A0 to A21 (output) CSn (output) <6> <7> <8> <9> <10> AD0 to AD15 (output) <95>...
Page 433 CHAPTER 19 ELECTRICAL SPECIFICATIONS (b) Read cycle (CLKOUT synchronous) (1/2): Multiplexed access → Separate access → Multiplexed access = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0...
Page 434 CHAPTER 19 ELECTRICAL SPECIFICATIONS (b) Read cycle (CLKOUT synchronous) (2/2): Multiplexed access → Separate access → Multiplexed access TASW TAHW TWDW TWWT TASW CLKOUT (output) <19> <20> A0 to A21 (output) CSn (output) <21> <22> AD0 to AD15 (output) <23> <24>...
Page 435 CHAPTER 19 ELECTRICAL SPECIFICATIONS (c) Write cycle (CLKOUT asynchronous) (1/2): Multiplexed access → Separate access → Multiplexed access = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0...
Page 436 CHAPTER 19 ELECTRICAL SPECIFICATIONS (c) Write cycle (CLKOUT asynchronous) (2/2): Multiplexed access → Separate access → Multiplexed access TASW TAHW TWDW TWWT TASW CLKOUT (output) A0 to A21 (output) CSn (output) <27> <28> <29> <31> <32> <30> <33> AD0 to AD15 (output) (output) <97>...
Page 437 CHAPTER 19 ELECTRICAL SPECIFICATIONS (d) Write cycle (CLKOUT synchronous) (1/2): Multiplexed access → Separate access → Multiplexed access = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0...
Page 438 CHAPTER 19 ELECTRICAL SPECIFICATIONS (d) Write cycle (CLKOUT synchronous) (2/2): Multiplexed access → Separate access → Multiplexed access TASW TAHW TWDW TWWT TASW CLKOUT (output) <19> <20> A0 to A21 (output) CSn (output) <39> <41> <40> <42> AD0 to AD15 (output) (output) <43>...
Page 439 CHAPTER 19 ELECTRICAL SPECIFICATIONS (4) Multiplexed bus mode (2) The following specifications apply to the CS0 to CS3 spaces when the CS1 space is set to multiplexed bus mode. (a) Read cycle (CLKOUT asynchronous) (1/3): Separate access → Multiplexed access → Separate access = −40 to +85°C, V = EV = BV...
Page 440 CHAPTER 19 ELECTRICAL SPECIFICATIONS (a) Read cycle (CLKOUT asynchronous) (2/3): Separate access → Multiplexed access → Separate access = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0...
Page 441 CHAPTER 19 ELECTRICAL SPECIFICATIONS (a) Read cycle (CLKOUT asynchronous) (3/3): Separate access → Multiplexed access → Separate access TASW TAHW TWDW TWWT CLKOUT (output) A0 to A21 (output) CSn (output) <100> <48> AD0 to AD15 (output) <98> <47> <55> <46> <52>...
Page 442 CHAPTER 19 ELECTRICAL SPECIFICATIONS (b) Read cycle (CLKOUT synchronous) (1/2): Separate access → Multiplexed access → Separate access = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0...
Page 443 CHAPTER 19 ELECTRICAL SPECIFICATIONS (b) Read cycle (CLKOUT synchronous) (2/2): Separate access → Multiplexed access → Separate access TASW TAHW TWDW TWWT CLKOUT (output) <67> <68> A0 to A21 (output) CSn (output) <70> <71> <72> <105> <69> AD0 to AD15 (output) <74>...
Page 444 CHAPTER 19 ELECTRICAL SPECIFICATIONS (c) Write cycle (CLKOUT asynchronous) (1/2): Separate access → Multiplexed access → Separate access = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0...
Page 445 CHAPTER 19 ELECTRICAL SPECIFICATIONS (c) Write cycle (CLKOUT asynchronous) (2/2): Separate access → Multiplexed access → Separate access TASW TAHW TWDW TWWT CLKOUT (output) A0 to A21 (output) CSn (output) <79> AD0 to AD15 (output) <98> <47> <83> <84> <46> <81>...
Page 446 CHAPTER 19 ELECTRICAL SPECIFICATIONS (d) Write cycle (CLKOUT synchronous) (1/2): Separate access → Multiplexed access → Separate access = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0...
Page 447 CHAPTER 19 ELECTRICAL SPECIFICATIONS (d) Write cycle (CLKOUT synchronous) (2/2): Separate access → Multiplexed access → Separate access TASW TAHW TWDW TWWT CLKOUT (output) <67> <68> A0 to A21 (output) CSn (output) <91> <105> <69> <92> AD0 to AD15 (output) <73>...
Page 448 CHAPTER 19 ELECTRICAL SPECIFICATIONS Bus Hold Cycle (1) Bus hold cycle (CLKOUT asynchronous) = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0 REF1 = 50 pF, t...
Page 449 CHAPTER 19 ELECTRICAL SPECIFICATIONS (2) Bus hold cycle (CLKOUT synchronous) = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0 REF1 = 50 pF, t = 5 ns) Parameter...
Page 450 CHAPTER 19 ELECTRICAL SPECIFICATIONS Basic Operation = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0 REF1 = 50 pF) Parameter Symbol Conditions MIN.
Page 451 CHAPTER 19 ELECTRICAL SPECIFICATIONS Timer Timing = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0 REF1 = 50 pF) Parameter Symbol Conditions MIN.
Page 452 CHAPTER 19 ELECTRICAL SPECIFICATIONS CSI Timing (1) Master mode = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0 REF1 = 50 pF) Parameter Symbol Conditions...
Page 453 CHAPTER 19 ELECTRICAL SPECIFICATIONS A/D Converter = −40 to +85°C, V = EV = BV = AV = AV = 3.0 to 3.6 V, V = EV = BV = AV = 0 V, REF0 REF1 = 50 pF) Parameter Symbol Conditions MIN.
Page 454: Chapter 20 Package Drawings
CHAPTER 20 PACKAGE DRAWINGS 120-PIN PLASTIC TQFP (FINE PITCH) (14x14) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.07 mm of 16.0±0.2 its true position (T.P.) at maximum material condition.-1 14.0±0.2 14.0±0.2 16.0±0.2 0.18±0.05 0.07 0.4 (T.P.) 1.0±0.2 0.17 +0.03...
Page 455 CHAPTER 20 PACKAGE DRAWINGS 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 22.0±0.2 its true position (T.P.) at maximum material condition. 20.0±0.2 20.0±0.2 22.0±0.2 1.25 1.25 0.22±0.05 0.08 0.5 (T.P.)
Page 456: Chapter 21 Recommended Soldering Conditions
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Remarks 1. Products with -A at the end of the part number are lead-free products. 2. For soldering methods and conditions other than those recommended, please contact an NEC Electronics sales representative.
Page 457: Appendix A Cautions
APPENDIX A CAUTIONS A.1 Restriction on Conflict Between sld Instruction and Interrupt Request A.1.1 Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1>...
Page 458: R> A.2 Restrictions On Generation Timing Of Re-Conversion Sources During Operation Of A/D Converter
APPENDIX A CAUTIONS <R> A.2 Restrictions on Generation Timing of Re-conversion Sources During Operation of A/D Converter A.2.1 Description The following restrictions apply. (1) After A/D conversion is enabled (ADA0M0.ADA0CE bit = 1), when the timing for ending stabilization time of Note the A/D converter (see Figures A-1 and A-2) and the re-conversion source conflict, the stabilization time is...
Page 459 APPENDIX A CAUTIONS Table A-1 Applicable and Non-applicable Restrictions Trigger Mode Operation Mode Normal Conversion Mode High-Speed Conversion Mode × − − − × Software trigger Continuous select × − − − × Continuous scan − − − Note 1 Note 1 One-shot select −...
Page 460: Workarounds
APPENDIX A CAUTIONS A.2.2 Workarounds The following workarounds are applicable to all of A.2.1 (1) to (4). (1) In the external trigger mode (ADA0M0.ADA0TMD bit = 1) In external trigger mode, set the high-speed conversion mode (ADA0M1.ADA0HS1 bit = 1). After A/D conversion is enabled (ADA0M0.ADA0CE bit = 1), input the external trigger after the elapse of the A/D converter stabilization time (see Table 11-3).
Page 461: Appendix B Notes On Target System Design
APPENDIX B NOTES ON TARGET SYSTEM DESIGN The following shows a diagram of the connection conditions between the in-circuit emulator emulation board and conversion connector. Design your system making allowances for conditions such as the form of parts mounted on the target system based on this configuration.
Page 462 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-1. When Using 120-Pin Plastic TQFP (Fine Pitch) (14 × 14) (2/2) Connection condition diagram In-circuit emulator emulation board probe Conversion adapter (EV-703220GC120) 32 mm 25.3 mm 39 mm 12.8 mm 7.2 mm Target connector (EV-703220GC120) 17 mm...
Page 463 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. When Using 144-Pin Plastic LQFP (Fine Pitch) (20 × 20) (1/2) Side view In-circuit emulator (IE-V850ES-G1) In-circuit emulator In-circuit emulator emulation emulation board board probe (IE-703220-G1-EM1) Conversion adapter (EV-703220GJ144) Note Target connector (EV-703220GJ144) Target system Note The A144-SA-01S (sold separately: product of Application Corporation) can be inserted here for...
Page 464 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. When Using 144-Pin Plastic LQFP (Fine Pitch) (20 × 20) (2/2) Connection condition diagram In-circuit emulator emulation board probe Conversion adapter (EV-703220GJ144) 32 mm 25.3 mm 39 mm 12.8 mm 7.2 mm Target connector (EV-703220GJ144) 23 mm...
Page 465: Appendix C Register Index
APPENDIX C REGISTER INDEX (1/6) Symbol Register Name Unit Page ADA0CR0 A/D conversion result register 0 ADA0CR0H A/D conversion result register 0H ADA0CR1 A/D conversion result register 1 ADA0CR1H A/D conversion result register 1H ADA0CR2 A/D conversion result register 2 ADA0CR2H A/D conversion result register 2H ADA0CR3...
Page 466 APPENDIX C REGISTER INDEX (2/6) Symbol Register Name Unit Page CTPC CALLT execution status saving register CTPSW CALLT execution status saving register DA0CS0 D/A converter conversion value setting register 0 DA0CS1 D/A converter conversion value setting register 1 DA0M D/A converter mode register DBPC Exception/debug trap status saving register DBPSW...
Page 467 APPENDIX C REGISTER INDEX (3/6) Symbol Register Name Unit Page Port CS register Port Port CT register Port Port DH register Port PFC0 Port 0 function control register Port PFC3 Port 3 function control register Port PFC3L Port 3 function control register L Port PFC5 Port 5 function control register...
Page 468 APPENDIX C REGISTER INDEX (4/6) Symbol Register Name Unit Page PMCCT Port CT mode control register Port PMCDH Port DH mode control register Port PMCM Port CM mode register Port PMCS Port CS mode register Port PMCT Port CT mode register Port PMDH Port DH mode register...
Page 469 APPENDIX C REGISTER INDEX (5/6) Symbol Register Name Unit Page TP2CCIC1 Interrupt control register INTC TP2CCR0 TMP2 capture/compare register 0 TP2CCR1 TMP2 capture/compare register 1 TP2CNT TMP2 counter read buffer register TP2CTL0 TMP2 control register 0 TP2CTL1 TMP2 control register 1 TP2IOC0 TMP2 I/O control register 0 TP2IOC1...
Page 470 APPENDIX C REGISTER INDEX (6/6) Symbol Register Name Unit Page TP5IOC2 TMP5 I/O control register 2 TP5OPT0 TMP5 option register 0 TP5OVIC Interrupt control register INTC UA0CTL0 UARTA0 control register 0 UART UA0CTL1 UARTA0 control register 1 UART UA0CTL2 UARTA0 control register 2 UART UA0OPT0 UARTA0 option control register 0...
Page 471: Appendix D Instruction Set List
APPENDIX D INSTRUCTION SET LIST D.1 Conventions (1) Register symbols used to describe operands Register Symbol Explanation reg1 General-purpose registers: Used as source registers. reg2 General-purpose registers: Used mainly as destination registers. Also used as source register in some instructions. reg3 General-purpose registers: Used mainly to store the remainders of division results and the higher order 32 bits of multiplication results.
Page 472 APPENDIX D INSTRUCTION SET LIST (3) Register symbols used in operations Register Symbol Explanation ← Input for GR [ ] General-purpose register SR [ ] System register zero-extend (n) Expand n with zeros until word length. sign-extend (n) Expand n with signs until word length. load-memory (a, b) Read size b data from address a.
Page 473 APPENDIX D INSTRUCTION SET LIST (5) Register symbols used in flag operations Identifier Explanation (Blank) No change Clear to 0 Set or cleared in accordance with the results. Previously saved values are restored. (6) Condition codes Condition Name Condition Code Condition Formula Explanation (cond)
Page 474: Instruction Set (In Alphabetical Order)
APPENDIX D INSTRUCTION SET LIST D.2 Instruction Set (In Alphabetical Order) (1/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × × × reg1,reg2 r r rr r0 01 11 0 RRRRR GR[reg2]←GR[reg2]+GR[reg1] × × ×...
Page 475 APPENDIX D INSTRUCTION SET LIST (2/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT DBTRAP 1111100001000000 DBPC←PC+2 (returned PC) DBPSW←PSW PSW.NP←1 PSW.EP←1 PSW.ID←1 PC←00000060H 0000011111100000 PSW.ID←1 0000000101100000 DISPOSE imm5,list12 0 0 0 0 0 1 1 0 0 1 i i i i i L sp←sp+zero-extend(imm5 logically shift left by 2) LLLLLLLLLLL00000 GR[reg in list12]←Load-memory(sp,Word)
Page 476 APPENDIX D INSTRUCTION SET LIST (3/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT LD.H disp16[reg1],reg2 rrrrr111001RRRRR adr←GR[reg1]+sign-extend(disp16) Note ddddddddddddddd0 GR[reg2]←sign-extend(Load-memory(adr,Half- word)) Note 8 LDSR reg2,regID rrrrr111111RRRRR SR[regID]←GR[reg2] Other than regID = PSW 0000000000100000 × × ×...
Page 477 APPENDIX D INSTRUCTION SET LIST (4/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × reg1,reg2 r r rr r0 01 00 0 RRRRR GR[reg2]←GR[reg2]OR GR[reg1] × × imm16,reg1,reg2 r r rr r1 10 10 0 RRRRR GR[reg2]←GR[reg1]OR zero-extend(imm16) i i i i i i i i i i i i i i i i PREPARE...
Page 478 APPENDIX D INSTRUCTION SET LIST (5/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16) dddddddddddddddd Z flag←Not (Load-memory-bit(adr,bit#3)) Note 3 Note 3 Note 3 Store-memory-bit(adr,bit#3,1) × reg2,[reg1] r r rr r1 11 11 1 RRRRR adr←GR[reg1] 0000000011100000 Z flag←Not(Load-memory-bit(adr,reg2))
Page 479 APPENDIX D INSTRUCTION SET LIST (6/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × × × reg1,reg2 r r rr r0 01 10 1 RRRRR GR[reg2]←GR[reg2]–GR[reg1] × × × × SUBR reg1,reg2 r r rr r0 01 10 0 RRRRR GR[reg2]←GR[reg1]–GR[reg2] SWITCH reg1 00000000010RRRRR adr←(PC+2) + (GR [reg1] logically shift left by 1)
Page 480 APPENDIX D INSTRUCTION SET LIST Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. r r r r r = regID specification RRRRR = reg2 specification...
Page 481: Appendix E Revision History
<R> APPENDIX E REVISION HISTORY E.1 Major Revisions in This Edition (1/2) Page Description • Change of ordering numbers of all products to lead-free product numbers Throughout • Change from “under development” to “developed" for all products • Change of NC pin to IC1 to IC6 pins pp.
Page 482 APPENDIX E REVISION HISTORY (2/2) Page Description p. 444 Modification of CHAPTER 19 ELECTRICAL SPECIFICATIONS Bus Timing (4) (c) Write cycle (CLKOUT asynchronous) p. 456 Addition of CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS p. 458 Addition of A.2 Restrictions on Generation Timing of Re-conversion Sources During Operation of A/D Converter p.
Page 483 Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [Asia & Oceania] [America] [Europe] NEC Electronics (China) Co., Ltd NEC Electronics America, Inc. NEC Electronics (Europe) GmbH 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian 2880 Scott Blvd. Arcadiastrasse 10 District, Beijing 100083, P.R.China Santa Clara, CA 95050-2554, U.S.A.

NEC V850ES/ST2 mPD703220 User Manual

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 Cpu Function

Chapter 4 Port Functions

Chapter 5 Bus Control Function

Chapter 6 Clock Generator

Chapter 7 16-Bit Timer/Event Counter P (Tmp)

Chapter 8 16-Bit Interval Timer M (Tmm)

Chapter 9 Watchdog Timer Functions

Chapter 10 Real-Time Output Function (Rto)

Chapter 11 A/D Converter

Chapter 12 D/A Converter

Chapter 13 Asynchronous Serial Interface a (Uarta)

Chapter 14 3-Wire Variable-Length Serial I/O (Csib)

Chapter 15 Interrupt/Exception Processing Function

Chapter 16 Standby Function

Chapter 17 Reset Function

Chapter 18 Regulator

Chapter 19 Electrical Specifications

Chapter 20 Package Drawings

Chapter 21 Recommended Soldering Conditions

Appendix A Cautions

Appendix B Notes on Target System Design

Appendix C Register Index

Appendix D Instruction Set List

Appendix E Revision History

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