Table of Contents
Advertisement
25.4.1 External asynchronous memory access read timing
Table 25-6: External Asynchronous Memory Access Read Timing
Parameter
Data input set up time (vs. address) <10>
Data input set up time (vs. RD↓)
RD Low level width
RD High level width
Address, CSn → RD↓ delay time
RD↑ → address delay time
Data input hold time
(vs. RD↑)
RD↑ → data output delay time
WAIT set up time
(vs. address)
WAIT high level width
Remarks: 1. T:
2/f
2. i:
Number of idle states specified by BCC register
3. w
: Number of waits specified by ASC register
AS
4. w
: Number of waits specified by DWC1, DWC2 register; w
D
5. w:
Number of waits due to external wait signal (WAIT)
6. n = 0, 1, 3, 4
1012
Chapter 25 Electrical Specifications
Symbol
t
SAID
<11>
t
SRDID
<12>
t
WRDL
<13>
t
WRDH
<14>
t
DARD
<15>
t
DRDA
<16>
t
HRDID
<17>
t
DRDOD
< 31 >
t
SAW
<32>
t
WWH
XX
User's Manual U16580EE3V1UD00
MIN.
(2 + w
(1.5 + w
+ w) T - 15
D
(0.5 + w
+ i) T - 15
AS
(0.5 + w
) T - 20
AS
iT - 2
0
(1 + i) T - 15
T - 2
MAX.
+ w
+ w) T - 30
AS
D
(1.5 + w
+ w) T - 30
D
(1 + w
) T- 30
AS
≥
1
D
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hide quick links:
Advertisement
Chapters
Table of Contents
