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Figure 11-12: TMTn I/O Control Register 3 (TTnIOC3) (2/2)
TTnECS1 TTnECS0
0
0
1
1
The encoder clear interrupt (INTTTnEC) is output upon detection of the valid edge set
with bits TTnECS1, TTnECS0.
Caution: When TTnSCE = 1, the encoder clear interrupt (INTTTnEC) is not output.
Remark: Bits TTnECS1 and TTnECS0 are valid in the encoder compare mode and
when TTnSCE = 0.
TTnEIS1
TTnEIS0
0
0
1
1
Remark: Bits TTnEIS1 and TTnEIS0 are valid when bits TTnUDS1 and TTnUDS0 of
register TTnCTL2 are "00B" or "01B".
Remark:
n = 0, 1
Chapter 11 16-bit Timer/Event Counter T
Set the valid edge of encoder clear input (TECRTn pin)
0
No edge detection
1
Rising edge detection
0
Falling edge detection
1
Both rising and falling edge detection
Set the valid edge of the encoder input signal
0
No edge detection
1
Rising edge detection
0
Falling edge detection
1
Both rising and falling edge detection
User's Manual U16580EE3V1UD00
(TENCTn1/TENCTn0 pins)
475
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