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Operation of DMA channel 4/5
no
no
Transfer content from serial receive buffer
(depending on DTFRx register) to iRAM :
(MARx)
Decrement DMA transfer count register:
Set DMA transfer status bit: DMASx = 1
Generate interrupt signal (INTDMAx
Note: DMA transfer completion interrupt has the same interrupt vector address as the corresponding
reception completion interrupt specified by DTFRX register, and replaces that interrupt.
Remark:
n = 0, 1
x = 4, 5
210
Chapter 6 DMA Functions (DMA Controller)
Figure 6-15: Operation of DMA Channel 4/5
DEx bit newly
written ?
yes
DEx bit = 1 ?
yes
DMA trigger
factor occurred ?
yes
yes
(16 bit)
SIRBn or CBnRX
Increment source pointer:
MARx
MARx + 2
DTCRx
DTCRx - 1
DTCRx = 0?
yes
(number of serial interface channel)
(number of DMA transfer channel)
User's Manual U16580EE3V1UD00
DMA transfer will be enabled by write
access to the corresponding DEn bit.
no
DMA trigger factor is the interrupt
source specified by DTFRx register.
no
(8 bit)
DMADSCx bit = 1 ?
Transfer content from serial receive buffer
(depending on DTFRx register) to iRAM :
(MARx)
SIRBnL, CBnRXL or UXnRX
Increment source pointer:
MARx
no
Note
)
MARx + 1
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