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(4/4)
Mnemonic
Operand
ST.W
reg2,disp16[reg1] rrrrr111011RRRRR
ddddddddddddddd1
Note 8
STSR
regID,reg2
rrrrr111111RRRRR
0000000001000000
SUB
reg1,reg2
rrrrr001101RRRRR GR[reg2]←GR[reg2]–GR[reg1]
SUBR
reg1,reg2
rrrrr001100RRRRR GR[reg2]←GR[reg1]–GR[reg2]
SWITCH
reg1
00000000010RRRRR adr←(PC+2) + (GR [reg1] logically shift left by 1)
SXB
reg1
00000000101RRRRR GR[reg1]←sign-extend
SXH
reg1
00000000111RRRRR GR[reg1]←sign-extend
TRAP
vector
00000111111iiiii
0000000100000000
TST
reg1,reg2
rrrrr001011RRRRR result←GR[reg2] AND GR[reg1]
TST1
bit#3,disp16[reg1] 11bbb111110RRRRR
dddddddddddddddd
reg2, [reg1]
rrrrr111111RRRRR
0000000011100110
XOR
reg1,reg2
rrrrr001001RRRRR GR[reg2]←GR[reg2] XOR GR[reg1]
XORI
imm16,reg1,reg2 rrrrr110101RRRRR
iiiiiiiiiiiiiiii
ZXB
reg1
00000000100RRRRR GR[reg1]←zero-extend (GR[reg1] (7 : 0))
ZXH
reg1
00000000110RRRRR GR[reg1]←zero-extend (GR[reg1] (15 : 0))
Notes:
1. dddddddd: Higher 8 bits of disp9.
2. 3 clocks if the final instruction includes PSW write access.
3. If there is no wait state (3 + the number of read access wait states).
4. n is the total number of list X load registers. (According to the number of wait states. Also,
if there are no wait states, n is the number of list X registers.)
5. RRRRR: other than 00000.
6. The lower half word data only are valid.
7. ddddddddddddddddddddd: The higher 21 bits of disp22.
8. ddddddddddddddd: The higher 15 bits of disp16.
9. According to the number of wait states (1 if there are no wait states).
10. b: bit 0 of disp16.
11. According to the number of wait states (2 if there are no wait states).
12. In this instruction, for convenience of mnemonic description, the source register is made
reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specifi-
cation in the mnemonic description and in the opcode differs from other instructions.
rrrrr= regID specification
RRRRR= reg2 specification
13. iiiii: Lower 5 bits of imm9.
IIII: Lower 4 bits of imm9.
14. In the case of reg2 = reg3 (the lower 32 bits of the results are not written in the register)
or reg3 = r0 (the higher 32 bits of the results are not written in the register), shortened by 1
clock.
15. sp/imm: specified by bits 19 and 20 of the sub-opcode.
Appendix A
Opcode
adr←GR[reg1] + sign-extend(disp16)
Store-memory (adr,GR[reg2], Word)
GR[reg2]←SR[regID]
PC←(PC+2) + (sign-extend
(GR[reg1] (7 : 0))
(GR[reg1] (15 : 0))
EIPC←PC+4 (Return PC)
EIPSW←PSW
ECR.EICC←Interrupt Code
PSW.EP←1
PSW.ID←1
PC←00000040H (when vector is 00H to 0FH)
00000050H (when vector is 10H to 1FH)
adr←GR[reg1] + sign-extend(disp16)
Z flag←Not (Load-memory-bit (adr,bit#3))
adr←GR[reg1]
Z flag←Not (Load-memory-bit (adr,reg2))
GR[reg2]←GR[reg1] XOR zero-extend (imm16)
Preliminary User's Manual U14913EE1V0UM00
Instruction Set List
Operation
(Load-memory (adr,Half-word)))
logically shift left by 1
Execution
Flags
Clock
i
r
l
CY OV S
Z SAT
1
1
1
1
1
1
×
×
×
×
1
1
1
×
×
×
×
1
1
1
5
5
5
1
1
1
1
1
1
3
3
3
×
×
1
1
1
0
×
3
3
3
Note
Note
Note
3
3
3
×
3
3
3
Note
Note
Note
3
3
3
×
×
1
1
1
0
×
×
1
1
1
0
1
1
1
1
1
1
591
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