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(c) When the data bus width is 16 bits (Big Endian)
<1> Access to even address (2n)
Address
15
15
2n
8
8
7
7
2n + 1
0
0
Halfword
External
data
data bus
(d) When the data bus width is 8 bits (Big Endian)
<1> Access to even address (2n)
1-st Access
15
Address
8
7
7
2n
0
0
Halfword
External
data
data bus
Preliminary User's Manual U14913EE1V0UM00
Chapter 4 Bus Control Function
2-nd Access
15
Address
8
7
7
2n + 1
0
0
Halfword
External
data
data bus
<2> Access to odd address (2n + 1)
1-st Access
Address
15
15
8
8
7
7
2n + 1
0
0
Halfword
External
data
data bus
<2> Access to odd address (2n + 1)
1-st Access
15
Address
8
7
7
2n + 1
0
0
Halfword
External
data
data bus
2-nd Access
Address
15
15
2n + 2
8
8
7
7
0
0
Halfword
External
data
data bus
2-nd Access
15
Address
8
7
7
2n + 2
0
0
Halfword
External
data
data bus
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