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(2)
Securing the time according to the signal level width (RESET pin input)
Watch mode and software STOP mode are released due to falling edge input to the RESET pin.
The time until the clock output from the oscillator stabilizes is secured according to the low level
width of the signal that is input to the pin.
The supply of internal system clocks begins after a rising edge is input to the RESET pin, and
processing branches to the handler address used for a system reset.
Figure 8-6: WATCH mode release by reset or watchdog timer
Oscillation circuit
System clock
Watch state
RESET signal
Internal system
reset signal
Oscillation waveform
Internal main clock
CLKOUT (output)
STOP state
RESET
(input)
Internal system
reset signal
Chapter 8 Clock Generator
Watch mode setting
Watch clock working
Figure 8-7: STOP mode release by RESET pin input
Set software STOP mode
Oscillator is stopped
Preliminary User's Manual U14913EE1V0UM00
Flash stabilization time
secured by RESET
or NMIWDT
Undefined
Undefined
Oscillation stabilization
time secured by RESET
245
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