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4.3.1 Chip Select Control Function
The 64 MB memory area can be divided into 2 MB, 4 MB and 8 MB memory blocks by the chip area
selection control registers 0 and 1 (CSC0, CSC1) to control the chip select signals.
The memory area can be effectively used by dividing the memory area into memory blocks using the
chip select control function. The priority order is described below.
(1)
Chip area selection control registers 0, 1 (CSC0, CSC1)
These registers can be read/written in 16-bit units. Valid by setting each bit (to 1).
If different chip area select signals are set to the same block, the priority order is controlled as fol-
lows.
CSC0: Peripheral I/O area > CS0 > CS2 > CS1 > CS3
CSC1: Peripheral I/O area > CS7 > CS5 > CS6 > CS4
If both the CS0n and CS2n bits of the CSC0 register are set to 0, CS1 becomes active to the corre-
sponding block (n = 0 to 3).
Similarly, if both the CS5n and CS7n bits of the CSC1 register are set to 0, CS6 becomes active to
the corresponding block (n = 0 to 3).
Note: Not all the chip area select signals are externally available on output pins. Even so, enabling
chip area select signals other than CS2 to CS4, the setting for the corresponding memory
blocks will be effective too, regardless of an external chip select output pin.
Figure 4-2: Chip Area Select Control Registers 0, 1 (1/2)
15
14
13
CSC0 CS33 CS32 CS31 CS30 CS23 CS22 CS21 CS20 CS13 CS12 CS11 CS10 CS03 CS02 CS01 CS00 3FFFFF060H 2C11H
CS3
15
14
13
CSC1 CS43 CS42 CS41 CS40 CS53 CS52 CS51 CS50 CS63 CS62 CS61 CS60 CS73 CS72 CS71 CS70 3FFFFF062H 2C11H
CS4
Chapter 4 Bus Control Function
12
11
10
9
8
CS2
12
11
10
9
8
CS5
Preliminary User's Manual U14913EE1V0UM00
Note
Note
7
6
5
4
3
CS1
7
6
5
4
3
CS6
2
1
0
Address
CS0
2
1
0
Address
CS7
Initial
value
Initial
value
121
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