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(3) System status register (SYS)
Status flags that indicate the operation status of the overall system are allocated to this register.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset:
00H
SYS
0
PRERR
0
1
The PRERR flag operates under the following conditions.
(a) Set condition (PRERR flag = 1)
(i) When data is written to a special register without writing anything to the PRCMD register (when <3> is
executed without executing <2> in 3.4.7 (1) Setting data to special register)
(ii) When data is written to a peripheral I/O register other than a special register (including execution of a
bit manipulation instruction) after writing data to the PRCMD register (if <3> in 3.4.7 (1) Setting data
to special register is not the setting of a special register)
Remark
Even if a peripheral I/O register is read (excluding execution of a bit manipulation instruction)
between a write access to the PRCMD register and a write access to a special register other
than the WDTM register (PCC and PSC registers) (such as an access to the internal RAM), the
PRERR flag is not set and data can be written to the special register.
(b) Clear condition (PRERR flag = 0)
(i) When 0 is written to the SYS.PRERR flag
(ii) When the system is reset
Cautions 1. If 0 is written to the SYS.PRERR bit, which is not a special register, immediately after a
write access to the PRCMD register, the PRERR bit is cleared to 0 (the write access takes
precedence).
2. If data is written to the PRCMD register, which is not a special register, immediately after a
write access to the PRCMD register, the PRERR bit is set to 1.
CHAPTER 3 CPU FUNCTION
R/W
Address:
FFFFF802H
0
0
0
Detects protection error
Protection error did not occur.
Protection error occurred.
User's Manual U17031EJ2V0UD
0
0
0
PRERR
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