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9.3
Control Registers
(1) Watchdog timer clock selection register (WDCS)
The WDCS register sets the overflow time of the watchdog timer and the interval timer.
This register can be read or written in 8-bit units.
Reset input clears WDCS to 00H.
After reset:
WDCS
WDCS2
Remark
f
= f
/2: Watchdog timer clock frequency
XW
XX
258
CHAPTER 9 WATCHDOG TIMER FUNCTIONS
00H
R/W
Address:
FFFF6C1H
0
0
0
WDCS1
WDCS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
User's Manual U17031EJ2V0UD
0
0
WDCS2
Overflow time of watchdog timer/interval timer
f
XX
32 MHz
34 MHz
μ
14
2
/f
482
s
512
XX
μ
15
2
/f
964
s
1.024 ms
XX
16
2
/f
1.928 ms
2.048 ms
XX
17
2
/f
3.855 ms
4.096 ms
XX
18
2
/f
7.710 ms
8.192 ms
XX
19
2
/f
15.42 ms
16.38 ms
XX
20
2
/f
32.77 ms
30.84 ms
XX
22
2
/f
123.4 ms
131.1 ms
XX
WDCS1
WDCS0
20 MHz
μ
μ
s
819
s
1.638 ms
3.277 ms
6.554 ms
13.11 ms
26.21 ms
52.43 ms
209.7 ms
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