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Continuous Mode (Master Mode, Transmission/Reception Mode) - NEC V850ES/ST2 mPD703220 User Manual

32-bit single-chip microcontroller
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14.5.3 Continuous mode (master mode, transmission/reception mode)

MSB first (CBnCTL0.CBnDIR bit = 0), communication type 3 (refer to 14.4 (2) CSIBn control register 1
(CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0)
CBnTX register
SCKBn pin
SOBn pin
SIBn pin
INTCBnT signal
INTCBnR signal
CBnTSF bit
CBnSCE bit
Shift register
SO latch
CBnRX register
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnTXE, CBnRXE, and CBnSCE bits of the CBnCTL0 register to 1 at the same time as
specifying the transfer mode using the CBnDIR bit, to set the transmission/reception enabled status.
(4) Set the CBnPWR bit to 1 to enable the CSIBn operation.
(5) Write transfer data to the CBnTX register (transmission start).
(6) The transmission enable interrupt request signal (INTCBnT) is received and transfer data is written to
the CBnTX register.
(7) The reception complete interrupt request signal (INTCBnR) is output.
Read the CBnRX register before the next receive data arrives or before the CBnPWR bit is cleared to 0.
(8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn
(end of transmission/reception).
To continue transfer, repeat steps (5) to (7) before (8).
In transmission mode or transmission/reception mode, the communication is not started by reading the
CBnRX register.
338
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
55H
0
1
0
1
0
1
1
0
0
1
(1)
(5)
(6)
(2)
(3)
(4)
User's Manual U17031EJ2V0UD
AAH
1
0
1
1
0
1
0
1
1
0
0
1
0
0
1
0
CCH
CCH
(7)
0
1
0
1
1
0
96H
00H
96H
00H
(7)
(8)

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