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17.3.2 Restore
Recovery from maskable interrupt servicing is carried out by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following steps, and transfers control to
the address of the restored PC.
<1> Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and
the NP bit of the PSW is 0.
<2> Transfers control to the address of the restored PC and PSW.
Figure 17-7 illustrates the processing of the RETI instruction.
Note: For the ISPR register, see 13.3.6 In-service priority register (ISPR).
Caution:
Remark:
696
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Chapter 17 Interrupt/Exception Processing Function
Figure 17-7: RETI Instruction Processing
RETI instruction
1
PSW.EP
0
PSW.NP
0
PC
EIPC
PSW
EIPSW
Corresponding
0
Note
bit of ISPR
Restores original processing
When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction dur-
ing maskable interrupt servicing, in order to restore the PC and PSW correctly during
recovery by the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP
back to 0 using the LDSR instruction immediately before the RETI instruction.
The solid line shows the CPU processing flow.
User's Manual U16702EE3V2UD00
1
PC
FEPC
PSW
FEPSW
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