Table of Contents
Advertisement
(7)
Permissible baud rate range for reception
The permissible baud rate error during reception is shown below.
Caution:
After the start bit is detected, the counter set by the UAnCTL2 register determines the latch timing
of the receive data, as shown in Figure 12-17. If the last data (stop bit) is received at this latch tim-
ing, the data can be correctly received.
Assuming 11 bits of data are to be received, the theoretical baud rate is as follows.
FL = (Brate) – 1
Brate: Baud rate of UARTAn (n = 0 to 1)
k:
FL:
Margin of latch timing: 2 clocks
Permissible minimum transfer rate:
428
Downloaded from
Elcodis.com
electronic components distributor
Chapter 12 Asynchronous Serial Interface A (UARTA)
Be sure to set the baud rate error for reception to within the permissible error range,
by using the expressions shown below.
Figure 12-17: Permissible Baud Rate Range for Reception
Latch
timing
Transfer rate
Start bit
of UARTAn
Permissible
minimum
Start bit
transfer rate
Permissible
Start bit
maximum
transfer rate
Set value of UAnCTL2 (n = 0 to 1)
1-bit data length
Flmin = 11 × FL –
Bit 0
Bit 1
FL
1 data frame (11 × FL)
Bit 0
Bit 1
Bit 7
FLmin
Bit 0
Bit 1
FLmax
21k + 2
k - 2
× FL =
2k
User's Manual U16702EE3V2UD00
Bit 7
Parity bit
Stop bit
Parity bit
Stop bit
Bit 7
Parity bit
Stop bit
FL
2k
Advertisement
Chapters
Table of Contents
