Page 1 Important Notes, Contents Product Overview SIMATIC Addressing ET 200S Interface Module ET 200S in the PROFIBUS Network IM 151/CPU Commissioning and Diagnostics Functions of the IM 151/CPU Manual Technical Specifications This manual is part of the document package with the order number: 6ES7 151-1AA00-8BA0 Cycle and Response Times Getting Started...
Page 2 This device and its components may only be used for the applications described in the catalog or the technical descriptions, and only in connection with devices or components from other manufacturers which have been approved or recommended by Siemens. This product can only function correctly and safely if it is transported, stored, set up, and installed cor- rectly, and operated and maintained as recommended.
Page 3 Important Information Purpose of the Manual This manual supplements the ET 200S Distributed I/O System manual. It describes all the functions of the IM 151/CPU interface module. The manual does not deal with general ET 200S functions. You will find descriptions of these in the ET 200S Distributed I/O System manual (see also the section entitled ”Delivery Package”).
Page 4 Important Information Applicability This manual is valid for the IM 151/CPU interface module with the order numbers 6ES7 151-7AA00-0AB0 and 6ES7 151-7AB00-0AB0 as well as the components of the ET 200S specified in the ET 200S Distributed I/O System manual. This manual contains a description of the components that were valid at the time the manual was published.
Page 5 Important Information Aids to Finding Information You can quickly access specific information in the manual by using the following aids: At the beginning of the manual you will find a comprehensive table of contents and lists of the figures and tables in the manual. The sections of the chapters in the manual contain subheadings that allow you to gain a quick overview of the contents of the section.
Page 6 Important Information ET 200S Interface Module IM 151/CPU A5E00058783-01...
Page 7: Table Of Contents
Contents Product Overview What Is the IM 151/CPU Interface Module? ......Guide to the ET 200S Manuals .
Page 8 Contents Functions of the IM 151/CPU Data for the PROFIBUS-DP ........The Mode Selector and LEDs .
Page 9 Contents Instruction List Address Identifiers and Parameter Ranges ......Abbreviations ........... .
Page 10 Contents B.32 Rotate Instructions ..........B-44 B.33 ACCU Transfer Instructions, Incrementing, Decrementing...
Page 11 Contents Figures View of the ET 200S Distributed I/O System with the IM 151/CPU ..Components and the Manuals Required for Them ....Structure of the Default Address Area .
Page 12 Contents Tables Topics of the Manuals in the ET 200S Manual Package ....Addresses of the ET 200S I/O Modules ......Examples of the Maximum Configuration .
Page 13 Contents Structure of the Configuration Frame in the special identifier format (SKF) ............Identifiers for the Address Areas of the Intermediate Memory .
Page 14 Contents ET 200S Interface Module IM 151/CPU A5E00058783-01...
Page 15: Product Overview
Product Overview In This Chapter The product overview provides information about The role of the IM 151/CPU interface module within the ET 200S distributed I/O system Which manuals in the ET 200S manual package contain what information. Chapter Overview Contents Page Section What Is the IM 151/CPU Interface Module?
Page 16: What Is The Im 151/Cpu Interface Module
Product Overview What Is the IM 151/CPU Interface Module? What Is the IM 151/CPU? The IM 151/CPU is a component of the ET 200S distributed I/O system with IP 20 protection. The IM 151/CPU interface module is an intelligent preprocessing unit (intelligent slave).
Page 17: View Of The Et 200S Distributed I/O System With The Im 151/Cpu
Product Overview View The figure below shows a sample configuration of an ET 200S with an IM 151/CPU. Electronic modules IM 151/CPU Power module for the Terminating module Interface module PM-E power mo- PM-D motor starter dule for electronic modules Direct-on-line Reversing starter starter...
Page 18 Product Overview Features of the IM 151/CPU Compared to Other Modules The IM 151/CPU interface module has the following special features: The interface module has PLC functionality (integrated CPU with 24 KB working memory and 40 KB RAM load memory). The interface module can be enhanced with up to 63 I/O modules from the ET 200S range.
Page 19: Guide To The Et 200S Manuals
Product Overview Guide to the ET 200S Manuals You are Using the Following Components ... The components of the ET 200S are described in various manuals in the ET 200S package. The figure below shows possible ET 200S configurations and the manuals required for them.
Page 20: With The Im 151/Cpu
Product Overview Table 1-1 Topics of the Manuals in the ET 200S Manual Package Manual ET 200S IM 151/CPU ET 200S Distributed Interface Motor Contents Chapter/ I/O System Module Starters Appendix ET 200S components ET 200S motor starter components ET 200S configuration options ET 200S motor starters configuration options Installing the ET 200S;...
Page 21: Addressing
Addressing Principle of Data Transfer Between the DP Master and the ET 200S This chapter contains information on the addressing of I/O modules and data transfer between the DP master and the IM 151/CPU. The following alternatives are available for addressing the I/O modules: Slot-oriented address allocation: Slot-oriented address allocation is the default form of addressing, in which STEP 7 allocates a fixed module base address to each slot number.
Page 22: Slot-Oriented Addressing
Addressing Slot-Oriented Addressing Slot-Oriented Address Allocation In slot-oriented addressing (default addressing) each slot number in a module is allocated an address area in the IM 151/CPU. Depending on the type of the I/O module, the addresses are digital or analog (see Table 2-1).
Page 23: Example Of Address Assignment For I/O Modules
Addressing Address Assignment Depending on the slot, 1 byte is reserved for digital I/Os and 16 bytes are reserved for analog I/Os in the address areas of the IM 151/CPU for each I/O module (maximum of 63). The table below indicates the default address assignment for analog and digital modules per slot.
Page 24: User-Defined Addressing
Addressing User-Defined Addressing User-Oriented Address Allocation User-oriented address allocation means you can select the following in units of 1 byte and independent of one another within the range 0 to 1535: Input addresses of modules Output addresses of modules The addresses 0 to 127 are in the process image. Assign the addresses in STEP 7 .
Page 25: Data Transfer With The Dp Master
Addressing Data Transfer with the DP Master User Data Transfer Via an Intermediate Memory The user data is located in an intermediate memory in the IM 151/CPU. This intermediate memory is always used when user data is transferred between the IM 151/CPU and the DP master.
Page 26: Examples Of The Maximum Configuration
Addressing Address Areas for User Data Transfer with the DP Master The ET 200S provides the PROFIBUS-DP with a maximum of 64 bytes of input data and 64 bytes of output data. This data can be addressed in the intermediate memory of the IM 151/CPU in up to 32 address areas.
Page 27: Accessing The Intermediate Memory In The Im 151/Cpu
Addressing Accessing the Intermediate Memory in the IM 151/CPU Access in the User Program The following table tells you how to access the intermediate memory in the ET 200S from the user program: Table 2-3 Accessing the Address Areas Access Dependent on Data The Following Applies Consistency 1-, 2- or 4-byte data consistency...
Page 28: Addressing Interface In Step 7 V5.1 (Extract)
When the IM 151/CPU is configured with STEP 7 for operation in the S5 or in non-Siemens systems, it is clear that only the logical addresses within the slave CPU are allocated. The addresses are then assigned in the master system using the specific configuration tool of the master system.
Page 29 Addressing Default Setting for Address Areas If, when configuring the ET 200S, you do not parameterize any address areas for data transfer with the DP master, the ET 200S starts up on the PROFIBUS-DP with a default setting. The default setting is: 16 words of input data;...
Page 30 Addressing In the IM 151/CPU Data preprocessing in the DP slave: Load actual value 2 and transfer to memory byte 6. Load input byte 0 and transfer to memory byte 7. Forward data to DP master Load memory word 6 and transfer to peripheral output word 136 In the DP Master CPU Postprocess received data in the DP master:...
Page 31 ET 200S in the PROFIBUS Network Introduction You can integrate the ET 200S with the IM 151/CPU as a node in a PROFIBUS network. This chapter contains a description of a typical network configuration with the ET 200S and the IM 151/CPU. It also tells you which functions can be executed via the programming device or OP on the ET 200S and which options are available for direct connection.
Page 32: Example Of A Profibus Network
ET 200S in the PROFIBUS Network ET 200S in the PROFIBUS Network Structure of a PROFIBUS Network The figure below illustrates the basic structure of a PROFIBUS network with one DP master and several DP slaves. S7-300 (DP master) ET 200S ET 200X OP 25** ET 200S...
Page 33 ET 200S in the PROFIBUS Network Access to the ET 200S The IM 151/CPU is a passive bus node. The programs and configuration of the IM 151/CPU can be transferred to the IM151/CPU by choosing ”Load PLC” from the programming device in SIMATIC Manager. All the other diagnostic and test functions are also possible with the programming device.
Page 34: The Pg/Op Accesses The Et 200S Via The Dp Interface In The
ET 200S in the PROFIBUS Network Examples for the Connection of the Programming Device/OP on the ET 200S The programming device/OP is connected to the PROFIBUS-DP interface of the DP master, but can be connected just as well to any other station in the DP network, including the ET 200S.
Page 35: Setting The Profibus Address
ET 200S in the PROFIBUS Network Setting the PROFIBUS Address Features Use the PROFIBUS address to specify the address at which the IM 151/CPU is contacted on the PROFIBUS-DP. Prerequisites The PROFIBUS-DP address for the IM 151/CPU is set via a DIP switch. The DIP switches are on the front of the module.
Page 36: Setting The Profibus Address
ET 200S in the PROFIBUS Network Setting the PROFIBUS Address The DIP switch has 2 functions: Switches 1-7: These are used to set the PROFIBUS addresses 1-125. Switch 8: If the IM 151/CPU is not configured, you can use this switch to toggle between stand-alone and DP slave operation in the case of a default startup.
Page 37: Network Components
ET 200S in the PROFIBUS Network Network Components To connect the ET 200S to the PROFIBUS-DP network, you need the following network components: Table 3-1 Network Components Purpose Network Components Order Numbers To set up the network Cables (e.g. 2-core, 6XV1 830-0AH10 shielded or 5-core, (2-core)
Page 38: Connecting The Dp Network
ET 200S in the PROFIBUS Network Example of the Use of Network Components The figure below shows the example from Figure 3-2 with the use of the network components. Connecting the bus cable to the bus connector is described in the Product Information document for the bus connector.
Page 39: Functions Via The Programming Device/Op
ET 200S in the PROFIBUS Network Functions via the Programming Device/OP You can use the programming device to: Configure the IM 151/CPU with ET 200S modules and put them into operation on the PROFIBUS-DP Program the CPU part of the IM 151/CPU Execute test functions such as “Monitor/Modify Variables”...
Page 40: Direct Communication
ET 200S in the PROFIBUS Network Direct Communication You can configure the IM 151/CPU as an intelligent slave with STEP 7 V 5.1 for direct communication. Direct communication is a special communication relationship between PROFIBUS-DP nodes. Principle Direct communication is characterized by the fact that the PROFIBUS-DP nodes ”listen in”...
Page 41 ET 200S in the PROFIBUS Network Functionality in Direct Communication The IM 151/CPU offers the following functionality in direct communication: Passive sender: When requested by the DP master, the IM 151/CPU, as the DP slave, sends the process outputs configured for direct communication as a broadcast frame to all bus nodes.
Page 42 ET 200S in the PROFIBUS Network ET 200S Interface Module IM 151/CPU 3-12 A5E00058783-01...
Page 43: Commissioning And Diagnostics
Commissioning and Diagnostics Configuring the IM 151/CPU with STEP 7 This chapter outlines how to configure an ET 200S for the IM 151/CPU with STEP 7 . Resetting the Memory of the IM 151/CPU Under certain circumstances you have to reset the memory of the CPU component of the IM 151/CPU.
Page 44: Configuring The Im 151/Cpu
SIMATIC S5 COM PROFIBUS Fully configured and programmed IM 151/CPU, integrated as a standard intelligent slave in COM PROFIBUS Non-Siemens Non-Siemens tool Fully configured and systems programmed IM 151/CPU, integrated as a standard intelligent slave in a non-Siemens tool Prerequisite You must have STEP 7 (as of V 5.1) open and be working in STEP 7 SIMATIC...
Page 45 8. The two stations must then be reloaded to start master-slave communication. Configuration in a Non-Siemens System Using the DDB file you can also integrate the IM 151/CPU in non-Siemens systems as a DP standard slave. In this case the diagnostic frame consists of the...
Page 46: Resetting The Memory Of The Im 151/Cpu
Commissioning and Diagnostics Resetting the Memory of the IM 151/CPU When Do You Reset the Memory of the IM 151/CPU? You must reset the memory of the IM 151/CPU if an entire new user program is to be transferred to the CPU or if the STOP indicator is flashing at 1-second intervals. The following are possible reasons for the MRES request: The ET 200S is starting up for the first time.
Page 47: How To Use The Mode Selector To Reset The Memory
Commissioning and Diagnostics STOP Max. 3 s Min. 3 s RUN-P RUN-P RUN-P RUN-P RUN-P STOP STOP STOP STOP STOP MRES MRES MRES MRES MRES Figure 4-1 How to Use the Mode Selector to Reset the Memory Is the STOP LED Not Flashing at Memory Resetting? Does the STOP LED not flash during memory reset or do other indicators come on? You must repeat steps 2 and 3.
Page 48 Commissioning and Diagnostics Note If the CPU cannot copy the contents of the memory module and requests a memory reset: Remove the memory module. Reset the CPU memory. Read out the diagnostic buffer. You can read out the diagnostic buffer with the programming device (see the STEP 7 online help system ).
Page 49: Commissioning And Startup Of The Et 200S
Commissioning and Diagnostics Commissioning and Startup of the ET 200S Commissioning the ET 200S Commission the ET 200S distributed I/O system as follows: 1. Install the ET 200S distributed I/O system (see the ET 200S Distributed I/O System manual). 2. Set the PROFIBUS address on the IM 151/CPU if you don’t require stand-alone operation (see the ET 200S Distributed I/O System manual).
Page 50 Commissioning and Diagnostics Backing Up the User Program When the ET 200S is commissioned, the user program is still not secure against a power failure, because it is only in the RAM load memory. To store the user program in a powerfail-proof location, you have the following options: Copy RAM-to-ROM: Insert an empty memory module before the program is downloaded, and acknowledge the memory reset request this causes.
Page 51: Diagnostics Using Leds
Commissioning and Diagnostics Diagnostics Using LEDs LEDs The RUN, STOP, ON, BF, SF and FRCE LEDs display important information on the states of the IM 151/CPU to the user. The IM 151/CPU has the following 6 LEDs: ”SF” LED (System Fault) for indicating the presence of a fault in the ET 200S ”BF”...
Page 52: Leds For Profibus-Dp
Commissioning and Diagnostics Diagnosis of DP Functionality Using the “BF” and “SF” LEDs If the “BF” and “SF” LEDs light up or flash, the ET 200S is not configured correctly. The table below shows you the possible error indications together with their meanings and the necessary action.
Page 53: Diagnostics Via Diagnostic Address With Step 7
Commissioning and Diagnostics Diagnostics via Diagnostic Address with STEP 7 Malfunctions that occur in the ET 200S are indicated by the “SF” LED, and the cause is entered in the diagnostic buffer of the IM 151/CPU. Either the CPU component of the IM 151/CPU goes into STOP mode, or you can respond to errors by means of error or interrupt OBs in the user program.
Page 54: Responses To Operating Mode Changes And Interruptions In User Data Transfer In The Dp Master/Et And The Et 200S With The Im 151/Cpu
Commissioning and Diagnostics Event Identification The following table indicates how the DP master or the IM 151/CPU of the ET 200S identifies changes in operating mode and interruptions in user data transfer. Table 4-5 Responses to Operating Mode Changes and Interruptions in User Data Transfer in the DP Master and the ET 200S with the IM 151/CPU What Happens ...
Page 55 Commissioning and Diagnostics Evaluation in the User Program The table below shows you how to evaluate RUN/STOP transitions in the DP master (SIMATIC S7) or ET 200S, for example. Table 4-6 Evaluation of RUN/STOP Transitions in the DP Master/ET 200S In the DP Master In the ET 200S (IM 151/CPU) Diagnostic addresses: (example)
Page 56: Slave Diagnosis
Commissioning and Diagnostics Slave Diagnosis Interrupts with STEP 7 and an S7/M7 DP Master You can trigger a process interrupt for the DP master from the user program of the IM 151/CPU. When you call SFC 7 (“DP_PRAL”), you activate an OB 40 in the user program of the DP master.
Page 57: Format Of The Slave Diagnostic Data
Commissioning and Diagnostics Structure of the Slave Diagnostic Data Byte 0 Byte 1 Station Status 1 to 3 Byte 2 Byte 3 Master PROFIBUS Address High byte Byte 4 Manufacturer ID Byte 5 Low byte Byte 6 Module Diagnostics (the length depends on the Byte x number of address areas configured for the intermediate...
Page 58: Station Status 1 To 3
Commissioning and Diagnostics 4.6.1 Station Status 1 to 3 Definition Station status 1 to 3 provides an overview of the status of a DP slave. Station Status 1 Table 4-7 Structure of Station Status 1 (Byte 0) Description Remedy 1: DP slave cannot be addressed by Is the correct DP address set on the DP DP master.
Page 59: Structure Of Station Status 2 (Byte 1)
Commissioning and Diagnostics Station Status 2 Table 4-8 Structure of Station Status 2 (Byte 1) Description 1: DP slave must be parameterized again and reconfigured. 1: A diagnostic message has arrived. The DP slave cannot continue operation until the error has been rectified (static diagnostic message). 1: This bit is always “1”...
Page 60: Master Profibus Address
Commissioning and Diagnostics 4.6.2 Master PROFIBUS Address Definition The DP address of the DP master is stored in the master PROFIBUS address diagnostic byte: The master that parameterized the DP slave The master that has read and write access to the DP slave Master PROFIBUS Address Table 4-10 Structure of the Master PROFIBUS Address (Byte 3) Description...
Page 61: Manufacturer Id
Commissioning and Diagnostics 4.6.3 Manufacturer ID Definition The manufacturer identification contains a code specifying the DP slave’s type. Manufacturer ID Table 4-11 Structure of the Manufacturer Identification (Bytes 4 and 5) Byte 4 Byte 5 Manufacturer Identification for IM 151/CPU IM 151/CPU FO ET 200S Interface Module IM 151/CPU 4-19...
Page 62: Structure Of The Module Diagnosis
Commissioning and Diagnostics 4.6.4 Module Diagnosis Definition The module diagnosis indicates for which of the configured address areas of the intermediate memory an entry has been made. The figure below shows the structure of the module diagnosis. Structure The figure below shows the structure of the module diagnosis. Bit no.
Page 63: Module Status
Commissioning and Diagnostics 4.6.5 Module Status Definition The module status, as a particular form of module diagnosis, indicates the status of the configured address areas of the intermediate memory and expands on the module diagnosis. The module status starts after the module diagnosis and varies in length according to the number of configured address areas.
Page 64: Structure Of The Station Diagnosis
Commissioning and Diagnostics 4.6.6 Structure of the Station Diagnosis The device-specific diagnosis is only issued in S7 slave operating mode. Definition The station diagnosis provides detailed information on a DP slave. The station diagnosis starts after the module status and contains a maximum of 20 bytes for the IM 151/CPU, depending on the slave operating mode and the parameter assignment frame.
Page 65: Structure Of The Station Diagnosis
Commissioning and Diagnostics Additional Interrupt Information and Diagnostic Data The meaning of the bytes as of byte (y+5) depends on byte (y+2): Table 4-12 Additional Interrupt Information and Diagnostic Data Byte (y+2) Contains the Code for... Diagnostic Interrupt (01 Process Interrupt (02 The diagnostic data contains the 16 bytes of For the process interrupt, you can program status information of the CPU component of...
Page 66: System Status List (Ssl)
Commissioning and Diagnostics System Status List (SSL) Possible System Status Sublists The following table lists all the possible sublists with the associated sublist extracts and the SSL IDs. Details on how to read out the SSL using, for example, SFC 51, and more information on the contents can be found in the following: In the System Software for S7-300/400 reference manual, in the chapter entitled System and Standard Functions, System Status List SSL...
Page 67 Commissioning and Diagnostics Table 4-13 SSL Sublists of the IM 151/CPU Sublist SSL ID Sublist Extract SSL ID Sublist Extract Module status information W#16#xy91 Module status information of all W#16#0A91 inserted modules Module status information of a W#16#0C91 module in a central configuration or at a integrated DP interface modules Module status information of all...
Page 68 Commissioning and Diagnostics ET 200S Interface Module IM 151/CPU 4-26 A5E00058783-01...
Page 69 Functions of the IM 151/CPU In This Chapter In this chapter you will find: Important features of the IM 151/CPU for the PROFIBUS-DP A list of the CPU functions of the IM 151/CPU that you can call with STEP 7 , such as the integrated clock, blocks for the user program and parameters that can be set Chapter Overview...
Page 70: Attributes Of The Device Database (Ddb) File
(configuration with COM PROFIBUS). You are using the ET 200S with a non-SIMATIC DP master (configuration with a non-Siemens tool). You can download the DDB file from the Internet. You will find all the DDB files under “Downloads” on the SIMATIC Customer Support web site: http://www.ad.siemens.de/support/html_00/index.shtml...
Page 71 Functions of the IM 151/CPU Tabelle 5-1 Attributes of the Device Database (DDB) File Feature DP Keyword to IEC 61158/EN IM 151/CPU 50170, Volume 2, PROFIBUS Supports 12 Mbps 12M_supp Supports the FREEZE control command Freeze_Mode_supp Supports the SYNC control command Sync_Mode_supp Supports automatic baud rate detection Auto_Baud_supp...
Page 72: Mode Selector
Functions of the IM 151/CPU The Mode Selector and LEDs Mode Selector The mode selector of the IM 151/CPU is designed as a 3-step toggle switch (see below): RUN–P STOP MRES Figure 5-1 Mode selector Positions of the Mode Selector The positions of the mode selector are explained in the order in which they are arranged on the IM 151/CPU.
Page 73: Leds For Cpu Functionality
Functions of the IM 151/CPU Meanings of the LEDs for CPU Functionality For the CPU component of the IM 151/CPU there are 2 separate LEDs that indicate the operating modes of the CPU: HALT STOP You can obtain information on the power supply of the CPU, on force requests and on general errors via 3 additional LEDs.
Page 74: Principle Behind Forcing
Functions of the IM 151/CPU Force Force Test Function In the case of the IM 151/CPU, you can preset the inputs and the outputs in the process image with fixed values using the “Force” function. The values (force values) you have preset can still be controlled in the IM 151/CPU by the user program and by programming device/operator panel functions.
Page 75 Functions of the IM 151/CPU Note Due to insufficient battery backup, force requests do not survive after power off/power on. Application Example Prerequisite: There is no direct I/O access in your user program. If, for example, an enable sensor (f) in your system is defective and it continually indicates a logical 0 to your user program, for example, via input 1.2, you can bridge this sensor by forcing the input to 1, ensuring that your system continues to operate.
Page 76: Available Mmcs
Functions of the IM 151/CPU Memory Module Micro Memory Card A micro memory card (MMC) is used as a memory module for the IM 151/CPU. The MMC module can be used as a load memory and portable data carrier. The following data is stored on the MMC: User program (all blocks) Configuration data (created with STEP 7 )
Page 77: Position Of The Memory Card Slot For The Mmc On The Im 151/Cpu
Functions of the IM 151/CPU Inserting/Changing the Card The MMC is designed so that it can also be removed and inserted when the power is on. The chamfered edge of the MMC prevents the card being inserted the wrong way round (reverse polarity protection). There is an eject button on the memory card slot to enable you to remove the card easily.
Page 78: Firmware Update With Mmc
Functions of the IM 151/CPU Firmware Update with MMC To update the firmware, proceed as follows: Table 5-5 Firmware Update with MMC Step Action Required What Happens in the IM 151/CPU: Transfer update files to a blank MMC using STEP 7 and your programming device.
Page 79: Backing Up The Operating System
Functions of the IM 151/CPU Backing Up the Operating System on the MMC To back up the operating system, proceed as follows: Table 5-6 Backing Up the Operating System Step Action Required What Happens in the IM 151/CPU: Insert a new micro memory card The CPU requests a memory (2 MB) in the CPU reset...
Page 80: Features Of The Clock
Functions of the IM 151/CPU Clock The IM 151/CPU has an integrated software clock. Setting, Reading and Programming the Clock You set and read the clock using the programming device (see the STEP 7 ) User Manual) or program the clock in the user program using SFCs (see the System and Standard Functions Reference Manual and Appendix C).
Page 81: Overview Of The Blocks
Functions of the IM 151/CPU Blocks This section provides an overview of the blocks that run in the CPU component of the IM 151/CPU. The operating system of the CPU is designed for event-driven processing of the user program. The following tables show which organization blocks (OBs) the operating system automatically invokes in response to which events.
Page 82: Obs For Cycle And Restart
Functions of the IM 151/CPU OBs for Cycle and Restart Table 5-9 OBs for Cycle and Restart Cycle and Restart Invoked OB Possible Start Events Cycle OB 1 First OB 1 after restart (power on or STOP-RUN transition of the IM 151/CPU) Termination of the previous program cycle Restart (change from STOP to OB 100...
Page 83: Obs For Error/Fault Responses
Functions of the IM 151/CPU OBs for Error/Fault Responses Table 5-11 OBs for Error/Fault Responses Error/Fault Invoked OB Possible Start Events Time-out OB 80 Cycle time exceeded Acknowledgment error during OB processing Putting the clock forward (time jump) to start an OB Program execution OB 85 Start event for an OB not loaded...
Page 84 Functions of the IM 151/CPU Parameters Parameterizable Properties of the CPU The properties and responses of the CPU component of the IM 151/CPU can be parameterized. You carry out this parameterization on different tabs in STEP 7 . Which Parameters Can Be Set for the IM 151/CPU? The following table contains all the parameter blocks for the IM 151/CPU.
Page 85 Functions of the IM 151/CPU Table 5-12 Parameter Blocks, Settable Parameters and Their Ranges for the IM 151/CPU Parameter Blocks Settable Parameters Range Start date for the OB 10 Year-month-day Start time for the OB 10 Hours:minutes Cyclic interrupts Periodicity of the OB 35 (ms) 1 to 60000 Cycle behavior Cycle load from communication (%)
Page 86: Parameterization Of The Reference Junction
Functions of the IM 151/CPU Parameterization of the Reference Junction for the Connection of Thermocouples If you want to use the IM 515/CPU in an ET 200S system with thermocouples and reference junctions, set the following parameters in the hardware configuration: Table 5-13 Parameterization of the Reference Junction CPU Module Parameter Range...
Page 87: Example Of A Parameterization Dialog Box For The Cpu Module Data In Step 7 V5.1
Functions of the IM 151/CPU Figure 5-4 Example of a Parameterization Dialog Box for the CPU Module Data in STEP 7 V5.1 Reference You can find detailed information on the procedure, the connection system and an example of parameterization in the chapter entitled Analog Electronic Modules in the ET 200S Distributed Device manual.
Page 88 Functions of the IM 151/CPU Removal and Insertion of Modules During Operation Removing and inserting one module at a time in the case of the IM 151/CPU with local ET 200S I/Os is possible during operation and in an energized state. Exceptions The CPU itself must not be removed during operation and in an energized state.
Page 89: Result Of The Preset/Actual Comparison In Modules That Cannot Be Parameterized
Functions of the IM 151/CPU Modules that Cannot be Parameterized The following activities occur irrespective of whether the power module of the inserted module is switched on or off. Table 5-14 Result of the Preset/Actual Comparison in Modules that Cannot be Parameterized Inserted Module = Configured Module Inserted Module Configured Module...
Page 90 Functions of the IM 151/CPU 5.10 Switching Power Modules Off and On During Operation What Happens When Power Modules Are Switched Off During Operation If the load power voltage to a power module is switched off during operation, the following activities take place: If you enable diagnostics during parameter assignment for the power module, diagnostic interrupt OB 82 (diagnostic address of the power module) is called with the corresponding diagnostic buffer entry (event 3942...
Page 91 Technical Specifications In This Chapter In this chapter you will find: The technical specifications of the IM 151/CPU interface module Chapter Overview Contents Page Section Technical Specifications of the IM 151/CPU ET 200S Interface Module IM 151/CPU A5E00058783-01...
Page 92 Technical Specifications Technical Specifications of the IM 151/CPU Order Numbers IM 151/CPU interface module: 6ES7 151-7AA00-0AB0 IM 151/CPU FO interface module: 6ES7 151-7AB00-0AB0 MMC (Micro Memory Card): 6ES7 953-8Lx00-0AA0 (see Section 5.4, Memory Modules) Features The IM 151/CPU interface module has the following features: Intelligent slave with RS485 interface or fiber-optic cable to the PROFIBUS-DP Stand-alone operation possible 24 KB working memory, not buffered...
Page 93: Terminal Assignment Of The Im 151/Cpu Interface Module
Technical Specifications Terminal Assignment for the IM 151/CPU Table 6-1 Terminal Assignment of the IM 151/CPU Interface Module View Signal Name Description 1 – – IM 151/CPU IM 151/CPU 2 – – 3 RxD/TxD-P Data line B 4 RTS Request To Send 5 M5V2 Data reference potential (from the station)
Page 94: Basic Circuit Diagram For The Im 151/Cpu
Technical Specifications Basic Circuit Diagram for the IM 151/CPU PROFIBUS-DP connection Backplane bus (RS485) ET 200S STOP Galvanic backplane bus isolation interface module PROFIBUS address ( P, ROM, RAM) RUN-P STOP MRES Mode selector FRCE Internal power supply Figure 6-1 Basic Circuit Diagram for the IM 151/CPU Basic Circuit Diagram for the IM 151/CPU FO PROFIBUS-DP connection (RS485)
Page 95 Technical Specifications Technical Specifications CPU and Product Version Data areas and their retentive characteristics MLFB 6ES7 151-7AA00-0AB0 Total retentive data area Max. 4736 bytes (incl. memory markers, timers, counters) 6ES7 151-7AB00-0AB0 Bit memories 256 bytes Hardware version Adjustable retentivity MB 0 to MB 255 Firmware version V1.0.0 Preset retentivity...
Page 96 Technical Specifications S7 message functions Interface Process diagnostic ALARM_S, ALARM_SQ Type of interface Integrated Fiber-optic messages RS 485 interface interface Testing and commissioning functions Integrated Status/Modify Variables RS 485 Variable Inputs, outputs, flags, interface data, timers, counters Physical system RS 485 Number of variables –...
Page 97 Technical Specifications Programming Power supply Rated value 24 V DC Programming language STEP 7 Permissible range 20,4 to 28,8 V Stored instructions See Appendix B Polarity reversal protection Nesting levels Voltage failure 20 ms System functions See Appendix C buffering (SFCs) Insulation tested at 500 V DC...
Page 98 Technical Specifications ET 200S Interface Module IM 151/CPU A5E00058783-01...
Page 99 Cycle and Response Times Introduction In this chapter you will learn what make up the cycle and response times of the ET 200S with the IM 151/CPU. You can use the programming device to read out the cycle time of your user program (see the STEP 7 User Manual ).
Page 100: Component Parts Of The Cycle Time
Cycle and Response Times Cycle time Cycle Time – A Definition The cycle time is the time that the operating system requires to process a program cycle – i.e. an OB 1 cycle – as well as all the program sections and system activities interrupting this cycle.
Page 101: Process Image Updating
Cycle and Response Times Extending the Cycle Time Note that the cycle time of a user program is extended by the following: Time-controlled interrupt handling Process interrupt handling (see also Section 7.3) Diagnostics and error handling (see also Section 7.3) Operating System Processing Time The operating system processing time for the IM 151/CPU takes 540 s to 1040 s...
Page 102: Dependency Of The User Program Scanning Time
Cycle and Response Times User Program Scanning Time: The user program scanning time is made up of the sum of the execution times for the instructions and SFCs called. These execution times can be found in the Instruction List. You also have to multiply the user program scanning time by a basic module-specific factor.
Page 103: Extending The Cycle By Nesting Interrupts
Cycle and Response Times Delay of the Inputs and Outputs You have to take into account the following delay times, depending on the expansion module: For digital inputs: The input delay time For digital outputs: Negligible delay times For analog inputs: Cycle time of the analog input For analog outputs: Response time of the analog output...
Page 104 Cycle and Response Times Response Time Response Time for the ET 200S with the IM 151/CPU The response time is the time from the detection of an input signal at the ET 200S with the IM 151/CPU to the modification of an associated output signal via the inputs and outputs of the expansion modules.
Page 105: Shortest Response Time
Cycle and Response Times Shortest Response Time The following figure shows you the conditions under which the shortest response time is obtained. Delay of the inputs The status of the observed input changes immediately before reading in the PII. The change in the input signal is therefore taken account of in the PII.
Page 106: Longest Response Time
Cycle and Response Times Longest Response Time The following figure shows what the longest response time consists of. Delay of the inputs While the PII is being read in, the status of the observed input changes. The change in the input signal is no longer taken into account in the PII.
Page 107: Interrupt Response Times Of The Im 151/Cpu (Without Communication)
Cycle and Response Times Interrupt Response Time Interrupt Response Time – A Definition The interrupt response time is the time from the first occurrence of an interrupt signal to the call of the first instruction in the interrupt OB of the IM 151/CPU. It generally applies that the interrupt response time is increased by the program scanning time of the interrupt OBs that have not yet been processed.
Page 108 Cycle and Response Times ET 200S Interface Module IM 151/CPU 7-10 A5E00058783-01...
Page 109 Getting Started Introduction This guide takes you through the 10 commissioning steps required to set up a functioning application by running through a concrete example. In this way, you will get to know the basic functions of your IM 151/CPU for the following: Hardware and software Stand-alone operation and as an intelligent DP slave Prerequisites...
Page 110 *HWWLQJ 6WDUWHG 0DWHULDOV DQG 7RROV 5HTXLUHG 4XDQWLW\ ,WHP 2UGHU 1XPEHU 6,(0(16 S7-300 system, consisting of power supply (PS), CPU with Various DP interface(CPU 315 2-DP in this example), digital input module (DI) on slot 4 and digital output module (DO) on slot 5, incl.
Page 111 *HWWLQJ 6WDUWHG 6WHS ,QVWDOOLQJ WKH (7 6,0 &38 DQG 6 6WDJH 'HVFULSWLRQ Install the S7-300 as described in the S7-300 Programmable Controller, Hardware and Installation manual or in STEP 7 V5.0 Getting Started . If you want to operate the IM 151/CPU with its own power supply, attach it to the S7-300 rail and tip it down until it snaps into position.
Page 112 *HWWLQJ 6WDUWHG 6WHS :LULQJ WKH (7 6,0 &38 DQG 6 6WDJH 'HVFULSWLRQ Wire the S7-300 as described in the S7-300 Programmable Controller, Hardware and Installation manual or in STEP 7 Getting Started, V5.0 . Extend the connections of the 4 switches using a cable. Strip 6 mm off the cable ends and attach wire end ferrules.
Page 113 *HWWLQJ 6WDUWHG 6WHS 3XWWLQJ WKH (7 6,0 &38 LQWR 2SHUDWLRQ 6WDJH 'HVFULSWLRQ Make sure that the mode selector is at STOP . Switch on the lowest DIP switch (for stand- alone operation) and the 4th DIP switch from the bottom (for PROFIBUS-DP address 4) on the IM 151/CPU.
Page 114 *HWWLQJ 6WDUWHG 6WHS &RQILJXULQJ WKH ,0 &38 IRU 6WDQG$ORQH 2SHUDWLRQ 6WDJH 3URFHGXUH 5HVXOW Does the assistant for a new project appear in If so: Close the assistant because it SIMATIC Manager? doesn‘t support the IM 151/CPU. If not: Continue to stage 2 In SIMATIC Manager, choose New from the File A new project is created and opened.
Page 115 *HWWLQJ 6WDUWHG Click 1HZ in the dialog box that appears, and check that the settings in the dialog box are as shown here: Close the dialog box with 2. Navigate to the 30 via the relevant ,0 &38. Insert the 30 whose order number corresponds to the order number on your PM by dragging and dropping it onto slot 4.
Page 116 *HWWLQJ 6WDUWHG 6WHS 3URJUDPPLQJ WKH ,0 &38 6WHS 3URFHGXUH 5HVXOW Navigate in SIMATIC Manager via ,0 &38 and 6 3URJUDP to the %ORFNV container. Double-click the 2% icon in the right-hand part of The LAD/FBD/STL editor for editing the window. the OB1 block opens.
Page 117 *HWWLQJ 6WDUWHG 6WHS 7HVW 5XQ 6WDJH 3URFHGXUH 5HVXOW In SIMATIC Manager, click %ORFNV in the left-hand %ORFNV is highlighted. part of the dialog box. Right-click the right-hand part of the window, and The blocks OB82 and OB86 appear insert an empty organization block with the name next to block OB1.
Page 118 *HWWLQJ 6WDUWHG 6WHS &RQYHUWLQJ WKH ,0 &38 WR D '3 6ODYH DQG 3XWWLQJ WKH 6 LQWR 2SHUDWLRQ 6WDJH 'HVFULSWLRQ Remove the connector of the programming device cable from the IM 151/CPU. Start the Setting the PG/PC Interface program as described in stage 6 of step 3. Change the configuration of the programming device/PC interface as follows: Apply the settings with OK, and close the Setting the PG/PC Interface program.
Page 119 *HWWLQJ 6WDUWHG 6WHS &RQILJXULQJ WKH ,0 &38 DV D '3 6ODYH DQG WKH 6 DV D '3 0DVWHU Change the configuration of the IM 151/CPU as shown below: 6WDJH 3URFHGXUH 5HVXOW Start the hardware configuration program as The hardware configuration editor described in step 4 for the IM 151/CPU.
Page 120 *HWWLQJ 6WDUWHG If a catalog is not displayed in the right-hand part of the window, activate the catalog by choosing the &DWDORJ command from the 9LHZ menu. Navigate in the catalog to 5DFN via 6,0$7,& Insert a rail by dragging and dropping it in the window in the upper-left corner.
Page 121 *HWWLQJ 6WDUWHG In the dialog box that appears, click the ,QWHUFRQQHFW button In the dialog box, select the Configuration tab and fill it in as shown in the screen shot. Confirm with 2. From the 6WDWLRQ menu, choose the 6DYH DQG The hardware configuration is &RPSLOH command compiled and saved, and the editor is...
Page 122 *HWWLQJ 6WDUWHG 6WHS 3URJUDPPLQJ WKH ,0 &38 DQG WKH 6 &38 6WDJH 3URFHGXUH 5HVXOW Navigate in SIMATIC Manager to the block container The LAD/FBD/STL editor is opened to of the ET 200S. edit block OB1. Double-click the 2% icon in the right-hand part of the window.
Page 123 *HWWLQJ 6WDUWHG Add to the OB1 of the S7-300 CPU as shown below: +RZ LW ZRUNV The status of the switch connected to I1.1 of the S7-300 is queried and temporarily stored in memory marker M13.0. The entire MB13 memory byte is transferred to the PQB12 I/O output byte.
Page 124 *HWWLQJ 6WDUWHG 6WHS 3XWWLQJ WKH ,0 &38 DQG 6 LQWR 2SHUDWLRQ DQG &DUU\LQJ 2XW D 7HVW 5XQ 6WDJH 3URFHGXUH 5HVXOW Navigate in SIMATIC Manager to the block container of the S7-300, and insert an empty organization block with the name 2% in the block container. This block ensures that the S7-300 CPU will start even if the IM157/CPU is still indicating an I/O error.
Page 125 *HWWLQJ 6WDUWHG Confirm the settings with OK, and close the Setting the PG/PC Interface program. Open the front panel of the S7-300 CPU. Remove the connector of the programming device cable from the MPI interface of the S7-300 CPU, and put it on the bus connector of the PROFIBUS-DP cable on the S7-300 CPU. Secure the connector.
Page 126 We recommend that you also read the following Getting Started document: *HWWLQJ 6WDUWHG ± )LUVW 6WHSV ZLWK 67(3 9. You can download all the manuals free of charge from the Siemens home page (Automation and Drives Customer Support). 8-18...
Page 127 Configuration Frame and Parameter Assignment Frame for the ET 200S By configuring the DP master you can specify which ID format should be used in the configuration frame: Configuration in STEP 7 with HWConfig: Integration of the IM 151/CPU slave, during operation on the S7 master: Special ID format SKF Configuration with another configuration tool: Integration of the IM 151/CPU slave via the DDB: Normal ID format AKF...
Page 128 Configuration Frame and Parameter Assignment Frame for the ET 200S Structure of the Configuration Frame (SKF) The length of the configuration frame depends on the number of address areas configured in the intermediate memory of the CPU component. The first 15 bytes in the configuration frame are already allocated because the first 3 identifiers of the 5-byte IDs are constant.
Page 129: Description Of Byte 0 Of The Address Area Identifiers
Configuration Frame and Parameter Assignment Frame for the ET 200S Identifiers for the Address Areas The identifiers for configuration depend on the type of the address area. The following table lists all the identifiers for the address areas. Table A-2 Identifiers for the Address Areas of the Intermediate Memory Identifiers (Hexadecimal) Length Byte...
Page 130 If your DP master doesn’t support the configuration frame in the special ID format (e.g. a non-SIMATIC DP master), you can obtain a DDB file with the normal ID format on the Internet at http://www.ad.siemens.de/csi/gsd (see also Section 5.1). Structure of the Configuration Frame The length of the configuration frame depends on the number of configured address areas of the intermediate memory of the CPU component.
Page 131 Configuration Frame and Parameter Assignment Frame for the ET 200S Configuration Frame with the Default Setting for Address Areas If you don’t parameterize the IM 151/CPU and therefore don’t specify any address areas for data transfer with the DP master, the IM 151/CPU will start up after commissioning with a default setting on the PROFIBUS-DP.
Page 132: Standard Section Of The Parameter Assignment Frame
Configuration Frame and Parameter Assignment Frame for the ET 200S Structure of the Parameter Assignment Frame All the parameterizable values of a DP slave are stored in the parameter assignment frame. Structure of the Parameter Assignment Frame The length of the parameter assignment frame for the IM 151/CPU is 16 bytes: Standard section;...
Page 133: General Section Of The Parameter Assignment Frame For The Im 151/Cpu
Configuration Frame and Parameter Assignment Frame for the ET 200S Structure of the General Parameters for the IM 151/CPU The length of the general parameters for the IM 151/CPU is 3 bytes. The following parameters can be set: Bit no. Byte 7 DPV1_Status_1 Watchdog timer 0: 10 ms (different DP master)
Page 134 Configuration Frame and Parameter Assignment Frame for the ET 200S ET 200S Interface Module IM 151/CPU A5E00058783-01...
Page 135 Instruction List This appendix contains the entire set of instructions available to you for programming the CPU component of the IM 151/CPU using STEP 7 . The typical execution time is also specified for each instruction. You will find detailed descriptions of all the instructions, together with examples, in the STEP 7 programming manuals .
Page 136 Instruction List Address Identifiers and Parameter Ranges Para- Description 0 to 254 Local data word dress meter 0 to 252 Local data double word Range 0.0 to Memory markers 0.0 to Output (in PIO) 255.7 127.7 0 to 255 Memory byte 0 to 127 Output byte (in PIQ) 0 to 254...
Page 137 Instruction List Abbreviations The following abbreviations and mnemonics are used in the Instruction List: Abbre- Stands for Example viation 8-bit constant 16-bit constant 62 531 32-bit constant 127 624 8-bit integer –155 16-bit integer +6523 32-bit integer –2 222 222 P#x.y (pointer) P#240.3 Binary constant...
Page 138 Instruction List Address Registers AR1 and AR2 (32 Bits) The address registers contain the area-specific or general addresses for instructions that use register-indirect addressing. The address registers are 32 bits long. The area-internal and/or area-crossing addresses have the following structure: Area-internal address: 00000000 00000bbb bbbbbbbb bbbbbxxx Area-crossing address:...
Page 139 Instruction List Examples of Addressing Addressing Examples Description Direct Addressing L +27 Load 16-bit integer constant ”27” into ACCU1 L L#–1 Load 32-bit integer constant ”–1” into ACCU1 L 2#1010101010101010 Load binary constant into ACCU1 L DW#16#A0F0 BCFD Load hexadecimal constant into ACCU1 L ’END’...
Page 140 Instruction List Addressing Examples Description Area-Crossing, Memory-Indirect Addressing For area-crossing, register-indirect addressing, bits 24 to 26 of the address must also con- tain an area identifier. The address is in the address register. Area Coding Area identifier Binary Hex. 1000 0000 80I/O area 1000 0001 81Input area...
Page 141 Instruction List Execution Times with Indirect Addressing Two-Part Statement A statement with indirectly addressed instructions consists of 2 parts: Part 1: Loading the Address of the Address ID Part 2: Executing the Instruction In other words, you must calculate the execution time of a statement with indirectly addressed instructions from these two parts.
Page 142 Instruction List Address Is In ... Execution Time in Parameter (word) ... for: Timers Counters Block calls Parameter (double word) ... for: Bits, bytes, words and double words ET 200S Interface Module IM 151/CPU A5E00058783-01...
Page 143 Instruction List B.5.1 Example of Memory-Indirect, Area-Internal Addressing Example Example: A I [DBD 12] Step 1 Load the contents of DBD 12 Address Is In ... Execution Time in s Memory marker area M Word Double word Data block DB/DX Word Double word Step 2...
Page 144 Instruction List B.5.2 Example of Register-Indirect, Area-Internal Addressing Example A I [AR1, P#34.3] Step 1 Load the contents of AR1 and increment it by the offset 34.3 Address Is In ... Execution Time in AR1/AR2 (area-internal) Step 2 ANDing of the addressed input (the execution time is in Appendix B.6 and the following chapters).
Page 145 Instruction List B.5.3 Example of Memory-Indirect, Area-Crossing Addressing Example U [AR1, P#23.1] ... with P#E 1.0 in the AR1 Step 1 Load the contents of AR1 and increment it by the offset 23.1 Address Is In ... Execution Time in AR1/AR2 (area-crossing) Step 2 ANDing of the addressed input (the execution time is in Appendix B.6 and the...
Page 146 Instruction List B.5.4 Example of Addressing Via Parameters Example A parameter ... with I 0.5 in the block parameter list Step 1 Loading the I 0.5 addressed via the parameter. Address Is In ... Execution Time in Parameter (double word) Step 2 ANDing of the addressed input (the execution time is in Appendix B.6 and the following chapters).
Page 147 Instruction List Bit Logic Instructions Examination of the signal state of the addressed instruction and gating of the result with the RLO in accordance with the appropriate logic function. Instru- Length Typical Execution Time in ction Address ID Description Direct Addres- Indirect Ad- Words sing...
Page 148 Instruction List Instru- Length Typical Execution Time in s ction Address ID Description Direct Addres- Indirect Ad- Words sing dressing EXCLUSIVE OR Input/output 1.6+ Memory markers 1.7+ Local data bit 1.9+ DBX/DIX Data bit 2.5+ [AR1,m] I/Q/M/L/DBX/DIX (addressed – [AR2,m] (area-crossing) via AR1/AR2 or via –...
Page 149 Instruction List Logic Instructions with Parenthetical Expressions Saving of the BR, RLO and OR bits and a function identifier (A, AN, ...) to the nesting stack. 7 nesting levels are possible per block. Length Instruc- Typical Execution Time in dress Description tion Words...
Page 150 Instruction List ORing of AND Operations The ORing of AND functions is carried out according to the principle: AND before Length Address Address Typical Execution Time in Typical Execution Time in Description Description str c struc- tion Words The ORing of AND functions is carried out according to the principle: AND before OR.
Page 151 Instruction List Logic Instructions with Timers and Counters Querying of the signal state of the addressed timer/counter and gating of the result with the RLO in accordance with the corresponding function. Instru- Length Typical Execution Time in s ction Address ID Description Direct Addres- Indirect Ad-...
Page 152 Instruction List B.10 Logic Instructions with the Contents of Accumulator 1 Gating of the contents of ACCU1 or ACCU1-L with a word or double word in accordance with the appropriate function. The word or double word is either a constant in the instruction or in ACCU2. The result is in ACCU1 or ACCU1-L. Length Address Description...
Page 153 Instruction List B.11 Logic Instructions with Condition Code Bits Examination of the signal state of the specified conditions and gating of the result with the RLO in accordance with the appropriate logic function. Length Address Typical Execution struc- Description Time in s tion Words AND result=0...
Page 154 Instruction List Length Address Typical Execution struc- Description Time in s tion Words AND NOT result=0 (CC 1=0) and (CC 0=0) >0 AND NOT result>0 (CC 1=1) and (CC 0=0) <0 AND NOT result<0 (CC 1=0) and (CC 0=1) <>0 AND NOT result 0 ((CC 1=0) and (CC 0=1) or (CC 1=1) and (CC 0=0))
Page 155 Instruction List Length Address Typical Execution Time in struc- Description tion Words OR result=0 (CC 1=0) and (CC 0=0) >0 OR result>0 (CC 1=1) and (CC 0=0) <0 OR result<0 (CC 1=0) and (CC 0=1) <>0 OR result 0 ((CC 1=0) and (CC 0=1) or (CC 1=1) and (CC 0=0)) <=0 OR result<=0...
Page 156 Instruction List Length Address Address Typical Execution Time in Typical Execution Time in Description Description str c struc- tion Words OR NOT result=0 (CC 1=0) and (CC 0=0) >0 OR NOT result>0 (CC 1=1) and (CC 0=0) <0 OR NOT result<0 (CC 1=0) and (CC 0=1) <>0 OR NOT result 0...
Page 157 Instruction List Length Address Typical Execution Time in struc- Description tion Words EXCLUSIVE OR result=0 (CC 1=0) and (CC 0=0) >0 EXCLUSIVE OR result>0 (CC 1=1) and (CC 0=0) <0 EXCLUSIVE OR result<0 (CC 1=0) and (CC 0=1) <>0 EXCLUSIVE OR result 0 ((CC 1=0) and (CC 0=1) or (CC 1=1) and (CC 0=0)) <=0...
Page 158 Instruction List Length Address Typical Execution Time in struc- Description tion Words EXCLUSIVE OR NOT result=0 (CC 1=0) and (CC 0=0) >0 EXCLUSIVE OR NOT result>0 (CC 1=1) and (CC 0=0) <0 EXCLUSIVE OR NOT result<0 (CC 1=0) and (CC 0=1) <>0 EXCLUSIVE OR NOT result 0 ((CC 1=0) and (CC 0=1) or (CC 1=1) and...
Page 159 Instruction List B.12 Edge-Triggered Instructions Detection of an edge change. The current signal state of the RLO is compared with the signal state of the instruction or ”edge memory marker”. FP detects an edge change from ”0” to ”1”. FN detects an edge change from ”1” to ”0”. Length Typical Execution Time in stru-...
Page 160 Instruction List B.13 Setting/Resetting Bit Addresses Assignment of the value ”1” or ”0” or the RLO to the addressed instruction. The instructions can be dependent on the MCR. Length Typical Execution Time in stru- Address Address Description Description ction Words Direct Ad- Indirect Ad- dressing...
Page 161 Instruction List B.14 Instructions Directly Affecting the RLO The following instructions have a direct effect on the RLO. Length Address Typical Execution Time in struc- Description tion Words Set RLO to ”0” Status word for:CLR Instruction depends on: – – –...
Page 162 Instruction List B.15 Timer Instructions Starting or resetting of a timer (addressed directly or via a parameter). The duration must be in ACCU1-L. Length Typical Execution Time in stru- Address Address Description Description ction Words Direct Ad- Indirect Ad- dressing dressing Start timer as pulse on edge change from 1**/2...
Page 163 Instruction List B.16 Counter Instructions The count is in ACCU1-L and in the address passed as a parameter. Length Typical Execution Time in s Address Address stru- Description Direct Addres- Indirect Ad- ction Words sing dressing Preset counter at edge change 1**/2 7.1+ from ”0”...
Page 164 Instruction List B.17 Load Instructions Loading the instructions in ACCU1. The old contents of ACCU1 are saved to ACCU2 first. The status word is not affected. Length Typical Execu- Typical Execu- stru- tion Time in s tion Time in s Address Address Description...
Page 165 Instruction List Length Typical Execution Time in s Address Address stru- Description Direct Addres- Indirect Ad- ction Words sing dressing Load (area-crossing addressing) ..B[AR1,m] Byte 40.1+ B[AR2,m] – 40.1+ W[AR1,m] W[AR1,m] Word Word 45.6+ 45.6+ W[AR2,m] – 45.6+ D[AR1,m] Double word 57.4+ D[AR2,m]...
Page 166 Instruction List B.18 Load Instructions for Timers and Counters Loading of a time value or count value into ACCU1. The contents of ACCU1 are saved to ACCU2 first. The indicators are not affected. Length Typical Execution Time in stru- Address Address Description Description...
Page 167 Instruction List B.19 Transfer Instructions Transfer of the contents of ACCU1 to the addressed instruction. The status word is not affected. Remember that some transfer instructions depend on the MCR. Length Typical Execution Time in stru- Address Address Description Description ction Words Direct Ad-...
Page 168 Instruction List Length Address Direct Ad- Indirect Ad- stru- Description dressing dressing ction Words Transfer contents of ACCU1–L to ... Input word 1**/2 1.5+ (MCR-dependent) 1.8+ Output word 1**/2 1.5+ (MCR-dependent) 1.8+ Peripheral output byte 1***/2 < 135 < 137 (MCR-dependent) <...
Page 169 Instruction List B.20 Load and Transfer Instructions for Address Registers Loading of a double word from a memory area or register into AR1 or AR2 or transfer of a double word from AR1 or AR2 to a memory area or register. The status word is not affected.
Page 170 Instruction List B.21 Load and Transfer Instructions for the Status Word Length Address Typical Execution Time in Description struc- tion Words Load status word* into ACCU1 Status word for: L STW Instruction depends on: Instruction controls: – – – – –...
Page 171 Instruction List B.23 Fixed-Point Math Instructions (16 Bits) Math instructions of two 16-bit numbers. The result is in ACCU1–L. Length Address Typical Execution Time in Description struc- tion Words – Add 2 integers (16 bits) (ACCU1-L)=(ACCU1-L)+ (ACCU2-L) –I – Subtract 2 integers (16 bits) (ACCU1-L)=(ACCU2-L)–...
Page 172 Instruction List B.24 Fixed-Point Math Instructions (32 Bits) Math instructions of two 32-bit numbers. The result is in ACCU1. Length Address Typical Execution Time in Description struc- tion Words – Add 2 integers (32 bits) (ACCU1)=(ACCU2)+(ACCU1) –D – Subtract 2 integers (32 bits) (ACCU1)=(ACCU2)–(ACCU1) –...
Page 173 Instruction List B.25 Floating-Point Math Instructions (32 Bits) The result of the math instructions is in ACCU1. The execution time of the instruction depends on the value to be calculated. Length Address Typical Execution Time in struc- Description tion Words –...
Page 174 Instruction List B.27 Addition via the Address Register Addition of an integer (16 bits) to the contents of the address register. The value is in the instruction or in ACCU 1-L. The indicators are not affected. Length Address Address Typical Execution Time in Typical Execution Time in Description Description...
Page 175 Instruction List B.29 Comparison Instructions with Integers (32 Bits) Comparison of the 32-bit integers in ACCU1 and ACCU2. RLO=1 if the condition is satisfied. Length Address Typical Execution Time in struc- Description tion Words ACCU2=ACCU1 <>D ACCU2 ACCU1 <D ACCU2<ACCU1 <=D ACCU2<=ACCU1 >D...
Page 176 Instruction List B.30 Comparison Instructions (32-Bit Real Numbers) Comparison of the 32-bit real numbers in ACCU1 and ACCU2. RLO=1 if the condition is satisfied. The execution time of the instruction depends on the value to be compared. Length Address Typical Execution Time in Description struc- tion...
Page 177 Instruction List B.31 Shift Instructions Shift the contents of ACCU1 or ACCU1-L by the specified number of places to the left/right. If an address ID is not specified, shift by the number specified in ACCU2-LL. Positions that become free are padded with zeros or a sign. The last bit shifted is in condition code bit CC 1.
Page 178 Instruction List B.32 Rotate Instructions Rotation of the contents of ACCU1 to the left or right by the specified number of places. If an address ID is not specified, rotate by the number specified in ACCU2-LL. Length Address Typical Execution Time in Description struc- tion...
Page 179 Instruction List B.33 ACCU Transfer Instructions, Incrementing, Decrementing Status Word The status word is not affected. Length Address Typical Execution Time in Description struc- tion Words Reverse the order of the bytes in ACCU1–L LL, LH becomes LH, LL. Reverse the order of the bytes in ACCU1 LL, LH, HL, HH becomes HH, HL, LH, LL.
Page 180 Instruction List B.35 Data Type Conversion Instructions Result The results of the conversion are in ACCU1. The execution time for the conversion of real numbers depends on the value. Length Address Typical Execution Time in struc- Description tion Words – Convert contents of ACCU1 from BCD to integer (16 bits) (BCD To Int) –...
Page 181 Instruction List B.36 Complement Formation Length Address Typical Execution Time in struc- Description tion Words INVI Create ones complement of ACCU1-L INVD Create ones complement of ACCU1 Status word for: INVI, INVD Instruction depends on: – – – – – –...
Page 182 Instruction List B.37 Block Call Instructions Length Typical Execution Time in stru- Words ction Address Description Direct Ad- Indirect Ad- dressing dressing CALL Unconditional call of a function 1**/2 Unconditional call of a function of the ope- See Appendix C for execution rating system times Unconditional call of blocks without para-...
Page 183 Instruction List B.38 Block End Instructions Address Typical Execution Time in struc- Description Length tion Words End block End block unconditionally – Status word for: BE, BEU Instruction depends on: – – – – – – – – – Instruction controls: –...
Page 184 Instruction List B.40 Jump Instructions Jumping as a function of conditions. The jump width in an 8-bit address ID is between (–128 to +127). The jump width in 16-bit address IDs is between (–32768 to –129) or (+128 to +32767). Note on JC Please note in the case of CPU 614 programs that the jump destination always forms the beginning of a Boolean logic string.
Page 185 Instruction List Length Address Typical Execution Time in struc- Description tion Words LABEL Jump on stored overflow (OV=”1”) 1*/2 Status word for: Instruction depends on: – – – – – – – – Instruction controls: – – – – – –...
Page 186 Instruction List B.41 Instructions for the Master Control Relay (MCR) MCR writes the value ”0” or leaves the memory contents unchanged. MCR=0 MCR is deactivated MCR=1 MCR is activated; ”T” instruction writes zeros to the corresponding address IDs; ”S”/”R” instructions do not change the memory contents. Length Address Typical Execution Time in...
Page 187 Execution Times of the SFCs and SFBs The CPU component of the IM 151/CPU provides you with different system functions and system function blocks for program scanning and diagnostics, for example. You can call these system functions/system function blocks in your user program using the number of the SFC.
Page 188 Execution Times of the SFCs and SFBs Name Description Execution Time in s FILL Presets a field +2.5 per byte CREATE_DB Creates a data block +5 per byte DEL_DB Deletes a data block TEST_DB Tests a data block SET_TINT Sets a time-of-day interrupt CAN_TINT Cancels a time-of-day interrupt ACT_TINT...
Page 189 Execution Times of the SFCs and SFBs Name Description Execution Time in s WR_REC Writes a module-specific data record 2200 (currently not used because there isn’t a module to which user records can be written) RD_REC Reads a module-specific data record (currently only reads diagnostic records 0 and 1) TIME_TICK Displays the system time with an accuracy of 10 ms...
Page 190 Execution Times of the SFCs and SFBs ET 200S Interface Module IM 151/CPU A5E00058783-01...
Page 191 Migration of the IM 151/CPU In this chapter, you will find out the most important differences of two selected CPUs in the S7-300 SIMATIC family. We will also show you how to rewrite programs you have written for the S7-300-CPUs for the IM 151/CPU. Chapter Overview In Section Contents...
Page 192 Migration of the IM 151/CPU Differences to Selected S7-300 CPUs The following table lists the most important programming differences between two selected CPUs of the S7-300 SIMATIC family and the IM 151/CPU. Table D-1 Differences to Selected S7-300 CPUs Features CPU 314 CPU 315-2 DP IM 151/CPU...
Page 193: Example: Fb With Unpacked Addresses
Migration of the IM 151/CPU Porting the User Program Introduction By porting we mean making available on a distributed basis a program that was previously used centrally on a master. Certain adjustments may be necessary to relocate an existing program partially or completely from a master to an intelligent slave.
Page 194: Example: Fb With Packed Addresses
Migration of the IM 151/CPU Porting with Packed Addresses If FBs with packed I/O addresses are copied to the IM 151/CPU, the packed addresses there can no longer be assigned to the I/Os of the I/O modules locally because the CPU of the IM 151/CPU cannot work with packed addresses. This requires rewiring of the corresponding FBs.
Page 195: Example: Rewiring Of The Signals
Migration of the IM 151/CPU 4. Click OK. This starts rewiring. After rewiring, you can decide in a dialog box whether you want to look at the rewiring information file. The file contains the list of old and new address IDs. The various blocks are also listed together with the number of rewirings carried out in the block.
Page 196 Migration of the IM 151/CPU ET 200S Interface Module IM 151/CPU A5E00058783-01...
Page 197 Glossary Accumulator The accumulators are registers in the CPU and are used as intermediate memory for loading, transfer, comparison, calculation and conversion operations. Address An address is the designation for a certain address ID or address area (e.g. input I 12.1; memory word MW 25; data block DB 3). Aggregate Current The sum of the currents of all the output channels of a digital output module.
Page 198 Glossary Compress The programming device online function “Compress” is used to align all valid blocks contiguously in the RAM of the CPU at the start of the user memory. This eliminates all gaps which arose when blocks were deleted or modified. Consistent Data Data that belongs together in terms of its content and should not separated is known as consistent data.
Page 199 Glossary Diagnostic Buffer The diagnostic buffer is a buffered memory area in the CPU in which diagnostic events are stored in the order of their occurrence. Diagnostic Interrupt Diagnostics-capable modules use diagnostic interrupts to report system errors which they have detected to the central CPU. In SIMATIC S7/M7: When an error is detected or disappears (e.
Page 200 ET 200S, ET 200M, ET 200B, ET 200C, ET 200U, ET 200X, ET 200L DP/AS-I Link S5-95U with a PROFIBUS-DP slave interface Other DP slaves from either Siemens or other vendors The distributed I/O systems are connected to the DP master via PROFIBUS-DP. DP master Master that complies with EN 50170, Volume 2, PROFIBUS, is referred to as a DP master.
Page 201 IM 308-C master interface module and the CPU 315-2 DP. DP slaves can be the distributed I/O devices ET 200S, ET 200B, ET 200C, ET 200M, ET 200X, ET 200U, ET 200L or DP slaves from Siemens or other vendors.
Page 202 Glossary Function A function (FC) in accordance with IEC 1131-3 is a code block without static data. A function allows parameters to be passed in the user program. Functions are therefore suitable for programming frequently repeated complex functions (e.g. calculations). Intelligent DP Slave The defining feature of an intelligent DP slave is that input/output data is not made available to the DP master by a real input/output of the DP slave directly,...
Page 203 Glossary Memory Marker Memory markers are part of the system memory of the CPU for storing interim results. They can be accessed in units of a bit, byte, word or doubleword. Micro Memory Card Memory module for SIMATIC systems. Can be used as a load memory and portable data carrier.
Page 204 Glossary Operating system of the CPU The operating system of the CPU organizes all the functions and processes of the CPU which are not associated with a special control task. Organization block Organization blocks (OBs) represent the interface between the operating system of the CPU and the user program.
Page 205 Glossary PROFIBUS Process Field Bus is a German process and field bus standard, defined in the IEC 61158/EN 50170, Volume 2, PROFIBUS standard. It defines the functional, electrical and mechanical features of a bit-serial field bus system. PROFIBUS is available with the protocols DP (the German abbreviation for distributed I/O), FMS (= field bus message specification), PA (= process automation) or TF (= technology (process-related) functions).
Page 206 Glossary Restart When a CPU is started up (e.g. by switching the mode selector from STOP to RUN or by switching the power on), the organization block OB 100 (complete restart) is executed before cyclic program scanning (OB 1) commences. On a complete restart, the process image input table is read in and the STEP 7 user program is processed starting with the first command in OB 1.
Page 207 Glossary Startup RESTART mode is activated during the transition from STOP mode to RUN mode. Can be triggered by the mode selector or after power on or an operator action on the programming device. In the case of the ET 200S a restart is carried out. STEP 7 Programming language for developing user programs for SIMATIC S7 PLCs.
Page 208 Glossary Timers (timer cells) Timers are part of the system memory of the CPU. The contents of the “timer cells” are updated automatically by the operating system asynchronously to the user program. STEP 7 instructions are used to define the exact function of the timer cells (e.g.
Page 209 Index Symbols AD, B-18 Address, Glossary-1 ), B-15 Address area )MCR, B-52 data consistency, 2-7 +, B-39 default setting, 2-10 +AR1, B-40 for user data transfer, 2-7 +AR2, B-40 of the expansion modules, 2-3 +D, B-38 Address assignment, for analog and digital +I, B-37 modules, 2-3 +R, B-39...
Page 210 Index Bus connector, 3-7 Data consistency, 2-7, 2-8 Bus faults, remedy, 3-9 Data exchange, direct, 3-10 Data interchange, sample program, 2-10 Data transfer principle behind, 2-1 with the DP master, 2-6 Cables, 3-7 DBs, 5-13 CAD, B-45 DDB (device database) file, 5-2 CALL, B-48 DEC, B-45 CAR, B-35...
Page 211 Index ET 200S Internode communication, see direct components, 1-5 communication, 3-10 manuals, 1-5 Interrupt, 4-14, Glossary-6 ET 200S manuals, guide to, 1-5 process, Glossary-9 Event identification, in the DP master/DP Interrupts, cycle extension, 7-5 slave, 4-12 INVD, B-47 Execution time, user program, 7-2 INVI, B-47 ITB, B-46 ITD, B-46...
Page 212 Index Manuals, guide to, 1-5 Manufacturer ID, CPU 31x-2 as DP slave, 4-19 O, B-13, B-16, B-21 Master, Glossary-6 O(, B-15 Master PROFIBUS address, 4-18 OB, Glossary-8 Master system, Glossary-6 start event, Glossary-10 MCR(, B-52 OB 1, 5-14 MCRA, B-52 OB 100, 5-14 MCRD, B-52 OB 122, 4-12, 5-15...
Page 213 Index Parameter ranges, STEP 7 instructions, B-2 RLDA, B-44 Parameters, BM 147/CPU, 5-16 RND, B-46 RND+, B-46 connection to ET 200S, 3-4 RND–, B-46 prerequisites, 3-2 RRD, B-44 PG, Glossary-9 RRDA, B-44 connection to ET 200X, 3-4 Rules, for addressing, 2-9 PLC, Glossary-9 Pointers, calculating, B-6 LED, 5-5...
Page 214 Index Station failure, OB 86, 5-15 Token, Glossary-12 Station status 1 to 3, 4-16 Transfer instruction, 2-8 Status word, B-4 Transmission rate, Glossary-12 STEP 7, Glossary-11 Troubleshooting, 4-1 addressing interface, 2-9 TRUNC, B-46 configuring the IM 151/CPU, 4-2 settings, 3-9 STOP LED, 5-5 UC, B-48...
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Siemens SIMATIC IM 151/CPU Manual

1 Product Overview

2 Addressing

3 ET 200S in the PROFIBUS Network

4 Commissioning and Diagnostics

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