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Manuals and User Guides for Hitachi SH7750R. We have
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Hitachi SH7750R manual available for free PDF download: Hardware Manual
Hitachi SH7750R Hardware Manual (1037 pages)
SH7750 Series SuperH RISC engine
Brand:
Hitachi
| Category:
Engine
| Size: 5.51 MB
Table of Contents
Table of Contents
21
Table of Contents
43
Overview
51
SH7750 Series (SH7750, SH7750S, SH7750R) Features
51
Table 1.1 SH7750 Series Features
53
Block Diagram
59
Figure 1.1 Block Diagram of SH7750 Series Functions
59
Figure 1.2 Pin Arrangement (256-Pin BGA)
60
Pin Arrangement
60
Figure 1.3 Pin Arrangement (208-Pin QFP)
61
Figure 1.4 Pin Arrangement (264-Pin CSP)
62
Pin Functions
63
Pin Functions (256-Pin BGA)
63
Table 1.2 Pin Functions
63
Pin Functions (208-Pin QFP)
73
Table 1.3 Pin Functions
73
Pin Functions (264-Pin CSP)
81
Table 1.4 Pin Functions
81
Data Formats
91
Programming Model
91
Register Configuration
92
Privileged Mode and Banks
92
Table 2.1 Initial Register Values
93
Appendix H Power-On and Power-Off Procedures
94
Appendix I Product Code Lineup
94
Figure 2.2 CPU Register Configuration in each Processor Mode
94
General Registers
95
Figure 2.3 General Registers
96
Floating-Point Registers
97
Figure 2.4 Floating-Point Registers
98
Control Registers
99
System Registers
100
Index
94
Memory-Mapped Registers
102
Data Format in Registers
103
Data Formats in Memory
103
Figure 2.1 Data Formats
103
Figure 2.5 Data Formats in Memory
103
Processor States
104
Figure 2.6 Processor State Transitions
105
Processor Modes
105
Memory Management Unit (MMU)
107
Overview
107
Features
107
Role of the MMU
107
Figure 3.1 Role of the MMU
109
Register Configuration
110
Caution
110
Table 3.1 MMU Registers
110
Figure 3.2 MMU-Related Registers
111
Register Descriptions
111
Address Space
114
Physical Address Space
114
Figure 3.3 Physical Address Space (MMUCR.AT = 0)
115
Figure 3.4 P4 Area
116
External Memory Space
117
Figure 3.5 External Memory Space
117
Virtual Address Space
118
Figure 3.6 Virtual Address Space (MMUCR.AT = 1)
118
On-Chip RAM Space
119
Address Translation
119
Single Virtual Memory Mode and Multiple Virtual Memory Mode
120
Address Space Identifier (ASID)
120
TLB Functions
121
Unified TLB (UTLB) Configuration
121
Figure 3.7 UTLB Configuration
121
Figure 3.8 Relationship between Page Size and Address Format
122
Instruction TLB (ITLB) Configuration
125
Address Translation Method
125
Figure 3.9 ITLB Configuration
125
Figure 3.10 Flowchart of Memory Access Using UTLB
126
Figure 3.11 Flowchart of Memory Access Using ITLB
127
MMU Functions
128
MMU Hardware Management
128
MMU Software Management
128
MMU Instruction (LDTLB)
128
Hardware ITLB Miss Handling
129
Figure 3.12 Operation of LDTLB Instruction
129
Avoiding Synonym Problems
130
MMU Exceptions
131
Instruction TLB Multiple Hit Exception
131
Instruction TLB Miss Exception
132
Instruction TLB Protection Violation Exception
133
Data TLB Multiple Hit Exception
134
Data TLB Miss Exception
134
Data TLB Protection Violation Exception
135
Initial Page Write Exception
136
Memory-Mapped TLB Configuration
137
ITLB Address Array
138
Figure 3.13 Memory-Mapped ITLB Address Array
138
ITLB Data Array 1
139
Figure 3.14 Memory-Mapped ITLB Data Array 1
139
ITLB Data Array 2
140
UTLB Address Array
140
Figure 3.15 Memory-Mapped ITLB Data Array 2
140
Figure 3.16 Memory-Mapped UTLB Address Array
141
UTLB Data Array 1
142
Figure 3.17 Memory-Mapped UTLB Data Array 1
142
UTLB Data Array 2
143
Figure 3.18 Memory-Mapped UTLB Data Array 2
143
Caches
145
Overview
145
Features
145
Table 4.1 Cache Features (SH7750, SH7750S)
145
Table 4.2 Cache Features (SH7750R)
145
Register Configuration
146
Table 4.3 Features of Store Queues
146
Table 4.4 Cache Control Registers
146
Figure 4.1 Cache and Store Queue Control Registers
147
Register Descriptions
147
Operand Cache (OC)
149
Configuration
149
Figure 4.2 Configuration of Operand Cache(SH7750, SH7750S)
150
Figure 4.3 Configuration of Operand Cache (SH7750R)
151
Read Operation
153
Write Operation
154
Write-Back Buffer
155
Write-Through Buffer
155
Figure 4.4 Configuration of Write-Back Buffer
155
Figure 4.5 Configuration of Write-Through Buffer
155
RAM Mode
156
OC Index Mode
157
Coherency between Cache and External Memory
157
Instruction Cache (IC)
158
Configuration
158
Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S)
159
Figure 4.7 Configuration of Instruction Cache (SH7750R)
160
Read Operation
161
IC Index Mode
161
Memory-Mapped Cache Configuration (SH7750, SH7750S)
162
IC Address Array
162
IC Data Array
163
Figure 4.8 Memory-Mapped IC Address Array
163
OC Address Array
164
Figure 4.9 Memory-Mapped IC Data Array
164
OC Data Array
165
Figure 4.10 Memory-Mapped OC Address Array
165
Figure 4.11 Memory-Mapped OC Data Array
166
IC Address Array
167
IC Data Array
168
Figure 4.12 Memory-Mapped IC Address Array
168
OC Address Array
169
Figure 4.13 Memory-Mapped IC Data Array
169
OC Data Array
170
Figure 4.14 Memory-Mapped OC Address Array
170
Summary of the Memory-Mapping of the OC
171
Figure 4.15 Memory-Mapped OC Data Array
171
Memory-Mapped Cache Configuration (SH7750R)
166
Store Queues
172
SQ Configuration
172
SQ Writes
172
Transfer to External Memory
172
Figure 4.16 Store Queue Configuration
172
SQ Protection
174
Reading the Sqs (SH7750R Only)
174
SQ Usage Notes
175
Exceptions
177
Overview
177
Features
177
Register Configuration
177
Table 5.1 Exception-Related Registers
177
Figure 5.1 Register Bit Configurations
178
Register Descriptions
178
Exception Handling Functions
179
Exception Handling Flow
179
Exception Handling Vector Addresses
179
Exception Types and Priorities
180
Figure 21.3 H-UDI Reset
180
Table 5.2 Exceptions
180
Exception Flow
182
Exception Source Acceptance
183
Figure 5.2 Instruction Execution and Exception Handling
183
Figure 5.3 Example of General Exception Acceptance Order
184
Exception Requests and BL Bit
185
Return from Exception Handling
185
Description of Exceptions
185
Resets
186
Table 5.3 Types of Reset
187
General Exceptions
191
Interrupts
205
Priority Order with Multiple Exceptions
208
Usage Notes
209
Restrictions
210
Data Formats
211
Floating-Point Format
211
Figure 6.1 Format of Single-Precision Floating-Point Number
211
Figure 6.2 Format of Double-Precision Floating-Point Number
212
Table 6.1 Floating-Point Number Formats and Parameters
212
Non-Numbers (Nan)
213
Table 6.2 Floating-Point Ranges
213
Denormalized Numbers
214
Figure 6.3 Single-Precision Nan Bit Pattern
214
Floating-Point Unit
211
Overview
211
Registers
215
Floating-Point Registers
215
Figure 6.4 Floating-Point Registers
216
Floating-Point Status/Control Register (FPSCR)
217
Floating-Point Communication Register (FPUL)
218
Rounding
218
Floating-Point Exceptions
219
Graphics Support Functions
220
Geometric Operation Instructions
220
Pair Single-Precision Data Transfer
222
Execution Environment
223
Instruction Set
223
Addressing Modes
225
Table 7.1 Addressing Modes and Effective Addresses
228
Instruction Set
229
Table 7.2 Notation Used in Instruction List
229
Table 7.3 Fixed-Point Transfer Instructions
230
Table 7.4 Arithmetic Operation Instructions
233
Table 7.5 Logic Operation Instructions
234
Table 7.6 Shift Instructions
235
Table 7.7 Branch Instructions
236
Table 7.8 System Control Instructions
237
Table 7.9 Floating-Point Single-Precision Instructions
239
Table 7.10 Floating-Point Double-Precision Instructions
240
Table 7.11 Floating-Point Control Instructions
240
Table 7.12 Floating-Point Graphics Acceleration Instructions
241
Pipelines
243
Pipelining
243
Figure 8.1 Basic Pipelines
244
Figure 8.2 Instruction Execution Patterns
249
Parallel-Executability
250
Table 8.1 Instruction Groups
250
Execution Cycles and Pipeline Stalling
254
Table 8.2 Parallel-Executability
254
Figure 8.3 Examples of Pipelined Execution
259
Table 8.3 Execution Cycles
261
Overview
271
Types of Power-Down Modes
271
Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes
272
Register Configuration
273
Pin Configuration
273
Table 9.2 Power-Down Mode Registers
273
Table 9.3 Power-Down Mode Pins
273
Power-Down Modes
271
Register Descriptions
274
Standby Control Register (STBCR)
274
Peripheral Module Pin High Impedance Control
276
Peripheral Module Pin Pull-Up Control
276
Standby Control Register 2 (STBCR2)
277
Clock-Stop Register 00 (CLKSTP00) (SH7750R Only)
278
Clock-Stop Clear Register 00 (CLKSTPCLR00) (SH7750R Only)
279
Deep Sleep Mode
280
Transition to Deep Sleep Mode
280
Exit from Deep Sleep Mode
281
Sleep Mode
280
Transition to Sleep Mode
280
Exit from Sleep Mode
280
Standby Mode
281
Transition to Standby Mode
281
Table 9.4 State of Registers in Standby Mode
281
Exit from Standby Mode
282
Clock Pause Function
282
Module Standby Function
283
Transition to Module Standby Function
283
Exit from Module Standby Function
284
Hardware Standby Mode (SH7750S, SH7750R Only)
285
Transition to Hardware Standby Mode
285
Exit from Hardware Standby Mode
285
Usage Notes
285
STATUS Pin Change Timing
286
In Reset
287
Figure 9.1 STATUS Output in Power-On Reset
287
Figure 9.2 STATUS Output in Manual Reset
287
In Exit from Standby Mode
288
Figure 9.3 STATUS Output in Standby → Interrupt Sequence
288
Figure 9.4 STATUS Output in Standby → Power-On Reset Sequence
288
Figure 9.5 STATUS Output in Standby → Manual Reset Sequence
289
In Exit from Sleep Mode
290
Figure 9.6 STATUS Output in Sleep → Interrupt Sequence
290
Figure 9.7 STATUS Output in Sleep → Power-On Reset Sequence
290
Figure 9.8 STATUS Output in Sleep → Manual Reset Sequence
291
In Exit from Deep Sleep Mode
292
Figure 9.9 STATUS Output in Deep Sleep → Interrupt Sequence
292
Figure 9.10 STATUS Output in Deep Sleep → Power-On Reset Sequence
292
Figure 9.11 STATUS Output in Deep Sleep → Manual Reset Sequence
293
Hardware Standby Mode Timing (SH7750S, SH7750R Only)
294
Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation)
294
Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation)
295
Figure 9.14 Timing When Power Other than VDD-RTC Is off
296
Figure 9.15 Timing When VDD-RTC Power Is off → on
296
Overview
297
Features
297
Section 10 Clock Oscillation Circuits
297
Overview of CPG
299
Block Diagram of CPG
299
Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S)
299
Figure 10.1 (2) Block Diagram of CPG (SH7750R)
300
CPG Pin Configuration
302
CPG Register Configuration
302
Table 10.1 CPG Pins
302
Table 10.2 CPG Register
302
Clock Operating Modes
303
Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S)
303
Table 10.3 (2) Clock Operating Modes (SH7750R)
303
CPG Register Description
304
Frequency Control Register (FRQCR)
304
Table 10.4 FRQCR Settings and Internal Clock Frequencies
304
Changing the Frequency
307
Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off)
307
Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On)
307
Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On)
308
Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off)
308
Changing CPU or Peripheral Module Clock Division Ratio
308
Output Clock Control
308
Overview of Watchdog Timer
309
Block Diagram
309
Figure 10.2 Block Diagram of WDT
309
Register Configuration
310
WDT Register Descriptions
310
Watchdog Timer Counter (WTCNT)
310
Table 10.5 WDT Registers
310
Watchdog Timer Control/Status Register (WTCSR)
311
Notes on Register Access
313
Using the WDT
313
Standby Clearing Procedure
313
Figure 10.3 Writing to WTCNT and WTCSR
313
Frequency Changing Procedure
314
Using Watchdog Timer Mode
314
Using Interval Timer Mode
315
Figure 10.4 Points for Attention When Using Crystal Resonator
315
Notes on Board Design
315
Figure 10.5 Points for Attention When Using PLL Oscillator Circuit
316
Overview
317
Features
317
Block Diagram
318
Figure 11.1 Block Diagram of RTC
318
Pin Configuration
319
Register Configuration
319
Table 11.1 RTC Pins
319
Table 11.2 RTC Registers
319
Section 11 Realtime Clock (RTC)
317
Register Descriptions
321
64 Hz Counter (R64CNT)
321
Second Counter (RSECCNT)
321
Minute Counter (RMINCNT)
322
Hour Counter (RHRCNT)
322
Day-Of-Week Counter (RWKCNT)
323
Day Counter (RDAYCNT)
324
Month Counter (RMONCNT)
324
Year Counter (RYRCNT)
325
Second Alarm Register (RSECAR)
326
Minute Alarm Register (RMINAR)
326
Hour Alarm Register (RHRAR)
327
Day-Of-Week Alarm Register (RWKAR)
327
Day Alarm Register (RDAYAR)
328
Month Alarm Register (RMONAR)
329
RTC Control Register 1 (RCR1)
329
RTC Control Register 2 (RCR2)
331
RTC Control Register 3 (RCR3) and Year-Alarm Register (RYRAR)
333
(SH7750R Only)
333
Operation
335
Time Setting Procedures
335
Figure 11.2 Examples of Time Setting Procedures
335
Time Reading Procedures
336
Figure 11.3 Examples of Time Reading Procedures
337
Alarm Function
338
Figure 11.4 Example of Use of Alarm Function
338
Interrupts
339
Usage Notes
339
Register Initialization
339
Carry Flag and Interrupt Flag in Standby Mode
339
Crystal Oscillator Circuit
339
Table 11.3 Crystal Oscillator Circuit Constants (Recommended Values)
339
Figure 11.5 Example of Crystal Oscillator Circuit Connection
340
Overview
341
Features
341
Block Diagram
342
Pin Configuration
342
Figure 12.1 Block Diagram of TMU
342
Table 12.1 TMU Pins
342
Register Configuration
343
Table 12.2 TMU Registers
343
Section 12 Timer Unit (TMU)
341
Register Descriptions
345
Timer Output Control Register (TOCR)
345
Timer Start Register (TSTR)
346
Timer Start Register 2 (TSTR2) (SH7750R Only)
347
Timer Constant Registers (TCOR)
348
Timer Counters (TCNT)
348
Timer Control Registers (TCR)
349
Input Capture Register (TCPR2)
353
Operation
354
Counter Operation
354
Figure 12.2 Example of Count Operation Setting Procedure
355
Figure 12.3 TCNT Auto-Reload Operation
355
Figure 12.4 Count Timing When Operating on Internal Clock
356
Figure 12.5 Count Timing When Operating on External Clock
356
Input Capture Function
357
Figure 12.6 Count Timing When Operating on On-Chip RTC Output Clock
357
Figure 12.7 Operation Timing When Using Input Capture Function
358
Interrupts
358
Usage Notes
359
Register Writes
359
TCNT Register Reads
359
Resetting the RTC Frequency Divider
359
External Clock Frequency
359
Table 12.3 TMU Interrupt Sources
359
Overview
361
Features
361
Block Diagram
363
Figure 13.1 Block Diagram of BSC
363
Pin Configuration
364
Table 13.1 BSC Pins
364
Register Configuration
368
Table 13.2 BSC Registers
368
Overview of Areas
369
Figure 13.2 Correspondence between Virtual Address Space and External Memory Space
369
Table 13.3 External Memory Space Map
370
Figure 13.3 External Memory Space Allocation
371
PCMCIA Support
372
Table 13.4 PCMCIA Interface Features
372
Table 13.5 PCMCIA Support Interfaces
373
Section 13 Bus State Controller (BSC)
361
Register Descriptions
376
Bus Control Register 1 (BCR1)
376
Bus Control Register 2 (BCR2)
385
Bus Control Register 3 (BCR3) (SH7750R Only)
387
Bus Control Register 4 (BCR4) (SH7750R Only)
388
Figure 13.4 Example of RDY Sampling Timing at Which BCR4 Is Set (Two Wait Cycles Are Inserted by WCR2)
388
Wait Control Register 1 (WCR1)
390
Wait Control Register 2 (WCR2)
393
Table 13.6 MPX Interface Is Selected (Areas 0 to 6)
400
Wait Control Register 3 (WCR3)
401
Memory Control Register (MCR)
402
PCMCIA Control Register (PCR)
409
Synchronous DRAM Mode Register (SDMR)
412
Refresh Timer Control/Status Register (RTCSR)
414
Refresh Timer Counter (RTCNT)
417
Refresh Time Constant Register (RTCOR)
418
Refresh Count Register (RFCR)
419
13.2.15 Notes on Accessing Refresh Control Registers
419
Operation
420
Endian/Access Size and Data Alignment
420
Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR
420
Table 13.7 (1) 64-Bit External Device/Big-Endian Access and Data Alignment
422
Table 13.7 (2) 64-Bit External Device/Big-Endian Access and Data Alignment
423
Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment
424
Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment
425
Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment
426
Table 13.11 (1) 64-Bit External Device/Little-Endian Access and Data Alignment
427
Table 13.11 (2) 64-Bit External Device/Little-Endian Access and Data Alignment
428
Table 13.12 32-Bit External Device/Little-Endian Access and Data Alignment
429
Table 13.13 16-Bit External Device/Little-Endian Access and Data Alignment
430
Table 13.14 8-Bit External Device/Little-Endian Access and Data Alignment
431
Areas
432
SRAM Interface
437
Figure 13.6 Basic Timing of SRAM Interface
438
Figure 13.7 Example of 64-Bit Data Width SRAM Connection
439
Figure 13.8 Example of 32-Bit Data Width SRAM Connection
440
Figure 13.9 Example of 16-Bit Data Width SRAM Connection
441
Figure 13.10 Example of 8-Bit Data Width SRAM Connection
442
Figure 13.11 SRAM Interface Wait Timing (Software Wait Only)
443
Figure 13.12 SRAM Interface Wait State Timing (Wait State Insertion by RDY Signal)
444
DRAM Interface
445
Figure 13.13 SRAM Interface Read-Strobe Negate Timing (Ans = 1, Anw = 4, Anh = 2) 395 Figure 13.14 Example of DRAM Connection (64-Bit Data Width, Area 3)
446
Figure 13.15 Example of DRAM Connection (32-Bit Data Width, Area 3)
447
Figure 13.16 Example of DRAM Connection (16-Bit Data Width, Areas 2 and 3)
448
Table 13.15 Relationship between AMXEXT and AMX2-0 Bits and
449
Figure 13.17 Basic DRAM Access Timing
450
Figure 13.18 DRAM Wait State Timing
451
Figure 13.19 DRAM Burst Access Timing
452
Figure 13.20 DRAM Bus Cycle (EDO Mode, RCD = 0, Anw = 0, TPC = 1)
453
Figure 13.21 Burst Access Timing in DRAM EDO Mode
454
Figure 13.22 (1) DRAM Burst Bus Cycle, RAS down Mode Start (Fast Page Mode, RCD = 0, Anw = 0)
455
Figure 13.22 (2) DRAM Burst Bus Cycle, RAS down Mode Continuation (Fast Page Mode, RCD = 0, Anw = 0)
456
Figure 13.22 (3) DRAM Burst Bus Cycle, RAS down Mode Start (EDO Mode, RCD = 0, Anw = 0)
457
Figure 13.22 (4) DRAM Burst Bus Cycle, RAS down Mode Continuation (EDO Mode, RCD = 0, Anw = 0)
458
Figure 13.23 CAS-Before-RAS Refresh Operation
459
Figure 13.24 DRAM CAS-Before-RAS Refresh Cycle Timing (tras = 0, TRC = 1)
460
Figure 13.25 DRAM Self-Refresh Cycle Timing
462
Synchronous DRAM Interface
463
Table 13.16 Example of Correspondence between SH7750 Series and Synchronous DRAM
466
Address Pins (64-Bit Bus Width, AMX2-AMX0 = 011, AMXEXT = 0)
466
Table 13.17 Cycles for Which Pipeline Access Is Possible
481
Burst ROM Interface
491
PCMCIA Interface
494
Table 13.18 Relationship between Address and CE When Using PCMCIA Interface
496
MPX Interface
505
Byte Control SRAM Interface
523
13.3.10 Waits between Access Cycles
528
13.3.11 Bus Arbitration
530
13.3.12 Master Mode
533
13.3.13 Slave Mode
534
13.3.14 Partial-Sharing Master Mode
535
13.3.15 Cooperation between Master and Slave
536
13.3.16 Notes on Usage
537
Overview
539
Features
539
Block Diagram (SH7750, SH7750S)
542
Pin Configuration (SH7750, SH7750S)
543
Table 14.1 DMAC Pins
543
Register Configuration (SH7750, SH7750S)
544
Table 14.2 DMAC Pins in DDT Mode
544
Table 14.3 DMAC Registers
544
Section 14 Direct Memory Access Controller (DMAC)
539
Register Descriptions (SH7750, SH7750S)
546
DMA Source Address Registers 0-3 (SAR0-SAR3)
546
DMA Destination Address Registers 0-3 (DAR0-DAR3)
547
DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3)
548
DMA Channel Control Registers 0-3 (CHCR0-CHCR3)
549
DMA Operation Register (DMAOR)
557
Operation
560
DMA Transfer Procedure
560
DMA Transfer Requests
562
Table 14.4 Selecting External Request Mode with RS Bits
563
Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits
564
Channel Priorities
565
Types of DMA Transfer
568
Table 14.6 Supported DMA Transfers
568
Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode
574
Table 14.8 External Request Transfer Sources and Destinations in Normal Mode
575
Table 14.9 External Request Transfer Sources and Destinations in DDT Mode
576
Number of Bus Cycle States and DREQ Pin Sampling Timing
577
Ending DMA Transfer
591
Examples of Use
594
Examples of Transfer between External Memory and an External Device with DACK
594
Table 14.10 Conditions for Transfer between External Memory and an External Device with DACK, and Corresponding Register Settings
594
On-Demand Data Transfer Mode (DDT Mode)
595
Operation
595
Pins in DDT Mode
597
Transfer Request Acceptance on each Channel
600
Notes on Use of DDT Module
621
Configuration of the DMAC (SH7750R)
624
Block Diagram of the DMAC
624
Pin Configuration (SH7750R)
625
Table 14.11 DMAC Pins
625
Register Configuration (SH7750R)
626
Table 14.12 DMAC Pins in DDT Mode
626
Table 14.13 Register Configuration
627
Register Descriptions (SH7750R)
629
DMA Source Address Registers 0-7 (SAR0-SAR7)
629
DMA Destination Address Registers 0-7 (DAR0-DAR7)
629
DMA Transfer Count Registers 0-7 (DMATCR0-DMATCR7)
630
DMA Channel Control Registers 0-7 (CHCR0-CHCR7)
630
DMA Operation Register (DMAOR)
633
Table 14.14 Channel Selection by DTR Format (DMAOR.DBL = 1)
634
Operation (SH7750R)
636
Channel Specification for a Normal DMA Transfer
636
Channel Specification for DDT-Mode DMA Transfer
636
Transfer Channel Notification in DDT Mode
636
Clearing Request Queues by DTR Format
637
Table 14.15 Notification of Transfer Channel in Eight-Channel DDT Mode
637
Table 14.16 Function of BAVL
637
Interrupt-Request Codes
638
Table 14.17 DTR Format for Clearing Request Queues
638
Table 14.18 DMAC Interrupt-Request Codes
639
Usage Notes
641
Overview
643
Features
643
Block Diagram
645
Pin Configuration
646
Register Configuration
646
Table 15.1 SCI Pins
646
Table 15.2 SCI Registers
646
Section 15 Serial Communication Interface (SCI)
643
Register Descriptions
647
Receive Shift Register (SCRSR1)
647
Receive Data Register (SCRDR1)
647
Transmit Shift Register (SCTSR1)
648
Transmit Data Register (SCTDR1)
648
Serial Mode Register (SCSMR1)
649
Serial Control Register (SCSCR1)
651
Serial Status Register (SCSSR1)
655
Serial Port Register (SCSPTR1)
659
Bit Rate Register (SCBRR1)
663
Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode
665
Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode
668
Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode)
669
Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
670
Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode)
670
Operation
671
Overview
671
Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection
672
Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection
672
Operation in Asynchronous Mode
673
Table 15.10 Serial Transfer Formats (Asynchronous Mode)
674
Table 15.11 Receive Error Conditions
682
Multiprocessor Communication Function
684
Operation in Synchronous Mode
692
SCI Interrupt Sources and DMAC
701
Table 15.12 SCI Interrupt Sources
701
Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data
702
Usage Notes
702
Overview
707
Features
707
Block Diagram
709
Pin Configuration
710
Table 16.1 SCIF Pins
710
Register Configuration
711
Section 16 Serial Communication Interface with FIFO (SCIF)
707
Register Descriptions
711
Receive Shift Register (SCRSR2)
711
Table 16.2 SCIF Registers
711
Receive FIFO Data Register (SCFRDR2)
712
Transmit Shift Register (SCTSR2)
712
Transmit FIFO Data Register (SCFTDR2)
713
Serial Mode Register (SCSMR2)
713
Serial Control Register (SCSCR2)
715
Serial Status Register (SCFSR2)
718
Bit Rate Register (SCBRR2)
724
FIFO Control Register (SCFCR2)
725
FIFO Data Count Register (SCFDR2)
728
Serial Port Register (SCSPTR2)
729
Line Status Register (SCLSR2)
734
Operation
735
Overview
735
Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection
735
Serial Operation
736
Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection
736
Table 16.5 Serial Transmit/Receive Formats
737
SCIF Interrupt Sources and the DMAC
747
Table 16.6 SCIF Interrupt Sources
747
Usage Notes
748
Overview
753
Features
753
Block Diagram
754
Pin Configuration
755
Register Configuration
755
Table 17.1 Smart Card Interface Pins
755
Table 17.2 Smart Card Interface Registers
755
Section 17 Smart Card Interface
753
Register Descriptions
756
Smart Card Mode Register (SCSCMR1)
756
Serial Mode Register (SCSMR1)
757
Serial Control Register (SCSCR1)
758
Serial Status Register (SCSSR1)
759
Operation
760
Overview
760
Pin Connections
761
Data Format
762
Register Settings
763
Table 17.3 Smart Card Interface Register Settings
763
Clock
765
Table 17.4 Values of N and Corresponding CKS1 and CKS0 Settings
765
Table 17.5 Examples of Bit Rate B (Bits/S) for Various SCBRR1 Settings (When N = 0)
766
Table 17.6 Examples of SCBRR1 Settings for Bit Rate B (Bits/S) (When N = 0)
766
Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
766
Table 17.8 Register Settings and SCK Pin State
767
Data Transmit/Receive Operations
768
Table 17.9 Smart Card Mode Operating States and Interrupt Sources
774
Usage Notes
775
Overview
781
Features
781
Block Diagrams
782
Pin Configuration
789
Table 18.1 20-Bit General-Purpose I/O Port Pins
789
Table 18.2 SCI I/O Port Pins
790
Table 18.3 SCIF I/O Port Pins
790
Register Configuration
791
Table 18.4 I/O Port Registers
791
Section 18 I/O Ports
781
Register Descriptions
792
Port Control Register a (PCTRA)
792
Port Data Register a (PDTRA)
793
Port Control Register B (PCTRB)
794
Port Data Register B (PDTRB)
795
GPIO Interrupt Control Register (GPIOIC)
795
Serial Port Register (SCSPTR1)
796
Serial Port Register (SCSPTR2)
798
Overview
801
Features
801
Block Diagram
801
Pin Configuration
803
Register Configuration
803
Table 19.1 INTC Pins
803
Table 19.2 INTC Registers
803
Section 19 Interrupt Controller (INTC)
801
Interrupt Sources
804
NMI Interrupt
804
IRL Interrupts
805
Table 19.3 IRL3-IRL0 Pins and Interrupt Levels
806
On-Chip Peripheral Module Interrupts
807
Table 19.4 SH7750 IRL3-IRL0 Pins and Interrupt Levels (When IRLM = 1)
807
Interrupt Exception Handling and Priority
808
Table 19.5 Interrupt Exception Handling Sources and Priority Order
809
Register Descriptions
811
Interrupt Priority Registers a to D (IPRA-IPRD)
811
Interrupt Control Register (ICR)
812
Table 19.6 Interrupt Request Sources and IPRA-IPRD Registers
812
Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only)
814
Interrupt Source Register 00 (INTREQ00) (SH7750R Only)
815
Table 19.7 Interrupt Request Sources and the Bits of the INTPRI00 Register
815
Interrupt Mask Register 00 (INTMSK00) (SH7750R Only)
816
Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only)
817
Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only)
817
Table 19.8 Bit Assignments
817
INTC Operation
818
Interrupt Operation Sequence
818
Multiple Interrupts
820
Interrupt Masking with MAI Bit
820
Interrupt Response Time
821
Table 19.9 Interrupt Response Time
821
Overview
823
Features
823
Block Diagram
824
Table 20.1 UBC Registers
825
Section 20 User Break Controller (UBC)
823
Register Descriptions
826
Access to UBC Control Registers
826
Break Address Register a (BARA)
827
Break ASID Register a (BASRA)
828
Break Address Mask Register a (BAMRA)
828
Break Bus Cycle Register a (BBRA)
829
Break Address Register B (BARB)
831
Break ASID Register B (BASRB)
831
Break Address Mask Register B (BAMRB)
831
Break Data Register B (BDRB)
831
Break Data Mask Register B (BDMRB)
832
Break Bus Cycle Register B (BBRB)
833
Break Control Register (BRCR)
833
Operation
835
Explanation of Terms Relating to Accesses
835
Explanation of Terms Relating to Instruction Intervals
836
User Break Operation Sequence
837
Instruction Access Cycle Break
838
Operand Access Cycle Break
839
Condition Match Flag Setting
840
Program Counter (PC) Value Saved
840
Contiguous a and B Settings for Sequential Conditions
841
Usage Notes
842
User Break Debug Support Function
843
Examples of Use
845
User Break Controller Stop Function
847
Transition to User Break Controller Stopped State
847
Cancelling the User Break Controller Stopped State
847
Examples of Stopping and Restarting the User Break Controller
848
Overview
849
Features
849
Block Diagram
849
Pin Configuration
851
Table 21.1 H-UDI Pins
851
Register Configuration
852
Table 21.2 H-UDI Registers
852
Section 21 Hitachi User Debug Interface (H-UDI)
849
Register Descriptions
853
Instruction Register (SDIR)
853
Data Register (SDDR)
855
Bypass Register (SDBPR)
855
Interrupt Source Register (SDINT) (SH7750R Only)
856
Boundary Scan Register (SDBSR) (SH7750R Only)
856
Table 21.3 Configuration of the Boundary Scan Register (1)
857
Table 21.3 Configuration of the Boundary Scan Register (2)
858
Table 21.3 Configuration of the Boundary Scan Register (3)
859
Operation
860
TAP Control
860
H-UDI Reset
861
H-UDI Interrupt
861
Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) (SH7750R Only)
862
Usage Notes
862
Absolute Maximum Ratings
863
Section 22 Electrical Characteristics
863
Table 22.1 Absolute Maximum Ratings
863
DC Characteristics
864
Table 22.2 DC Characteristics (HD6417750RBP240)
864
Table 22.3 DC Characteristics (HD6417750RF240)
866
Table 22.4 DC Characteristics (HD6417750RBP200)
868
Table 22.5 DC Characteristics (HD6417750RF200)
870
Table 22.6 DC Characteristics (HD6417750SBP200)
872
Table 22.7 DC Characteristics (HD6417750SF200)
874
Table 22.8 DC Characteristics (HD6417750BP200M)
876
Table 22.9 DC Characteristics (HD6417750SF167)
878
Table 22.10 DC Characteristics (HD6417750SF167I)
880
Table 22.11 DC Characteristics (HD6417750F167)
882
Table 22.12 DC Characteristics (HD6417750F167I)
884
Table 22.13 DC Characteristics (HD6417750SVF133)
886
Table 22.14 DC Characteristics (HD6417750SVBT133)
888
Table 22.15 DC Characteristics (HD6417750VF128)
890
Table 22.16 Permissible Output Currents
891
AC Characteristics
892
Table 22.17 Clock Timing (HD6417750RBP240)
892
Table 22.18 Clock Timing (HD6417750RF240)
892
Table 22.19 Clock Timing (HD6417750BP200M, HD6417750SBP200, HD6417750RBP200)
892
Table 22.20 Clock Timing (HD6417750RF200)
892
Table 22.21 Clock Timing (HD6417750SF200)
892
Table 22.22 Clock Timing (HD6417750F167, HD6417750F167I, HD6417750SF167, HD6417750SF167I)
893
Table 22.23 Clock Timing (HD6417750SVF133, HD6417750SVBT133)
893
Table 22.24 Clock Timing (HD6417750VF128)
893
Clock and Control Signal Timing
894
Table 22.25 Clock and Control Signal Timing (HD6417750RBP240)
894
Table 22.26 Clock and Control Signal Timing (HD6417750RF240)
896
Table 22.27 Clock and Control Signal Timing (HD6417750RBP200)
898
Table 22.28 Clock and Control Signal Timing (HD6417750RF200)
900
Table 22.29 Clock and Control Signal Timing
902
Table 22.30 Clock and Control Signal Timing (HD6417750SF200)
904
Table 22.31 Clock and Control Signal Timing
906
Hd6417750Sf167, Hd6417750Sf167I)
906
Hd6417750Svbt133: V
908
Table 22.33 Clock and Control Signal Timing (HD6417750VF128)
910
Figure 22.1 EXTAL Clock Input Timing
912
Figure 22.2(1) CKIO Clock Output Timing
912
Figure 22.2(2) CKIO Clock Output Timing
912
Figure 22.3 Power-On Oscillation Settling Time
913
Figure 22.4 Standby Return Oscillation Settling Time (Return by RESET)
913
Figure 22.5 Power-On Oscillation Settling Time
914
Figure 22.6 Standby Return Oscillation Settling Time (Return by RESET)
914
Figure 22.7 Standby Return Oscillation Settling Time (Return by NMI)
915
Figure 22.8 Standby Return Oscillation Settling Time (Return by IRL3-IRL0)
915
Figure 22.10 PLL Synchronization Settling Time in Case of IRL Interrupt
916
Figure 22.9 PLL Synchronization Settling Time in Case of RESET or NMI Interrupt
916
Figure 22.11 Manual Reset Input Timing
917
Figure 22.12 Mode Input Timing
917
Control Signal Timing
918
Table 22.34 Control Signal Timing (1)
918
Table 22.34 Control Signal Timing (2)
919
Figure 22.13 Control Signal Timing
920
Figure 22.14 Pin Drive Timing for Standby Mode
920
Bus Timing
921
Table 22.35 Bus Timing (1)
921
Table 22.35 Bus Timing (2)
923
Table 22.35 Bus Timing (3)
925
Figure 22.15 SRAM Bus Cycle: Basic Bus Cycle (no Wait)
927
Figure 22.16 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait)
928
Insertion, Ans = 1, Anh = 1)
930
Figure 22.19 Burst ROM Bus Cycle (no Wait)
931
Figure 22.20 Burst ROM Bus Cycle (1St Data: One Internal Wait + One External Wait; 2Nd/3Rd/4Th Data: One Internal Wait)
932
Figure 22.21 Burst ROM Bus Cycle (no Wait, Address Setup/Hold Time Insertion, Ans = 1, Anh = 1)
933
Figure 22.22 Burst ROM Bus Cycle (One Internal Wait + One External Wait)
934
Figure 22.23 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011)
935
Burst (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011)
937
Figure 22.25 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RCD[1:0] = 01, CAS Latency = 3)
937
CAS Latency = 3)
938
Figure 22.27 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst (CAS Latency = 3)
939
Figure 22.28 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)
940
Figure 22.29 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)
941
Figure 22.30 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RCD[1:0] = 01, TRWL[2:0] = 010)
942
Figure 22.31 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)
943
Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (TRWL[2:0] = 010)
944
Figure 22.33 Synchronous DRAM Bus Cycle: Synchronous DRAM Precharge Command (TPC[2:0] = 001)
945
Figure 22.34 Synchronous DRAM Bus Cycle: Synchronous DRAM Auto-Refresh (tras = 1, TRC[2:0] = 001)
946
Figure 22.35 Synchronous DRAM Bus Cycle: Synchronous DRAM Self-Refresh (TRC[2:0] = 001)
947
Figure 22.36 (A) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (PALL)
948
Figure 22.36 (B) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (SET)
949
Figure 22.37 DRAM Bus Cycles (1) RCD[1:0] = 00, Anw[2:0] = 000, TPC[2:0] = 001 (2) RCD[1:0] = 01, Anw[2:0] = 001, TPC[2:0] = 010
950
Figure 22.38 DRAM Bus Cycle (EDO Mode, RCD[1:0] = 00, Anw[2:0] = 000, TPC[2:0] = 001)
951
Figure 22.39 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 00, Anw[2:0] = 000, TPC[2:0] = 001)
952
Figure 22.40 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, Anw[2:0] = 001, TPC[2:0] = 001)
953
TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width)
954
Figure 22.42 DRAM Burst Bus Cycle: RAS down Mode State (EDO Mode, RCD[1:0] = 00, Anw[2:0] = 000)
955
Figure 22.43 DRAM Burst Bus Cycle: RAS down Mode Continuation (EDO Mode, RCD[1:0] = 00, Anw[2:0] = 000)
956
Figure 22.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 00, Anw[2:0] = 000, TPC[2:0] = 001)
957
Figure 22.45 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, Anw[2:0] = 001, TPC[2:0] = 001)
958
Figure 22.46 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, Anw[2:0] = 001, TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width)
959
Figure 22.47 DRAM Burst Bus Cycle: RAS down Mode State (Fast Page Mode, RCD[1:0] = 00, Anw[2:0] = 000)
960
(Fast Page Mode, RCD[1:0] = 00, Anw[2:0] = 000)
961
(Tras[2:0] = 000, Trc[2:0] = 001)
962
(Tras[2:0] = 001, Trc[2:0] = 001)
963
Figure 22.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] = 001)
964
Figure 22.52 PCMCIA Memory Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, no Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait
965
Figure 22.53 PCMCIA I/O Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, no Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait
966
Figure 22.54 PCMCIA I/O Bus Cycle (TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait, Bus Sizing)
967
1St Data (One Internal Wait + One External Wait)
968
1St Data (One Internal Wait + One External Wait)
969
1St Data (One Internal Wait), 2Nd to 4Th Data (One Internal Wait + One External Wait)
970
Figure 22.58 MPX Bus Cycle: Burst Write (1) no Internal Wait (2) 1St Data (One Internal Wait), 2Nd to 4Th Data (no Internal Wait + External Wait Control)
971
Basic Read Cycle (One Internal Wait + One External Wait)
972
Figure 22.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (no Wait, Address Setup/Hold Time Insertion, Ans[0] = 1, Anh[1:0] =01)
973
Peripheral Module Signal Timing
974
Table 22.36 Peripheral Module Signal Timing (1)
974
Table 22.36 Peripheral Module Signal Timing (2)
976
Table 22.36 Peripheral Module Signal Timing (3)
978
Figure 22.61 TCLK Input Timing
980
Figure 22.62 RTC Oscillation Settling Time at Power-On
980
Figure 22.63 SCK Input Clock Timing
980
Figure 22.64 SCI I/O Synchronous Mode Clock Timing
981
Figure 22.65 I/O Port Input/Output Timing
981
Figure 22.66(A) DREQ/DRAK Timing
981
Figure 22.66(B) DBREQ/TR Input Timing and BAVL Output Timing
982
AC Characteristic Test Conditions
984
Delay Time Variation Due to Load Capacitance
985
Appendix A Address List
987
Table A.1 Address List
988
Appendix B Package Dimensions
993
Appendix C Mode Pin Settings
997
Appendix D CKIO2ENB Pin Configuration
999
Appendix E Pin Functions
1001
Pin States
1001
Table E.1 Pin States in Reset, Power-Down State, and Bus-Released State
1001
Handling of Unused Pins
1004
Appendix F Synchronous DRAM Address Multiplexing Tables
1005
Appendix G Prefetching of Instructions and Its Side Effects
1027
Hd6417750Sbp200
1029
Table I.1 SH7750 Series Product Code Lineup
1029
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