Hitachi SH7750S SuperH Risc Engine Manuals

Manuals and User Guides for Hitachi SH7750S SuperH Risc Engine. We have 2 Hitachi SH7750S SuperH Risc Engine manuals available for free PDF download: Hardware Manual

Hitachi SH7750S Hardware Manual

Hitachi SH7750S Hardware Manual (1037 pages)

SH7750 Series SuperH RISC engine

Brand: Hitachi | Category: Engine | Size: 5.51 MB

Table of Contents

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Hitachi SH7750S Hardware Manual

Hitachi SH7750S Hardware Manual (858 pages)

SuperH RISC engine

Brand: Hitachi | Category: Engine | Size: 4.47 MB

Table of Contents

Table of Contents
6
Overview
18
SH7750 Series Features
18
Block Diagram
25
Programming Model
26
Data Formats
26
Register Configuration
27
- Privileged Mode and Banks
  27
- General Registers
  28
- Floating-Point Registers
  32
- Control Registers
  34
- System Registers
  35
Memory-Mapped Registers
37
Data Format in Registers
38
Data Formats in Memory
38
Processor States
39
Processor Modes
41
Memory Management Unit (MMU)
42
Overview
42
- Features
  42
- Role of the MMU
  42
- Register Configuration
  45
- Caution
  45
Register Descriptions
46
Memory Space
49
TLB Functions
55
MMU Functions
62
- MMU Hardware Management
  62
- MMU Software Management
  62
- MMU Instruction (LDTLB)
  62
- Hardware ITLB Miss Handling
  63
- Avoiding Synonym Problems
  64
MMU Exceptions
65
Memory-Mapped TLB Configuration
71
- ITLB Address Array
  72
- ITLB Data Array 1
  73
- ITLB Data Array 2
  74
- UTLB Address Array
  74
- UTLB Data Array 1
  76
- UTLB Data Array 2
  77
Caches
78
Overview
78
- Features
  78
- Register Configuration
  79
Register Descriptions
79
Operand Cache (OC)
82
- Configuration
  82
- Read Operation
  83
- Write Operation
  84
- Write-Back Buffer
  86
- Write-Through Buffer
  86
- RAM Mode
  86
- OC Index Mode
  87
- Coherency between Cache and External Memory
  88
- Prefetch Operation
  88
Instruction Cache (IC)
89
- Configuration
  89
- Read Operation
  90
- IC Index Mode
  91
Memory-Mapped Cache Configuration
91
- IC Address Array
  91
- IC Data Array
  92
- OC Address Array
  93
- OC Data Array
  95
Store Queues
96
- SQ Configuration
  96
- SQ Writes
  96
- Transfer to External Memory
  96
- SQ Protection
  98
Exceptions
99
Overview
99
- Features
  99
- Register Configuration
  99
Register Descriptions
100
Exception Handling Functions
101
- Exception Handling Flow
  101
- Exception Handling Vector Addresses
  101
Exception Types and Priorities
102
Exception Flow
104
- Exception Source Acceptance
  105
- Exception Requests and BL Bit
  107
- Return from Exception Handling
  107
Description of Exceptions
107
- Resets
  108
- General Exceptions
  113
- Interrupts
  127
- Priority Order with Multiple Exceptions
  130
Usage Notes
131
Restrictions
132
Floating-Point Unit
133
Overview
133
Data Formats
133
- Floating-Point Format
  133
- Non-Numbers (Nan)
  135
- Denormalized Numbers
  136
Registers
137
Rounding
140
Floating-Point Exceptions
141
Graphics Support Functions
142
- Geometric Operation Instructions
  142
- Pair Single-Precision Data Transfer
  144
Instruction Set
145
Execution Environment
145
Addressing Modes
147
Instruction Set
151
Pipelining
164
Pipelines
164
Parallel-Executability
171
Execution Cycles and Pipeline Stalling
175
Power-Down Modes
191
Overview
191
- Types of Power-Down Modes
  191
- Register Configuration
  193
- Pin Configuration
  193
Register Descriptions
193
Sleep Mode
198
- Transition to Sleep Mode
  198
- Exit from Sleep Mode
  198
Deep Sleep Mode
198
- Transition to Deep Sleep Mode
  198
- Exit from Deep Sleep Mode
  198
Standby Mode
199
- Transition to Standby Mode
  199
- Exit from Standby Mode
  200
- Clock Pause Function
  200
Module Standby Function
201
- Transition to Module Standby Function
  201
- Exit from Module Standby Function
  201
STATUS Pin Change Timing
202
- In Reset
  202
- In Exit from Standby Mode
  203
- In Exit from Sleep Mode
  205
- In Exit from Deep Sleep Mode
  208
Section 10 Clock Oscillation Circuits
210
Overview
210
- Features
  210
Overview of CPG
212
- Block Diagram of CPG
  212
- CPG Pin Configuration
  214
- CPG Register Configuration
  214
Clock Operating Modes
215
CPG Register Description
216
- Frequency Control Register (FRQCR)
  216
Changing the Frequency
219
Output Clock Control
220
Overview of Watchdog Timer
221
- Block Diagram
  221
- Register Configuration
  222
WDT Register Descriptions
222
Using the WDT
225
- Standby Clearing Procedure
  225
- Frequency Changing Procedure
  226
- Using Watchdog Timer Mode
  226
- Using Interval Timer Mode
  227
Notes on Board Design
227
Section 11 Realtime Clock (RTC)
229
Overview
229
- Features
  229
- Block Diagram
  230
- Pin Configuration
  231
- Register Configuration
  231
Register Descriptions
233
- 64 Hz Counter (R64CNT)
  233
- Second Counter (RSECCNT)
  233
- Minute Counter (RMINCNT)
  234
- Hour Counter (RHRCNT)
  234
- Day-Of-Week Counter (RWKCNT)
  235
- Day Counter (RDAYCNT)
  236
- Month Counter (RMONCNT)
  236
- Year Counter (RYRCNT)
  237
- Second Alarm Register (RSECAR)
  238
- Minute Alarm Register (RMINAR)
  238
- Hour Alarm Register (RHRAR)
  239
- Day-Of-Week Alarm Register (RWKAR)
  239
- Day Alarm Register (RDAYAR)
  240
- Month Alarm Register (RMONAR)
  241
- RTC Control Register 1 (RCR1)
  241
- RTC Control Register 2 (RCR2)
  243
Operation
246
- Time Setting Procedures
  246
- Time Reading Procedures
  247
- Alarm Function
  249
Interrupts
250
Usage Notes
250
- Register Initialization
  250
- Crystal Oscillator Circuit
  250
Section 12 Timer Unit (TMU)
252
Overview
252
- Features
  252
- Block Diagram
  253
- Pin Configuration
  253
- Register Configuration
  254
Register Descriptions
255
- Timer Output Control Register (TOCR)
  255
- Timer Start Register (TSTR)
  256
- Timer Constant Registers (TCOR)
  257
- Timer Counters (TCNT)
  257
- Timer Control Registers (TCR)
  258
- Input Capture Register (TCPR2)
  261
Operation
262
- Counter Operation
  262
- Input Capture Function
  265
Interrupts
266
Usage Notes
267
- Register Writes
  267
- TCNT Register Reads
  267
- Resetting the RTC Frequency Divider
  267
- External Clock Frequency
  267
Section 13 Bus State Controller (BSC)
268
Overview
268
- Features
  268
- Block Diagram
  270
- Pin Configuration
  271
- Register Configuration
  275
- Overview of Areas
  276
- PCMCIA Support
  279
Register Descriptions
283
Operation
320
- Endian/Access Size and Data Alignment
  320
- Areas
  331
- Basic Interface
  335
- DRAM Interface
  343
- Synchronous DRAM Interface
  361
- Burst ROM Interface
  385
- PCMCIA Interface
  388
- MPX Interface
  399
- Byte Control SRAM
  416
- 13.3.10 Waits between Access Cycles
  421
- 13.3.11 Bus Arbitration
  422
- 13.3.12 Master Mode
  426
- 13.3.13 Slave Mode
  427
- 13.3.14 Partial-Sharing Master Mode
  427
- 13.3.15 Cooperation between Master and Slave
  429
- 13.3.16 Notes on Usage
  429
Section 14 Direct Memory Access Controller (DMAC)
430
Overview
430
- Features
  430
- Block Diagram
  432
- Pin Configuration
  433
- Register Configuration
  434
Register Descriptions
436
Operation
450
- DMA Transfer Requests
  452
- Channel Priorities
  455
- Types of DMA Transfer
  458
- Number of Bus Cycle States and '5
  467
- Ending DMA Transfer
  481
Examples of Use
484
- Examples of Transfer between External Memory and an External Device with DACK
  484
On-Demand Data Transfer Mode
485
- Operation
  485
- Pins in DDT Mode
  487
- Transfer Request Acceptance on each Channel
  490
- Notes on Use of DDT Module
  510
Usage Notes
513
Section 15 Serial Communication Interface (SCI)
514
Overview
514
- Features
  514
- Block Diagram
  516
- Pin Configuration
  517
- Register Configuration
  517

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