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SIGNAL NAME
RD-
(Read)
WR-
(Write)
RFSH-
(Refresh)
HALT-
WAIT-
INT-
(Interrupt
Request)
NMI-
(Non-Maskable
Interrupt)
Table 3-4. Z-80B CPU Signals (Continued)
FUNCTION
Tri-state output, active low.
Indicates that the CPU wants to read data
from memory or an I/O device.
Memory or
I/O device uses this signal to gate data onto
the CPU data bus.
Tri-state output, active low.
Indicates that the CPU data bus holds valid
data for the addressed memory or I/O device.
Not used by the MUX card.
Not used by the MUX card.
Input, active low.
Indicates to the Z-80B CPU that the addressed
memory or I/O devices are not ready for a
data transfer.
This signal allows memory
or I/O devices of any speed to be
synchronized to the Z-80B CPU.
Input, active low.
Generated by I/O devices.
A request will be
honored at the end of the current instruction
if an internal Interrupt Enable flip-flop
is enabled and if the BUSRQ- signal is not
active.
Not used by the MUX card.
This signal is
tied to +5V through a 3.3K ohm resistor.
3-11
HP 27130B
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