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1.6 Block Diagram
TI00/TO0/P70
16-bit timer/
event counter
TI01/P71
8-bit timer/
TI50/TO50/P72
event counter 50
8-bit timer/
TI51/TO51/P73
event counter 51
Watchdog timer
Watch timer
SI30/P20
SO30/P21
SCK30/P22
SI31/P34
SO31/P35
SCK31/P36
RxD0/P23
TxD0/P24
ASCK0/P25
ANI0/P10 to
ANI3/P13
AV
DD
A/D converter
AV
SS
AV
REF
INTP0/P00 to
Interrupt control
INTP3/P03
BUZ/P75
Buzzer output
PCL/P74
Remarks 1. The internal ROM and RAM capacities depend on the product.
2. Pin connection in parentheses is intended for the µ PD78F0034BS.
30
CHAPTER 1 OUTLINE
78K/0
CPU core
Serial
interface 30
Serial
interface 31
RAM
UART0
Clock output
V
V
control
DD0
Preliminary User's Manual U16035EJ1V0UM
ROM
System control
V
V
IC
DD1
SS0
SS1
(V
)
PP
Port 0
P00 to P03
Port 1
P10 to P13
Port 2
P20 to P25
Port 3
P34 to P36
Port 4
P40 to P47
Port 5
P50 to P57
Port 7
P70 to P75
RESET
X1
X2
XT1
XT2
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