Page 1 User’s Manual µ PD789104, 789114, 789124, 789134 Subseries 8-bit Single-chip Microcontrollers µ PD789101 µ PD789121 µ PD789102 µ PD789122 µ PD789104 µ PD789124 µ PD789111 µ PD789131 µ PD789112 µ PD789132 µ PD789114 µ PD789134 µ PD78F9116 µ PD78F9136 Document No. U13045EJ2V0UM00 (2nd edition) Date Published July 1999 N CP(K) ©...
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Page 3 Reset operation must be executed immediately after power-on for devices having reset function. EEPROM is a trademark of NEC Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
Page 4 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability •...
Page 6 Major Revisions in This Edition Page Description Throughout Deletion of 28-pin plastic shrink DIP Addition of 30-pin plastic shrink DIP in the “in planning“ status Deletion of description “under development” from mask ROM versions and the µ PD78F9116 Addition of MC-5A4 type to the packages Modification of the minimum power-supply voltage from 1.8 V to 2.7 V p.
Page 7 INTRODUCTION Target Readers This manual is intended for users who wish to understand the functions of the µ PD789104, 789114, 789124, 789134 Subseries and to design and develop application systems and programs using these microcontrollers. The target devices are shown as follows: •...
Page 8 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: ××× (overscore over pin or signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ...
Page 9 Japanese SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Devices C11531E C11531J NEC Semiconductor Device Reliability/Quality Control System C10983E C10983J Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
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Page 11: Table Of Contents
CONTENTS CHAPTER 1 GENERAL ( µ PD789104, 789114 SUBSERIES) ............1.1 Features ..........................1.2 Applications ........................1.3 Ordering Information ......................1.4 Pin Configuration (Top View) ................... 1.5 78K/0S Series Lineup ......................1.6 Block Diagram ........................1.7 Outline of Functions ......................CHAPTER 2 GENERAL ( µ...
Page 12 4.2.1 Control registers ........................4.2.2 General registers ........................4.2.3 Special function registers (SFRs) .................... 4.3 Instruction Address Addressing ..................4.3.1 Relative addressing ........................4.3.2 Immediate addressing ......................4.3.3 Table indirect addressing ......................4.3.4 Register addressing ......................... 4.4 Operand Address Addressing ..................4.4.1 Direct addressing ........................
Page 13 7.4 System Clock Oscillator ....................7.4.1 System clock oscillator ......................7.4.2 Divider ............................7.5 Operation of Clock Generator ..................100 7.6 Changing Setting of CPU Clock ..................101 7.6.1 Time required for switching CPU clock ................... 7.6.2 Switching CPU clock ........................ CHAPTER 8 16-BIT TIMER COUNTER ....................
Page 14 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD789114, 789134 SUBSERIES) ......149 12.1 10-Bit A/D Converter Functions ..................149 12.2 10-Bit A/D Converter Configuration ................149 12.3 Registers Controlling 10-Bit A/D Converter ..............152 12.4 10-Bit A/D Converter Operation ..................154 12.4.1 Basic operation of 10-bit A/D converter ................
Page 15 18.1.1 Selecting communication mode ..................... 18.1.2 Function of flash memory programming ................18.1.3 Flashpro III connection example ................... 18.1.4 Example of settings for Flashpro III (PG-FP3) ............... CHAPTER 19 MASK OPTION (MASK ROM VERSION) ..............239 CHAPTER 20 INSTRUCTION SET ....................241 20.1 Operation ...........................
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Page 17 LIST OF FIGURES (1/4) Figure No. Title Page 3-1. Pin Input/Output Circuits ........................Memory Map ( µ PD789101, 789111, 789121, 789131) ..............4-1. Memory Map ( µ PD789102, 789112, 789122, 789132) ..............4-2. Memory Map ( µ PD789104, 789114, 789124, 789134) ..............4-3.
Page 18 LIST OF FIGURES (2/4) Figure No. Title Page 8-1. Block Diagram of 16-Bit Timer Counter ..................... 8-2. 16-Bit Timer Mode Control Register 20 Format ................8-3. Port Mode Register 2 Format ......................8-4. Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation ......8-5.
Page 19 LIST OF FIGURES (3/4) Figure No. Title Page 12-6. Software-Started A/D Conversion ...................... 12-7. How to Reduce Current Consumption in Standby Mode ..............12-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value) ...... 12-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value) ......12-10.
Page 20 LIST OF FIGURES (4/4) Figure No. Title Page 17-1. Block Diagram of Reset Function ...................... 17-2. Reset Timing by RESET Input ......................17-3. Reset Timing by Overflow in Watchdog Timer .................. 17-4. Reset Timing by RESET Input in STOP Mode .................. 18-1.
Page 21 LIST OF TABLES (1/2) Table No. Title Page 3-1. Types of Pin Input/Output Circuits and Recommended Connection of Unused Pins ...... 4-1. Internal ROM Capacity ........................4-2. Vector Table ............................4-3. Special Function Register List ......................5-1. Port Functions ............................. 5-2.
Page 22 LIST OF TABLES (2/2) Table No. Title Page 13-4. Relationship between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) ......................13-5. Example of Relationship between System Clock and Baud Rate ............ 13-6. Relationship between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) ................
Page 23: Chapter 1 General ( Μ Pd789104, 789114 Subseries)
CHAPTER 1 GENERAL ( µ PD789104, 789114 SUBSERIES) 1.1 Features ROM and RAM capacities Item Program Memory Data Memory Part Number (Internal High-Speed RAM) µ PD789101, 789111 2 Kbytes 256 bytes µ PD789102, 789112 4 Kbytes µ PD789104, 789114 8 Kbytes µ...
Page 24: Ordering Information
CHAPTER 1 GENERAL ( µ PD789104, 789114 SUBSERIES) 1.3 Ordering Information Part Number Package Internal ROM µ PD789101GS-××× 30-pin plastic shrink SOP (300 mil, resin thickness 1.7 mm) Mask ROM µ PD789101MC-×××-5A4 30-pin plastic shrink SOP (300 mil, resin thickness 1.2 mm) Mask ROM µ...
Page 25: Pin Configuration (Top View)
CHAPTER 1 GENERAL ( µ PD789104, 789114 SUBSERIES) 1.4 Pin Configuration (Top View) • 30-pin plastic shrink SOP (300 mil, resin thickness 1.7 mm) µ PD789101GS-××× µ PD789111GS-××× µ PD789102GS-××× µ PD789112GS-××× µ PD789104GS-××× µ PD789114GS-××× µ PD78F9116GS • 30-pin plastic shrink SOP (300 mil, resin thickness 1.2 mm) µ...
Page 26 CHAPTER 1 GENERAL ( µ PD789104, 789114 SUBSERIES) ANI0 to ANI3: Analog Input RxD20: Receive Data ASCK20: Asynchronous Serial Input SCK20: Serial Clock Analog Power Supply SI20: Serial Input Analog Ground SO20: Serial Output CPT20: Capture Trigger Input SS20: Chip Select Input IC0: Internally Connected TI80:...
Page 27: 0S Series Lineup
CHAPTER 1 GENERAL ( µ PD789104, 789114 SUBSERIES) 1.5 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products in mass-production Products under development Small-scale package, general-purpose applications µ µ...
Page 28 CHAPTER 1 GENERAL ( µ PD789104, 789114 SUBSERIES) The major functional differences between the subseries are listed below. Function Timer 8-bit 10-bit Serial Interface Remark Capacity 8-bit 16-bit Watch WDT A/D MIN. Value Subseries Name Small-scale µ PD789046 16 K 1 ch 1 ch 1 ch 1 ch –...
Page 29: Block Diagram
CHAPTER 1 GENERAL ( µ PD789104, 789114 SUBSERIES) 1.6 Block Diagram TI80/INTP2/P25 8-bit TIMER PORT0 P00 to P03 EVENT/COUNTER 80 TO80/TO20 /INTP1/P24 TO20/TO80 PORT1 P10, P11 /INTP1/P24 16-bit TIMER COUNTER 20 CPT20/INTP0 /SS20/P23 P20 to P25 PORT2 WATCHDOG TIMER 78K/0S (FLASH CPU CORE MEMORY)
Page 30: Outline Of Functions
CHAPTER 1 GENERAL ( µ PD789104, 789114 SUBSERIES) 1.7 Outline of Functions µ PD789101 µ PD789102 µ PD789104 µ PD78F9116 Item µ PD789111 µ PD789112 µ PD789114 Maks ROM Mask ROM Flash memory Internal memory 2 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes High-speed RAM 256 bytes...
Page 31: Chapter 2 General ( Μ Pd789124, 789134 Subseries)
CHAPTER 2 GENERAL ( µ PD789124, 789134 SUBSERIES) 2.1 Features ROM and RAM capacities Item Program Memory Data Memory Part Number (Internal High-Speed RAM) µ PD789121, 789131 2 Kbytes 256 bytes µ PD789122, 789132 4 Kbytes µ PD789124, 789134 8 Kbytes µ...
Page 32: Ordering Information
CHAPTER 2 GENERAL ( µ PD789124, 789134 SUBSERIES) 2.3 Ordering Information Part Number Package Internal ROM µ PD789121GS-××× 30-pin plastic shrink SOP (300 mil, resin thickness 1.7 mm) Mask ROM µ PD789121MC-×××-5A4 30-pin plastic shrink SOP (300 mil, resin thickness 1.2 mm) Mask ROM µ...
Page 33: Pin Configuration (Top View)
CHAPTER 2 GENERAL ( µ PD789124, 789134 SUBSERIES) 2.4 Pin Configuration (Top View) • 30-pin plastic shrink SOP (300 mil, resin thickness 1.7 mm) µ PD789121GS-××× µ PD789131GS-××× µ PD789122GS-××× µ PD789132GS-××× µ PD789124GS-××× µ PD789134GS-××× µ PD78F9136GS Note • 30-pin plastic shrink SOP (300 mil, resin thickness 1.2 mm) µ...
Page 34 CHAPTER 2 GENERAL ( µ PD789124, 789134 SUBSERIES) ANI0 to ANI3: Analog Input RESET: Reset ASCK20: Asynchronous Serial Input RxD20: Receive Data Analog Power Supply SCK20: Serial Clock Analog Ground SI20: Serial Input CL1, CL2: RC oscillator SO20: Serial Output CPT20: Capture Trigger Input SS20:...
Page 35: 0S Series Lineup
CHAPTER 2 GENERAL ( µ PD789124, 789134 SUBSERIES) 2.5 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products in mass-production Products under development Small-scale package, general-purpose applications µ µ...
Page 36 CHAPTER 2 GENERAL ( µ PD789124, 789134 SUBSERIES) The major functional differences between the subseries are listed below. Function Timer 8-bit 10-bit Serial Interface Remark Capacity 8-bit 16-bit Watch WDT A/D MIN. Value Subseries Name Small-scale µ PD789046 16 K 1 ch 1 ch 1 ch 1 ch –...
Page 37: Block Diagram
CHAPTER 2 GENERAL ( µ PD789124, 789134 SUBSERIES) 2.6 Block Diagram TI80/INTP2/P25 8-bit TIMER PORT0 P00 to P03 EVENT/COUNTER 80 TO80/TO20 /INTP1/P24 TO20/TO80 PORT1 P10, P11 16-bit TIMER /INTP1/P24 COUNTER 20 CPT20/INTP0 /SS20/P23 P20 to P25 PORT2 WATCHDOG TIMER 78K/0S (FLASH CPU CORE MEMORY)
Page 38: Outline Of Functions
CHAPTER 2 GENERAL ( µ PD789124, 789134 SUBSERIES) 2.7 Outline of Functions µ PD789121 µ PD789122 µ PD789124 µ PD78F9136 Item µ PD789131 µ PD789132 µ PD789134 Internal memory Mask ROM Flash memory 2 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes High-speed RAM 256 bytes System clock...
Page 39: Chapter 3 Pin Functions
CHAPTER 3 PIN FUNCTIONS 3.1 Pin Function List (1) Port pins Pin Name Input/Output Function After Reset Alternate Function P00 to P03 Input/output Port 0 Input — 4-bit input/output port Input/output can be specified in 1-bit units When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0).
Page 40 CHAPTER 3 PIN FUNCTIONS (2) Non-port pins Pin Name Input/Output Function After Reset Alternate Function INTP0 Input External interrupt input for which the valid edge (rising Input P23/CPT20/SS20 INTP1 edge, falling edge, or both rising and falling edges) P24/TO80/TO20 INTP2 can be specified.
Page 41: Description Of Pin Functions
CHAPTER 3 PIN FUNCTIONS 3.2 Description of Pin Functions 3.2.1 P00 to P03 (Port 0) These pins constitute a 4-bit I/O port and can be set in input or output port mode in 1-bit units by using port mode register 0 (PM0). When these pins are used as an input port, use of an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0).
Page 42: P50 To P53 (Port 5)
CHAPTER 3 PIN FUNCTIONS (h) RxD20, TxD20 These are the serial data I/O pins of the asynchronous serial interface. (i) ASCK20 This is the serial clock input pin of the asynchronous serial interface. Caution When using these pins as serial interface pins, the input/output mode and output latch must be set according to the functions to be used.
Page 43: Pp ( Μ Pd78F9116, 78F9136 Only)
CHAPTER 3 PIN FUNCTIONS ( µ PD78F9116, 78F9136 only) 3.2.13 V A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. Directly connect this pin to V in the normal operation mode.
Page 44: Pin Input/Output Circuits And Recommended Connection Of Unused Pins
CHAPTER 3 PIN FUNCTIONS 3.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins The input/output circuit type for each pin and the recommended connection of pins are shown in Table 3-1. For the input/output circuit configuration of each type, refer to Figure 3-1. Table 3-1.
Page 45 CHAPTER 3 PIN FUNCTIONS Figure 3-1. Pin Input/Output Circuits Type 2 Type 9-C Comparator P-ch N-ch – (Threshold voltage) Schmitt-triggered input with hysteresis characteristics Input enable Type 13-V Type 5-A Pull-up P-ch IN/OUT enable Output data N-ch Output disable Data P-ch IN/OUT Input enable...
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Page 47: Chapter 4 Cpu Architecture
CHAPTER 4 CPU ARCHITECTURE 4.1 Memory Space The µ PD789134 Subseries can access 64 Kbytes of memory space. Figures 4-1 through 4-4 show the memory maps. Figure 4-1. Memory Map ( µ PD789101, 789111, 789121, 789131) FFFFH Special function registers 256 ×...
Page 48 CHAPTER 4 CPU ARCHITECTURE Figure 4-2. Memory Map ( µ PD789102, 789112, 789122, 789132) FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 256 × 8 bits FE00H FDFFH Reserved Data memory space 0FFFH 1000H 0FFFH Program area 0080H Program...
Page 49 CHAPTER 4 CPU ARCHITECTURE Figure 4-3. Memory Map ( µ PD789104, 789114, 789124, 789134) FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 256 × 8 bits FE00H FDFFH Reserved Data memory space 1FFFH 2000H 1FFFH Program area 0080H Program...
Page 50 CHAPTER 4 CPU ARCHITECTURE Figure 4-4. Memory Map ( µ PD78F9116, 78F9136) FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 256 × 8 bits FE00H FDFFH Reserved Data memory space 3FFFH 4000H 3FFFH Program area 0080H Program Flash memory...
Page 51: Internal Program Memory Space
CHAPTER 4 CPU ARCHITECTURE 4.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The µ PD789134 Subseries provides the following internal ROMs (or flash memory) containing the following capacities.
Page 52: Internal Data Memory (Internal High-Speed Ram) Space
CHAPTER 4 CPU ARCHITECTURE 4.1.2 Internal data memory (internal high-speed RAM) space The µ PD789134 Subseries provides a 256-byte internal high-speed RAM. The internal high-speed RAM can also be used as a stack memory. 4.1.3 Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (refer to Table 4-3).
Page 53 CHAPTER 4 CPU ARCHITECTURE Figure 4-6. Data Memory Addressing ( µ PD789102, 789112, 789122, 789132) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short direct Internal high-speed RAM addressing 256 × 8 bits FE20H FE1FH FE00H...
Page 54 CHAPTER 4 CPU ARCHITECTURE Figure 4-7. Data Memory Addressing ( µ PD789104, 789114, 789124, 789134) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short direct Internal high-speed RAM addressing 256 × 8 bits FE20H FE1FH FE00H...
Page 55 CHAPTER 4 CPU ARCHITECTURE Figure 4-8. Data Memory Addressing ( µ PD78F9116, 78F9136) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short direct Internal high-speed RAM addressing 256 × 8 bits FE20H FE1FH FE00H FDFFH Direct addressing...
Page 56: Processor Registers
CHAPTER 4 CPU ARCHITECTURE 4.2 Processor Registers The µ PD789134 Subseries provides the following on-chip processor registers: 4.2.1 Control registers The control registers contain special functions to control the program sequence statuses and stack memory. The program counter, program status word, and stack pointer are control registers. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
Page 57 CHAPTER 4 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of CPU. When IE = 0, the IE is set to interrupt disabled (DI) status. All interrupt requests except non-maskable interrupt are disabled. When IE = 1, the IE is set to interrupt enabled (EI) status and interrupt request acknowledgement is controlled with an interrupt mask flag for various interrupt sources.
Page 58 CHAPTER 4 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 4-11. Stack Pointer Configuration SP15 SP14 SP13 SP12 SP11 SP10 SP9...
Page 59: General Registers
CHAPTER 4 CPU ARCHITECTURE 4.2.2 General registers The general registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and in addition, two 8-bit registers in pairs can be used as a 16- bit register (AX, BC, DE, and HL).
Page 60: Special Function Registers (Sfrs)
CHAPTER 4 CPU ARCHITECTURE 4.2.3 Special function registers (SFRs) Unlike general registers, special function registers have their own functions and are allocated to the 256-byte area FF00H to FFFFH. Special function registers can be manipulated, like general registers, with operation, transfer, and bit manipulation instructions.
Page 61 CHAPTER 4 CPU ARCHITECTURE Table 4-3. Special Function Register List (1/2) Address Special Function Register (SFR) Name Symbol Bit Units for Manipulation After Reset 1 bit 8 bits 16 bits √ √ FF00H Port 0 — √ √ FF01H Port 1 —...
Page 62 CHAPTER 4 CPU ARCHITECTURE Table 4-3. Special Function Register List (2/2) Address Special Function Register (SFR) Name Symbol Bit Units for Manipulation After Reset 1 bit 8 bits 16 bits √ √ FF70H Asynchronous serial interface mode register 20 ASIM20 —...
Page 63: Instruction Address Addressing
CHAPTER 4 CPU ARCHITECTURE 4.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 64: Immediate Addressing
CHAPTER 4 CPU ARCHITECTURE 4.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the “CALL !addr16 and BR !addr16” instructions are executed. CALL !addr16 and BR !addr16 instructions can branch to all the memory spaces. [Illustration] In case of CALL !addr16, BR !addr16 instruction CALL or BR...
Page 65: Register Addressing
CHAPTER 4 CPU ARCHITECTURE 4.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched.
Page 66: Operand Address Addressing
CHAPTER 4 CPU ARCHITECTURE 4.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 4.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier Description...
Page 67: Short Direct Addressing
CHAPTER 4 CPU ARCHITECTURE 4.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space where this addressing is applied to is the 256-byte space FE20H to FF1FH. An internal high- speed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 68: Special Function Register (Sfr) Addressing
CHAPTER 4 CPU ARCHITECTURE 4.4.3 Special function register (SFR) addressing [Function] Memory-mapped special function registers (SFRs) are addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 69: Register Addressing
CHAPTER 4 CPU ARCHITECTURE 4.4.4 Register addressing [Function] General registers are accessed as operands. The general register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
Page 70: Register Indirect Addressing
CHAPTER 4 CPU ARCHITECTURE 4.4.5 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces.
Page 71: Based Addressing
CHAPTER 4 CPU ARCHITECTURE 4.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits.
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Page 73: Chapter 5 Port Functions
CHAPTER 5 PORT FUNCTIONS 5.1 Functions of Ports The µ PD789134 Subseries provides the ports shown in Figure 5-1, enabling various methods of control. Numerous other functions are provided that can be used in addition to the digital I/O port function. For more information on these additional functions, refer to CHAPTER 3 PIN FUNCTIONS.
Page 74 CHAPTER 5 PORT FUNCTIONS Table 5-1. Port Functions Pin Name Input/Output Function After Reset Alternate Function P00 to P03 Input/output Port 0 Input — 4-bit I/O port Input/output can be specified in 1-bit units When used as input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0).
Page 75: Port Configuration
CHAPTER 5 PORT FUNCTIONS 5.2 Port Configuration A port consists of the following hardware. Table 5-2. Configuration of Port Parameter Configuration Control register Port mode register (PMm: m = 0 to 2, 5) Pull-up resistor option register 0 (PU0) Pull-up option register B2 (PUB2) Port Total: 20 (input: 7, input/output: 16) Pull-up resistor...
Page 76: Port 1
CHAPTER 5 PORT FUNCTIONS 5.2.2 Port 1 This is a 2-bit I/O port with output latches. Port 1 can be specified as input or output mode in 1-bit units by using port mode register 1 (PM1). When pins P10 and P11 are used as input port pins, on-chip pull-up resistors can be connected in 2-bit units by using pull-up resistor option register 0 (PU0).
Page 77: Port 2
CHAPTER 5 PORT FUNCTIONS 5.2.3 Port 2 This is a 6-bit I/O port with output latches. Port 2 can be specified as input or output mode in 1-bit units by using port mode register 2 (PM2). Use of on-chip pull-up resistors can be specified for pins P20 to P25 in 1-bit units by using pull-up resistor option register B2 (PUB2).
Page 78 CHAPTER 5 PORT FUNCTIONS Figure 5-5. Block Diagram of P21 PUB2 PUB21 P-ch PORT Output latch P21/TxD20/ (P21) SO20 PM21 Alternate function Serial output enable signal PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U13045EJ2V0UM00...
Page 79 CHAPTER 5 PORT FUNCTIONS Figure 5-6. Block Diagram of P22, P23, and P25 PUB2 PUB22, PUB23, P-ch PUB25 Alternate function PORT Output latch P22/RxD20/SI20 (P22, P23, P25) P23/INTP0/CPT20/ SS20 P25/INTP2/TI80 PM22, PM23, PM25 PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U13045EJ2V0UM00...
Page 80 CHAPTER 5 PORT FUNCTIONS Figure 5-7. Block Diagram of P24 PUB2 PUB24 P-ch Alternate function P24/INTP1/ TO80/TO20 PORT Output latch (P24) PM24 Alternate function Alternate function PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U13045EJ2V0UM00...
Page 81: Port 5
CHAPTER 5 PORT FUNCTIONS 5.2.4 Port 5 This is a 4-bit N-ch open-drain I/O port with output latches. Port 5 can be specified as input or output mode in 1-bit units by using port mode register 5 (PM5). For a mask ROM version, whether a pull-up resistor is to be incorporated can be specified by the mask option.
Page 82: Port 6
CHAPTER 5 PORT FUNCTIONS 5.2.5 Port 6 This is a 4-bit input port. The port is also used as an analog input to the A/D converter. RESET input sets port 6 to input mode. Figure 5-9 shows a block diagram of port 6. Figure 5-9.
Page 83: Port Function Control Registers
CHAPTER 5 PORT FUNCTIONS 5.3 Port Function Control Registers The following three types of registers control the ports. • Port mode registers (PM0 to PM2, PM5) • Pull-up resistor option register 0 (PU0) • Pull-up resistor option register B2 (PUB2) (1) Port mode registers (PM0 to PM2, PM5) These registers are used to set port input/output in 1-bit units.
Page 84 CHAPTER 5 PORT FUNCTIONS Figure 5-10. Port Mode Register Format Symbol Address After reset PM03 PM02 PM01 PM00 FF20H FF21H PM11 PM10 PM25 PM24 PM23 PM22 PM21 PM20 FF22H PM53 PM52 PM51 PM50 FF25H PMmn Pmn pin input/output mode selection (m = 0 to 2, 5, n = 0 to 7) Output mode (output buffer ON) Input mode (output buffer OFF) (2) Pull-up resistor option register 0 (PU0)
Page 85: Operation Of Port Functions
CHAPTER 5 PORT FUNCTIONS 5.4 Operation of Port Functions The operation of a port differs depending on whether the port is set in input or output mode, as described below. 5.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port.
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Page 87: Chapter 6 Clock Generator ( Μ Pd789104, 789114 Subseries)
CHAPTER 6 CLOCK GENERATOR ( µ PD789104, 789114 SUBSERIES) 6.1 Function of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The system clock oscillator is the following type. • System clock (crystal/ceramic) oscillator This circuit oscillates at frequencies of 1.0 to 5.0 MHz.
Page 88: Register Controlling Clock Generator
CHAPTER 6 CLOCK GENERATOR ( µ PD789104, 789114 SUBSERIES) 6.3 Register Controlling Clock Generator The clock generator is controlled by the following register: • Processor clock control register (PCC) (1) Processor clock control register (PCC) PCC sets the CPU clock selection and the ratio of division. PCC is set with a 1-bit or 8-bit memory manipulation instruction.
Page 89: System Clock Oscillator
CHAPTER 6 CLOCK GENERATOR ( µ PD789104, 789114 SUBSERIES) 6.4 System Clock Oscillator 6.4.1 System clock oscillator The system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the system clock oscillator. In this case, input the clock signal to the X1 pin, and leave the X2 pin open.
Page 90 CHAPTER 6 CLOCK GENERATOR ( µ PD789104, 789114 SUBSERIES) Figure 6-4. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORTn (n = 0 to 2, 5, 6) User’s Manual U13045EJ2V0UM00...
Page 91 CHAPTER 6 CLOCK GENERATOR ( µ PD789104, 789114 SUBSERIES) Figure 6-4. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current High current (e) Signal is fetched User’s Manual U13045EJ2V0UM00...
Page 92: Divider
CHAPTER 6 CLOCK GENERATOR ( µ PD789104, 789114 SUBSERIES) 6.4.2 Divider The divider divides the output of the system clock oscillator (f ) to generate various clocks. 6.5 Operation of Clock Generator The clock generator generates the following clocks and controls the operating modes of the CPU, such as the standby mode: •...
Page 93: Changing Setting Of Cpu Clock
CHAPTER 6 CLOCK GENERATOR ( µ PD789104, 789114 SUBSERIES) 6.6 Changing Setting of CPU Clock 6.6.1 Time required for switching CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC). Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old clock is used for the duration of several instructions after that (refer to Table 6-2).
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Page 95: Chapter 7 Clock Generator ( Μ Pd789124, 789134 Subseries)
CHAPTER 7 CLOCK GENERATOR ( µ PD789124, 789134 SUBSERIES) 7.1 Function of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The system clock oscillator consists of the following type. • System clock (RC) oscillator This circuit oscillates at frequencies of 2.0 to 4.0 MHz.
Page 96: Register Controlling Clock Generator
CHAPTER 7 CLOCK GENERATOR ( µ PD789124, 789134 SUBSERIES) 7.3 Register Controlling Clock Generator The clock generator is controlled by the following register: • Processor clock control register (PCC) (1) Processor clock control register (PCC) PCC sets the CPU clock selection and the ratio of division. PCC is set with a 1-bit or 8-bit memory manipulation instruction.
Page 97: System Clock Oscillator
CHAPTER 7 CLOCK GENERATOR ( µ PD789124, 789134 SUBSERIES) 7.4 System Clock Oscillator 7.4.1 System clock oscillator The system clock oscillator is oscillated by the resistor (R) and capacitor (C) (4.0 MHz TYP.) connected across the CL1 and CL2 pins. An external clock can also be input to the system clock oscillator.
Page 98 CHAPTER 7 CLOCK GENERATOR ( µ PD789124, 789134 SUBSERIES) Figure 7-4. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORTn (n = 0 to 2, 5, 6) User’s Manual U13045EJ2V0UM00...
Page 99 CHAPTER 7 CLOCK GENERATOR ( µ PD789124, 789134 SUBSERIES) Figure 7-4. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator (potential at points A and B fluctuates) PORTn (n = 0 to 2, 5, 6) High current (e) Signal is fetched User’s Manual U13045EJ2V0UM00...
Page 100: Divider
CHAPTER 7 CLOCK GENERATOR ( µ PD789124, 789134 SUBSERIES) 7.4.2 Divider The divider divides the output of the system clock oscillator (f ) to generate various clocks. 7.5 Operation of Clock Generator The clock generator generates the following clocks and controls the operating modes of the CPU, such as the standby mode: •...
Page 101: Changing Setting Of Cpu Clock
CHAPTER 7 CLOCK GENERATOR ( µ PD789124, 789134 SUBSERIES) 7.6 Changing Setting of CPU Clock 7.6.1 Time required for switching CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC). Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old clock is used for the duration of several instructions after that (refer to Table 7-2).
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Page 103: Chapter 8 16-Bit Timer Counter
CHAPTER 8 16-BIT TIMER COUNTER The µ PD789134 Subseries features the following on-chip timers. (1) 16-bit timer counter 20 (TM20) The 16-bit timer counter references the free running counter and provides the functions such as timer interrupt and timer output. In addition, the count value can be captured by a trigger pin. (2) 8-bit timer/event counter 80 (TM80) The 8-bit timer/event counter can be used as an interval timer, external event counter, and for square wave output and PWM output of arbitrary frequency (see CHAPTER 9 8-BIT TIMER/EVENT COUNTER).
Page 104: 16-Bit Timer Counter Functions
CHAPTER 8 16-BIT TIMER COUNTER 8.1 16-Bit Timer Counter Functions 16-bit timer counter 20 (TM20) has the following functions. • Timer interrupt • Timer output • Count value capture (1) Timer interrupt An interrupt is generated when a count value and compare value matches. (2) Timer output Timer output control is possible when an count value and compare value matches.
Page 105: 16-Bit Timer Counter Configuration
CHAPTER 8 16-BIT TIMER COUNTER 8.2 16-Bit Timer Counter Configuration 16-bit timer counter 20 (TM20) consists of the following hardware. Table 8-2. Configuration of 16-Bit Timer Counter Item Configuration 16 bits × 1 (TM20) Timer register Compare register: 16 bits × 1 (CR20) Register 16 bits ×...
Page 106 CHAPTER 8 16-BIT TIMER COUNTER (1) 16-bit compare register 20 (CR20) This register compares the value set to CR20 with the count value of 16-bit timer register 20 (TM20), and when they match, generates an interrupt request (INTTM20). CR20 is set with a 16-bit memory manipulation instruction. The values 0000H to FFFFH can be set. RESET input sets this register to FFFFH.
Page 107: Registers Controlling 16-Bit Timer Counter
CHAPTER 8 16-BIT TIMER COUNTER 8.3 Registers Controlling 16-Bit Timer Counter The following two types of registers control 16-bit timer counter 20 (TM20). • 16-bit timer mode control register 20 (TMC20) • Port mode register 2 (PM2) (1) 16-bit timer mode control register 20 (TMC20) 16-bit timer mode control register 20 (TMC20) controls the setting of the counter clock, capture edge, etc.
Page 108 CHAPTER 8 16-BIT TIMER COUNTER Figure 8-2. 16-Bit Timer Mode Control Register 20 Format <6> <0> Symbol Address After reset TMC20 TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 FF48H Note TOD20 Timer output data Timer output of 0 Timer output of 1 TOF20 Overflow flag set Clear by reset and software...
Page 109 CHAPTER 8 16-BIT TIMER COUNTER (2) Port mode register 2 (PM2) This register sets the input/output of port 2 in 1-bit units. To use the P24/TO20/INTP1/TO80 pin for timer output, set the output latch of PM24 and P24 to 0. PM2 is set with a 1-bit or 8-bit memory manipulation instruction.
Page 110: 16-Bit Timer Counter Operation
CHAPTER 8 16-BIT TIMER COUNTER 8.4 16-Bit Timer Counter Operation 8.4.1 Operation as timer interrupt In the timer interrupt function, interrupts are repeatedly generated at the count value set to 16-bit compare register 20 (CR20) in advance based on the intervals of the value set in TCL201 and TCL200. To operate the 16-bit timer counter as a timer interrupt, the following settings are required.
Page 111 CHAPTER 8 16-BIT TIMER COUNTER Figure 8-5. Timing of Timer Interrupt Operation Count clock TM20 count value 0000H 0001H FFFFH 0000H 0001H FFFFH CR20 INTTM20 Interrupt accept Interrupt accept TO20 TOF20 Overflow flag set Remark N = 0000H to FFFFH User’s Manual U13045EJ2V0UM00...
Page 112: Operation As Timer Output
CHAPTER 8 16-BIT TIMER COUNTER 8.4.2 Operation as timer output Timer outputs are repeatedly generated at the count value set to 16-bit compare register 20 (CR20) in advance based on the intervals of the value set in TCL201 and TCL200. To operate the 16-bit timer counter as a timer output, the following settings are required.
Page 113: Capture Operation
CHAPTER 8 16-BIT TIMER COUNTER 8.4.3 Capture operation The capture operation functions to capture and latch the count value of 16-bit timer register 20 (TM20) in synchronization with a capture trigger. Set as shown in Figure 8-8 to allow 16-bit timer counter 20 to start the capture operation. Figure 8-8.
Page 114: 16-Bit Timer Register 20 Readout
CHAPTER 8 16-BIT TIMER COUNTER 8.4.4 16-bit timer register 20 readout The count value of 16-bit timer register 20 (TM20) is read out by a 16-bit manipulation instruction. TM20 readout is performed through a counter read buffer. The counter read buffer latches the TM20 count value. Buffer operation is then held pending at the CPU clock falling edge after the read signal of the TM20 lower byte rises and the count value is retained.
Page 115: Chapter 9 8-Bit Timer/Event Counter
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.1 Functions of 8-Bit Timer/Event Counter 8-bit timer/event counter 80 (TM80) has the following functions: • Interval timer • External event counter • Square wave output • PWM output (1) 8-bit interval timer When the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at an arbitrary time interval set in advance.
Page 116: 8-Bit Timer/Event Counter Configuration
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.2 8-Bit Timer/Event Counter Configuration 8-bit timer/event counter 80 consists of the following hardware. Table 9-3. 8-Bit Timer/Event Counter 80 Configuration Item Configuration 8 bits × 1 (TM80) Timer register Compare register: 8 bits × 1 (CR80) Register Timer output 1 (TO80)
Page 117 CHAPTER 9 8-BIT TIMER/EVENT COUNTER Figure 9-1. Block Diagram of 8-Bit Timer/Event Counter 80 Internal bus 8-bit compare register 80 (CR80) Match INTTM80 TO20 Note output Clear 8-bit timer counter 80 (TM80) TI80/P25/ INTP2 TO80/P24/ INTP1/TO20 P24 output TCE80 PWME80 TCL801 TCL800 TOE80 PM24 latch...
Page 118: 8-Bit Timer/Event Counter Control Registers
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.3 8-Bit Timer/Event Counter Control Registers The following two types of registers are used to control the 8-bit timer/event counter. • 8-bit timer mode control register 80 (TMC80) • Port mode register 2 (PM2) (1) 8-bit timer mode control register 80 (TMC80) This register enables/stops operation of 8-bit timer register 80 (TM80), sets the counter clock of TM80, and controls the operation of the output control circuit of 8-bit timer/event counter 80.
Page 119 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (2) Port mode register 2 (PM2) This register sets port 2 to input/output in 1-bit units. When using the P24/TO80/INTP1/TO20 pin for timer output, set the output latch of PM24 and P24 to 0. PM2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM2 to FFH.
Page 120: Operation Of 8-Bit Timer/Event Counter
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.4 Operation of 8-Bit Timer/Event Counter 9.4.1 Operation as interval timer The interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit compare register 80 (CR80) in advance. To operate the 8-bit timer/event counter as an interval timer, the following settings are required.
Page 121 CHAPTER 9 8-BIT TIMER/EVENT COUNTER Figure 9-4. Interval Timer Operation Timing Count clock TM80 count value Clear Clear CR80 TCE80 Count start INTTM80 Interrupt accept Interrupt accept TO80 Interval time Interval time Interval time Remark Interval time = (N + 1) × t : N = 00H to FFH User’s Manual U13045EJ2V0UM00...
Page 122: Operation As External Event Counter
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.4.2 Operation as external event counter The external event counter counts the number of external clock pulses input to the TI80/P25/INTP2 pin by using timer register 80 (TM80). To operate the 8-bit timer/event counter as an external event counter, the following settings are required. <1>...
Page 123: Operation As Square Wave Output
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.4.3 Operation as square wave output The 8-bit timer/event counter can generate output square waves of a given frequency at intervals specified by the count value set to the 8-bit compare register 80 (CR80) in advance. To operate the 8-bit timer/event counter 80 for square wave output, the following settings are required.
Page 124 CHAPTER 9 8-BIT TIMER/EVENT COUNTER Figure 9-6. Square Wave Output Timing Count clock TM80 count value Clear Clear CR80 TCE80 Count start INTTM80 Interrupt accept Interrupt accept Note TO80 Note The initial value of TO80 during output enable (TOE80 = 1) becomes low level. User’s Manual U13045EJ2V0UM00...
Page 125: Operation As Pwm Output
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.4.4 Operation as PWM output PWM output enables interrupt generation repeatedly at intervals specified by the count value set to 8-bit compare register 80 (CR80) in advance. To use 8-bit timer/counter 80 for PWM output, the following settings are required. <1>...
Page 126 CHAPTER 9 8-BIT TIMER/EVENT COUNTER Figure 9-7. PWM Output Timing Count clock TM80 FFH 00H 01H 02H M M + 1 M + 2 FFH 00H 01H • • • • • • • • • • • • • • • •...
Page 127: Notes On Using 8-Bit Timer/Event Counter
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.5 Notes on Using 8-Bit Timer/Event Counter (1) Error on starting timer An error of up to 1 clock occurs after the timer has been started until a coincidence signal is generated. This is because 8-bit timer register 80 (TM80) is started in asynchronization with the count pulse. Figure 9-8.
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Page 129: Chapter 10 Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.1 Functions of Watchdog Timer The watchdog timer has the following functions: • Watchdog timer • Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). (1) Watchdog timer The watchdog timer is used to detect program runaway.
Page 130: Configuration Of Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.2 Configuration of Watchdog Timer The watchdog timer consists of the following hardware: Table 10-3. Configuration of Watchdog Timer Item Configuration Control register Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) Figure 10-1. Block Diagram of Watchdog Timer Internal bus TMMK4 Prescaler...
Page 131: Watchdog Timer Control Register
CHAPTER 10 WATCHDOG TIMER 10.3 Watchdog Timer Control Register The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock.
Page 132 CHAPTER 10 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 10-3.
Page 133: Operation Of Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.4 Operation of Watchdog Timer 10.4.1 Operation as watchdog timer The watchdog timer operates to detect a runaway when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (runaway detection time interval) of the watchdog timer can be selected by bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2).
Page 134: Operation As Interval Timer
CHAPTER 10 WATCHDOG TIMER 10.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of watchdog timer mode register (WDTM) are set to 1, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time intervals specified by a count value set in advance.
Page 135: Chapter 11 8-Bit A/D Converter ( Μ Pd789104, 789124 Subseries)
CHAPTER 11 8-BIT A/D CONVERTER ( µ PD789104, 789124 SUBSERIES) 11.1 8-Bit A/D Converter Functions The 8-bit A/D converter is an 8-bit resolution converter to convert analog input to digital signals. This converter can control up to four channels of analog inputs (ANI0 to ANI3). A/D conversion can only be started by software.
Page 136 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD789104, 789124 SUBSERIES) Figure 11-1. Block Diagram of 8-Bit A/D Converter P-ch Sample and hold circuit ANI0/P60 Voltage comparator ANI1/P61 ANI2/P62 ANI3/P63 Successive approximation register (AR) Control INTAD0 circuit A/D conversion result register 0 (ADCR0) ADS01 ADS00 ADCS0 FR02 FR01...
Page 137 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD789104, 789124 SUBSERIES) (5) Series resistor string The series resistor string is configured between AV and AV . It generates the reference voltages against which analog inputs are compared. (6) ANI0 to ANI3 pins Pins ANI0 to ANI3 are the 4-channel analog input pins for the A/D converter.
Page 138: Registers Controlling 8-Bit A/D Converter
CHAPTER 11 8-BIT A/D CONVERTER ( µ PD789104, 789124 SUBSERIES) 11.3 Registers Controlling 8-Bit A/D Converter The following two registers are used to control the 8-bit A/D converter. • A/D converter mode register 0 (ADM0) • A/D input select register 0 (ADS0) (1) A/D converter mode register 0 (ADM0) ADM0 specifies the conversion time for analog inputs.
Page 139 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD789104, 789124 SUBSERIES) (2) A/D input select register 0 (ADS0) The ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal. ADS0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADS0 to 00H.
Page 140: 8-Bit A/D Converter Operation
CHAPTER 11 8-BIT A/D CONVERTER ( µ PD789104, 789124 SUBSERIES) 11.4 8-Bit A/D Converter Operation 11.4.1 Basic operation of 8-bit A/D converter <1> Select a channel for A/D conversion, using A/D input select register 0 (ADS0). <2> The voltage supplied to the selected analog input channel is sampled using the sample and hold circuit. <3>...
Page 141: Input Voltage And Conversion Result
CHAPTER 11 8-BIT A/D CONVERTER ( µ PD789104, 789124 SUBSERIES) Figure 11-4. Basic Operation of 8-Bit A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined or 40H result Conversion ADCR0 result INTAD0 A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software. If an attempt is made to write to ADM0 or A/D input select register 0 (ADS0) during A/D conversion, the ongoing A/D conversion is canceled.
Page 142 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD789104, 789124 SUBSERIES) Figure 11-5. Relationships between Analog Input Voltage and A/D Conversion Result A/D conversion result (ADCR0) Input voltage/AV User’s Manual U13045EJ2V0UM00...
Page 143: Operation Mode Of 8-Bit A/D Converter
CHAPTER 11 8-BIT A/D CONVERTER ( µ PD789104, 789124 SUBSERIES) 11.4.3 Operation mode of 8-bit A/D converter The 8-bit A/D converter is initially in the select mode. In this mode, A/D input selection register 0 (ADS0) is used to select an analog input channel from ANI0 to ANI3 for A/D conversion. A/D conversion can only be started by software, that is, by setting A/D converter mode register 0 (ADM0).
Page 144: Cautions Related To 8-Bit A/D Converter
CHAPTER 11 8-BIT A/D CONVERTER ( µ PD789104, 789124 SUBSERIES) 11.5 Cautions Related to 8-Bit A/D Converter (1) Current consumption in the standby mode When the A/D converter enters the standby mode, it stops its operation. Stopping conversion (bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) = 0) can reduce the current consumption.
Page 145 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD789104, 789124 SUBSERIES) (4) Conversion results immediately following start of A/D conversion The first A/D conversion value immediately following the start of A/D converter operation may be undefined. Be sure to poll the A/D conversion end interrupt request (INTAD0) and perform processing such as annulling the first conversion result.
Page 146 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD789104, 789124 SUBSERIES) (6) Noise prevention To maintain a resolution of 8 bits, watch for noise to the AV and ANI0 to ANI3 pins. The higher the output impedance of the analog input source is, the larger the effect by noise. To reduce noise, attach an external capacitor to the relevant pins as shown in Figure 11-8.
Page 147 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD789104, 789124 SUBSERIES) Figure 11-11. A/D Conversion End Interrupt Request Generation Timing Rewriting to ADM0 Rewriting to ADM0 (to begin conversion (to begin conversion ADIF0 has been set, but conversion for ANIn) for ANIm) for ANIm has not been completed.
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Page 149: Chapter 12 10-Bit A/D Converter ( Μ Pd789114, 789134 Subseries)
CHAPTER 12 10-BIT A/D CONVERTER ( µ PD789114, 789134 SUBSERIES) 12.1 10-Bit A/D Converter Functions The 10-bit A/D converter is a 10-bit resolution converter to convert an analog input to digital signals. This converter can control up to four channels of analog inputs (ANI0 to ANI3). A/D conversion can only be started by software.
Page 150 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD789114, 789134 SUBSERIES) Figure 12-1. Block Diagram of 10-Bit A/D Converter P-ch Sample and hold circuit ANI0/P60 Voltage comparator ANI1/P61 ANI2/P62 ANI3/P63 Successive approximation register (SAR) Control INTAD0 circuit A/D conversion result register 0 (ADCR0) ADS01 ADS00 ADCS0 FR02 FR01...
Page 151 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD789114, 789134 SUBSERIES) (3) Sample and hold circuit The sample-and-hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. The sampled analog input voltage is held during A/D conversion. (4) Voltage comparator The voltage comparator compares an analog input with the voltage output by the series resistor string.
Page 152: Registers Controlling 10-Bit A/D Converter
CHAPTER 12 10-BIT A/D CONVERTER ( µ PD789114, 789134 SUBSERIES) 12.3 Registers Controlling 10-Bit A/D Converter The following two registers are used to control the 10-bit A/D converter. • A/D converter mode register 0 (ADM0) • A/D input select register 0 (ADS0) (1) A/D converter mode register 0 (ADM0) ADM0 specifies the conversion time for analog inputs.
Page 153 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD789114, 789134 SUBSERIES) (2) A/D input select register 0 (ADS0) The ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal. ADS0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADS0 to 00H.
Page 154: 10-Bit A/D Converter Operation
CHAPTER 12 10-BIT A/D CONVERTER ( µ PD789114, 789134 SUBSERIES) 12.4 10-Bit A/D Converter Operation 12.4.1 Basic operation of 10-bit A/D converter <1> Select a channel for A/D conversion, using A/D input select register 0 (ADS0). <2> The voltage supplied to the selected analog input channel is sampled using the sample and hold circuit. <3>...
Page 155: Input Voltage And Conversion Result
CHAPTER 12 10-BIT A/D CONVERTER ( µ PD789114, 789134 SUBSERIES) Figure 12-4. Basic Operation of 10-Bit A/D Converter Conversion time Sampling time A/D converter A/D conversion Sampling operation Conversion Undefined result Conversion ADCR0 result INTAD0 A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software. If an attempt is made to write to ADM0 or A/D input select register 0 (ADS0) during A/D conversion, the ongoing A/D conversion is canceled.
Page 156 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD789114, 789134 SUBSERIES) Figure 12-5. Relationships between Analog Input Voltage and A/D Conversion Result 1,023 1,022 1,021 A/D conversion result (ADCR0) 2,043 1,022 2,045 1,023 2,047 2,048 1,024 2,048 1,024 2,048 1,024 2,048 1,024 2,048 1,024...
Page 157: Operation Mode Of 10-Bit A/D Converter
CHAPTER 12 10-BIT A/D CONVERTER ( µ PD789114, 789134 SUBSERIES) 12.4.3 Operation mode of 10-bit A/D converter The 10-bit A/D converter is initially in the select mode. In this mode, A/D input select register 0 (ADS0) is used to select an analog input channel from ANI0 to ANI3 for A/D conversion. A/D conversion can be started only by software, that is, by setting A/D converter mode register 0 (ADM0).
Page 158: Cautions Related To 10-Bit A/D Converter
CHAPTER 12 10-BIT A/D CONVERTER ( µ PD789114, 789134 SUBSERIES) 12.5 Cautions Related to 10-Bit A/D Converter (1) Current consumption in the standby mode When the A/D converter enters the standby mode, it stops its operation. Stopping conversion (bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) = 0) can reduce the current consumption.
Page 159 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD789114, 789134 SUBSERIES) (4) Conversion results immediately following start of A/D conversion The first A/D conversion value immediately following the start of A/D converter operation may be undefined. Be sure to poll the A/D conversion end interrupt request (INTAD0) and perform processing such as annulling the first conversion result.
Page 160 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD789114, 789134 SUBSERIES) (6) Noise prevention To maintain a resolution of 10 bits, watch for noise to the AV and ANI0 to ANI3 pins. The higher the output impedance of the analog input source is, the larger the effect by noise is. To reduce noise, attach an external capacitor to the relevant pins as shown in Figure 12-10.
Page 161 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD789114, 789134 SUBSERIES) Figure 12-11. A/D Conversion End Interrupt Request Generation Timing Rewriting to ADM0 Rewriting to ADM0 (to begin conversion (to begin conversion ADIF0 has been set, but conversion for ANIn) for ANIm) for ANIm has not been completed.
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Page 163: Chapter 13 Serial Interface 20
CHAPTER 13 SERIAL INTERFACE 20 13.1 Functions of Serial Interface 20 Serial interface 20 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not performed. Power consumption is minimized in this mode. (2) Asynchronous serial interface (UART) mode This mode is used to send and receive the one byte of data that follows a start bit.
Page 164 Figure 13-1. Serial Interface 20 Block Diagram Internal bus Serial operation mode Asynchronous serial Asynchronous serial register 20 (CSIM20) interface status register 20 interface mode register 20 (ASIS20) (ASIM20) Receive buffer CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 PE20 FE20 OVE20 TXE20 RXE20 PS201 PS200 CL20 SL20 register 20 (RXB20) Switching of the first bit...
Page 165 Figure 13-2. Baud Rate Generator Block Diagram Reception detection clock Transmission Transmission shift clock clock counter Reception shift clock Reception clock counter TXE20 SCK20/ASCK20/P20 RXE20 CSIE20 Reception detection TPS203 TPS202 TPS201 TPS200 Baud rate generator control register 20 (BRGC20) Internal bus...
Page 166 CHAPTER 13 SERIAL INTERFACE 20 (1) Transmit shift register 20 (TXS20) TXS20 is a register in which transmission data is prepared. The transmission data is output from TXS20 bit- serially. When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmission data. Writing data to TXS20 triggers transmission.
Page 167: Serial Interface 20 Control Registers
CHAPTER 13 SERIAL INTERFACE 20 13.3 Serial Interface 20 Control Registers Serial interface 20 is controlled by the following four registers. • Serial operating mode register 20 (CSIM20) • Asynchronous serial interface mode register 20 (ASIM20) • Asynchronous serial interface status register 20 (ASIS20) •...
Page 168 CHAPTER 13 SERIAL INTERFACE 20 (2) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is used to make the settings related to asynchronous serial interface mode. ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. Figure 13-4.
Page 169 CHAPTER 13 SERIAL INTERFACE 20 Table 13-2. Serial Interface 20 Operating Mode Settings (1) Operation stopped mode ASIM20 CSIM20 PM22 P21 PM21 P21 PM20 P20 First Shift P22/SI20/RxD20 P21/SO20/TxD20 P20/SCK20/ Clock Pin Function Pin Function ASCK20 Pin TXE20 RXE20 CSIE20 DIR20 CSCK20 Function ×...
Page 170 CHAPTER 13 SERIAL INTERFACE 20 (3) Asynchronous serial interface status register 20 (ASIS20) ASIS20 is used to display the type of a reception error, if it occurs while asynchronous serial interface mode is set. ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction. The contents of ASIS20 are undefined in 3-wire serial I/O mode.
Page 171 CHAPTER 13 SERIAL INTERFACE 20 (4) Baud rate generator control register 20 (BRGC20) BRGC20 is used to specify the serial clock for serial interface. BRGC20 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC20 to 00H. Figure 13-6. Baud Rate Generator Control Register 20 Format Symbol Address After reset...
Page 172 CHAPTER 13 SERIAL INTERFACE 20 The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input from the ASCK20 pin. (a) Generation of baud rate transmit/receive clock by means of system clock The transmit/receive clock is generated by scaling the system clock.
Page 173 CHAPTER 13 SERIAL INTERFACE 20 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK20 pin The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud rate generated from the clock input from the ASCK20 pin is estimated by using the following expression. ASCK [Baud rate] = [Hz]...
Page 174: Serial Interface 20 Operation
CHAPTER 13 SERIAL INTERFACE 20 13.4 Serial Interface 20 Operation Serial interface 20 provides the following three types of modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 13.4.1 Operation stop mode In the operation stop mode, serial transfer is not executed, therefore, the power consumption can be reduced. The P20/SCK20/ASCK20, P21/SO20/TxD20, and P22/SI20/RxD20 pins can be used as normal I/O ports.
Page 175 CHAPTER 13 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. Symbol Address After reset <7> <6> ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20 FF70H TXE20 Transmit operation control...
Page 176: Asynchronous Serial Interface (Uart) Mode
CHAPTER 13 SERIAL INTERFACE 20 13.4.2 Asynchronous serial interface (UART) mode In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communication is possible. This device incorporates a UART-dedicated baud rate generator that enables communication at the desired transfer rate from many options.
Page 177 CHAPTER 13 SERIAL INTERFACE 20 (a) Serial operating mode register 20 (CSIM20) CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM20 to 00H. Set 00H to CSIM20 when UART mode is selected. Symbol <7> Address After reset CSIM20...
Page 178 CHAPTER 13 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. Symbol <7> <6> Address After reset ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20 FF70H TXE20 Transmit operation control...
Page 179 CHAPTER 13 SERIAL INTERFACE 20 (c) Asynchronous serial interface status register 20 (ASIS20) ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIS20 to 00H. Symbol Address After reset ASIS20 PE20 FE20 OVE20 FF71H PE20 Parity error flag Parity error not generated Parity error generated (when the parity of transmit data does not match.)
Page 180 CHAPTER 13 SERIAL INTERFACE 20 (d) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC20 to 00H. Address After reset Symbol BRGC20 TPS203 TPS202 TPS201 TPS200 FF73H TPS203 TPS202 TPS201 TPS200 3-bit counter source clock selection...
Page 181 CHAPTER 13 SERIAL INTERFACE 20 The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input from the ASCK20 pin. (i) Generation of baud rate transmit/receive clock by means of system clock The transmit/receive clock is generated by scaling the system clock.
Page 182 CHAPTER 13 SERIAL INTERFACE 20 (ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK20 pin The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud rate generated from the clock input from the ASCK20 pin is estimated by using the following expression.
Page 183 CHAPTER 13 SERIAL INTERFACE 20 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 13-7. One data frame consists of a start bit, character bits, parity bit and stop bit(s). The specification of character bit length, parity selection, and specification of stop bit length for each data frame is carried out using asynchronous serial interface mode register 20 (ASIM20).
Page 184 CHAPTER 13 SERIAL INTERFACE 20 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected.
Page 185 CHAPTER 13 SERIAL INTERFACE 20 (c) Transmission A transmit operation is started by writing transmit data to transmit shift register 20 (TXS20). The start bit, parity bit and stop bit are added automatically. When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, a transmission completion interrupt (INTST20) is generated.
Page 186 CHAPTER 13 SERIAL INTERFACE 20 (d) Reception When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set (1), a receive operation is enabled and sampling of the RxD20 pin input is performed. RxD20 pin input sampling is performed using the serial clock specified by ASIM20. When the RxD20 pin input becomes low, the 3-bit counter starts counting, and when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output.
Page 187 CHAPTER 13 SERIAL INTERFACE 20 (e) Receive errors The following three errors may occur during a receive operation: a parity error, framing error, or overrun error. The data reception result error flag is set in asynchronous serial interface status register 20 (ASIS20).
Page 188 CHAPTER 13 SERIAL INTERFACE 20 (3) UART mode cautions (a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during transmission, be sure to set transmit shift register 20 (TXS20) to FFH, then set TXE20 to 1 before executing the next transmission.
Page 189: 3-Wire Serial I/O Mode
CHAPTER 13 SERIAL INTERFACE 20 13.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc. that incorporate a conventional synchronous clocked serial interface, such as the 75XL Series, 78K Series, 17K Series, etc. Communication is performed using three lines: the serial clock (SCK20), serial output (SO20), and serial input (SI20).
Page 190 CHAPTER 13 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. When the 3-wire serial I/O mode is selected, 00H must be set to ASIM20. Symbol <7>...
Page 191 CHAPTER 13 SERIAL INTERFACE 20 (c) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC20 to 00H. Address After reset Symbol BRGC20 TPS203 TPS202 TPS201 TPS200 FF73H TPS203 TPS202 TPS201 TPS200 3-bit counter source clock selection...
Page 192 CHAPTER 13 SERIAL INTERFACE 20 (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit in synchronization with the serial clock. The transmit shift register (TXS20/SIO20) and receive shift register (RXS20) shift operations are performed in synchronization with the fall of the serial clock (SCK20).
Page 193 CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (2/7) (ii) Slave operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0) SIO20 Write SCK20 SI20 Note SO20 INTCSI20 Note The value of the last bit previously output is output. (iii) Slave operation (when DAP20 = 0, CKP20 = 0, SSE20 = 1) SS20 SIO20...
Page 194 CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (3/7) (iv) Master operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0) SIO20 Write SCK20 SO20 SI20 INTCSI20 (v) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 Write SCK20...
Page 195 CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (4/7) (vi) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 1) SS20 SIO20 Write SCK20 Note 1 SIO20 Write (master) SI20 Hi-Z Hi-Z Note 2 SO20 INTCSI20 Notes...
Page 196 CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (5/7) (viii) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0) SIO20 Write SCK20 Note SIO20 Write (master) SI20 SO20 INTCSI20 Note The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the first bit before the first falling of SCK20.
Page 197 CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (6/7) (x) Master operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 Write SCK20 SO20 Note DOI4 SI20 INTCSI20 Note The value of the last bit previously output is output. (xi) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 Write...
Page 198 CHAPTER 13 SERIAL INTERFACE 20 Figure 13-11. 3-Wire Serial I/O Mode Timing (7/7) (xii) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 1) SS20 SIO20 Write SCK20 SI20 Hi-Z Hi-Z Note 1 Note 2 SO20 INTCSI20 Notes 1.
Page 199: Chapter 14 Multiplier
CHAPTER 14 MULTIPLIER 14.1 Multiplier Function The multiplier has the following function: • Calculation of 8 bits × 8 bits = 16 bits 14.2 Multiplier Configuration (1) 16-bit multiplication result storage register 0 (MUL0) This register stores the 16-bit result of multiplication. This register holds the result of multiplication after 16 CPU clocks have elapsed.
Page 200 CHAPTER 14 MULTIPLIER Figure 14-1. Block Diagram of Multiplier Internal bus Multiplication data Multiplication data register A (MRA0) register B (MRB0) Counter value CPU clock Selector 3-bit counter Start Clear 16-bit adder 16-bit multiplication result storage register 0 (Master) (MUL0) 16-bit multiplication result storage register 0 (Slave) Reset...
Page 201: Multiplier Control Register
CHAPTER 14 MULTIPLIER 14.3 Multiplier Control Register The multiplier is controlled by the following register: • Multiplier control register (MULC0) MULC0 indicates the operating status of the multiplier after operation, as well as controls the multiplier. MULC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 202: Multiplier Operation
CHAPTER 14 MULTIPLIER 14.4 Multiplier Operation The multiplier of the µ PD789134 Subseries can execute the calculation of 8 bits × 8 bits = 16 bits. Figure 14-3 shows the operation timing of the multiplier where MRA0 is set to AAH and MRB0 is set to D3H. <1>...
Page 203: Chapter 15 Interrupt Functions
CHAPTER 15 INTERRUPT FUNCTIONS 15.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated.
Page 204 CHAPTER 15 INTERRUPT FUNCTIONS Table 15-1. Interrupt Source List Interrupt Type Priority Note 1 Internal Vector Basic Interrupt Source /External Table Configuration Name Trigger Note 2 Address Type Non-maskable — INTWDT Watchdog timer overflow (watchdog timer Internal 0004H mode 1 selected) Maskable INTWDT Watchdog timer overflow (interval timer...
Page 205 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal bus Vector table Interrupt request address generator Standby release signal (B) Internal maskable interrupt Internal bus Vector table address generator Interrupt request Standby release signal (C) External maskable interrupt Internal bus External interrupt mode...
Page 206: Interrupt Function Control Registers
CHAPTER 15 INTERRUPT FUNCTIONS 15.3 Interrupt Function Control Registers The following four registers are used to control the interrupt functions. • Interrupt request flag registers (IF0, IF1) • Interrupt mask flag registers (MK0, MK1) • External interrupt mode register (INTM0) •...
Page 207 CHAPTER 15 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0, IF1) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgement of an interrupt request or upon RESET input.
Page 208 CHAPTER 15 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0, MK1) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. Figure 15-3.
Page 209 CHAPTER 15 INTERRUPT FUNCTIONS (3) External interrupt mode register 0 (INTM0) This register is used to set the valid edge of INTP0 to INTP2. INTM0 is set with an 8-bit memory manipulation instruction. RESET input clears INTM0 to 00H. Figure 15-4. External Interrupt Mode Register 0 Format Address After reset Symbol...
Page 210 CHAPTER 15 INTERRUPT FUNCTIONS (4) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped. This register can be read/written in 8-bit units and can carry out operations using a bit manipulation and dedicated instructions (EI, DI).
Page 211: Interrupt Processing Operation
CHAPTER 15 INTERRUPT FUNCTIONS 15.4 Interrupt Processing Operation 15.4.1 Non-maskable interrupt request acknowledgement operation The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Page 212 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-6. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgement Start WDTM4 = 1 (watchdog timer mode is selected) Interval timer overflows WDTM3 = 0 (non-maskable interrupt is selected) Reset processing Interrupt request is generated Interrupt processing is started WDTM: Watchdog timer mode register WDT: Watchdog timer...
Page 213: Maskable Interrupt Request Acknowledgement Operation
CHAPTER 15 INTERRUPT FUNCTIONS 15.4.2 Maskable interrupt request acknowledgement operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt enabled status (when the IE flag is set to 1).
Page 214 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-9. Interrupt Acknowledgement Program Algorithm Start ××IF = 1 ? Yes (Interrupt request generated) ××MK = 0 ? Interrupt request pending IE = 1 ? Interrupt request pending Vectored interrupt processing ××IF: Interrupt request flag ××MK: Interrupt mask flag Flag to control maskable interrupt request acknowledgement (1 = enable, 0 = disable)
Page 215: Multiple Interrupt Processing
CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-10. Interrupt Request Acknowledgement Timing (Example of MOV A,r) 8 clocks Clock Save PSW and PC, jump Interrupt processing program MOV A,r to interrupt processing Interrupt If an interrupt request flag (××IF) is set before an instruction clock n (n = 4 to 10) under execution becomes n– 1, the interrupt is acknowledged after the instruction under execution is complete.
Page 216 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-12. Example of Multiple Interrupts Example 1. Multiple interrupts are acknowledged INTxx processing INTyy processing Main processing IE = 0 IE = 0 INTxx INTyy RETI RETI During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and a multiple interrupt is generated. An EI instruction is issued before each interrupt request acknowledgement, and the interrupt request acknowledgement enable state is set.
Page 217: Interrupt Request Reserve
CHAPTER 15 INTERRUPT FUNCTIONS 15.4.4 Interrupt request reserve Some instructions may reserve the acknowledgement of an instruction request until the completion of the execution of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external interrupt) is generated during the execution.
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Page 219: Chapter 16 Standby Function
CHAPTER 16 STANDBY FUNCTION 16.1 Standby Function and Configuration 16.1.1 Standby function The standby function is to reduce the power consumption of the system and can be effected in the following two modes: (1) HALT mode This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the CPU.
Page 220: Standby Function Control Register ( Μ Pd789104, 789114 Subseries)
CHAPTER 16 STANDBY FUNCTION 16.1.2 Standby function control register ( µ PD789104, 789114 Subseries) The wait time after the STOP mode is released upon interrupt request until the oscillation stabilizes is controlled Note with the oscillation stabilization time select register (OSTS) OSTS is set with an 8-bit memory manipulation instruction.
Page 221: Operation Of Standby Function
CHAPTER 16 STANDBY FUNCTION 16.2 Operation of Standby Function 16.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operation status in the HALT mode is shown in the following table. Table 16-1. HALT Mode Operating Status Item HALT Mode Operating Status Clock generator...
Page 222 CHAPTER 16 STANDBY FUNCTION (2) Releasing HALT mode The HALT mode can be released by the following three types of sources: (a) Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt request is able to be acknowledged, vectored interrupt processing is performed.
Page 223 CHAPTER 16 STANDBY FUNCTION (c) Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 16-3.
Page 224: Stop Mode
CHAPTER 16 STANDBY FUNCTION 16.2.2 STOP mode (1) Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction. Cautions 1. When the STOP mode is set, the X2 or CL2 pin is internally pulled up to V to suppress the current leakage of the oscillation circuit block.
Page 225 CHAPTER 16 STANDBY FUNCTION (2) Releasing STOP mode The STOP mode can be released by the following two types of sources: (a) Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is able to be acknowledged, vectored interrupt processing is performed, after the oscillation stabilization time has elapsed.
Page 226 CHAPTER 16 STANDBY FUNCTION (b) Releasing by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 16-5. Releasing STOP Mode by RESET Input STOP Note Wait instruction...
Page 227: Chapter 17 Reset Function
CHAPTER 17 RESET FUNCTION The following two operations are available to generate reset signals. External reset input with RESET pin Internal reset by program runaway time detection with watchdog timer External and internal reset have no functional differences. In both cases, program execution starts at the addresses 0000H and 0001H by reset signal input.
Page 228 CHAPTER 17 RESET FUNCTION Figure 17-2. Reset Timing by RESET Input X1, CL1 Reset period Oscillation During normal Normal operation (oscillation stabilization operation (reset processing) stops) time wait RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 17-3. Reset Timing by Overflow in Watchdog Timer X1, CL1 Reset period Oscillation...
Page 229 CHAPTER 17 RESET FUNCTION Table 17-1. Hardware Status after Reset (1/2) Hardware Status after Reset Note 1 Program counter (PC) The contents of reset vector tables (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2...
Page 230 CHAPTER 17 RESET FUNCTION Table 17-1. Hardware Status after Reset (2/2) Hardware Status after Reset Multiplier 16-bit multiplication result storage register (MUL0) Undefined Data register A (MRA0) Undefined Data register B (MRB0) Undefined Control register (MULC0) Interrupt Request flag register (IF0, IF1) Mask flag register (MK0, MK1) External interrupt mode register (INTM0) User’s Manual U13045EJ2V0UM00...
Page 231: Chapter 18 Μ Pd78F9116, 78F9136
CHAPTER 18 µ PD78F9116, 78F9136 The µ PD78F9116 is a version with flash memory instead of the internal ROM of the mask ROM version in the µ PD789104 and 789114 Subseries. The µ PD78F9136 is a version with flash memory instead of the internal ROM of the mask ROM version in the µ...
Page 232: Flash Memory Programming
CHAPTER 18 µ PD78F9116, 78F9136 18.1 Flash Memory Programming The on-chip program memory in the µ PD78F9116, 78F9136 is flash memory. The flash memory can be written with the µ PD78F9116 mounted on the target system (on-board). Connect the dedicated flash programmer (Flashpro III (part number: FL-PR3, PG-FP3)) to the host machine and target system to write the flash memory.
Page 233: Function Of Flash Memory Programming
CHAPTER 18 µ PD78F9116, 78F9136 18.1.2 Function of flash memory programming By transmitting/receiving commands and data in the selected communication mode, operations such as writing to the flash memory are performed. Table 18-3 shows the major functions of flash memory programming. Table 18-3.
Page 234 CHAPTER 18 µ PD78F9116, 78F9136 Figure 18-3. Flashpro III Connection in UART Mode µ Flashpro III PD78F9116 Note , AV RESET RESET RxD20 TxD20 , AV Note n = 1, 2 Figure 18-4. Flashpro III Connection in Pseudo 3-Wire Mode (When P0 Is Used) µ...
Page 235 CHAPTER 18 µ PD78F9116, 78F9136 (b) Connection between µ PD78F9136 and Flashpro III Figure 18-5. Flashpro III Connection in 3-Wire Serial I/O Mode µ Flashpro III PD78F9136 Note , AV RESET RESET SCK20 SI20 SO20 , AV Note n = 1, 2 Figure 18-6.
Page 236 CHAPTER 18 µ PD78F9116, 78F9136 Figure 18-7. Flashpro III Connection in Pseudo 3-Wire Mode (When P0 Is Used) µ Flashpro III PD78F9136 Note , AV RESET RESET P00 (Serial clock) P02 (Serial input) P01 (Serial output) , AV Note n = 1, 2 User’s Manual U13045EJ2V0UM00...
Page 237: Example Of Settings For Flashpro Iii (Pg-Fp3)
CHAPTER 18 µ PD78F9116, 78F9136 18.1.4 Example of settings for Flashpro III (PG-FP3) Make the following setting when writing to flash memory using Flashpro III (PG-FP3). <1> Load the parameter file. <2> Select serial mode and serial clock using the type command. <3>...
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Page 239: Chapter 19 Mask Option (Mask Rom Version)
CHAPTER 19 MASK OPTION (MASK ROM VERSION) Table 19-1. Selection of Mask Option for Pins Mask Option P50 to P53 On-chip pull-up resistor can be specified in 1-bit units. For P50 to P53 (port 5), an on-chip pull-up resistor can be specified by the mask option. The mask option is specified in 1-bit units.
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Page 241: Chapter 20 Instruction Set
CHAPTER 20 INSTRUCTION SET This chapter lists the instruction set of the µ PD789134 Subseries. For the details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series User’s Manual Instruction (U11047E). 20.1 Operation 20.1.1 Operand identifiers and description methods Operands are described in “Operand”...
Page 242: Description Of "Operation" Column
CHAPTER 20 INSTRUCTION SET 20.1.2 Description of “operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 243: Operation List
CHAPTER 20 INSTRUCTION SET 20.2 Operation List Flag Mnemonic Operands Byte Clock Operation Z AC CY r ← byte r,#byte (saddr) ← byte saddr,#byte sfr ← byte sfr,#byte A ← r Note 1 r ← A Note 1 A ← (saddr) A,saddr (saddr) ←...
Page 244 CHAPTER 20 INSTRUCTION SET Flag Mnemonic Operands Byte Clock Operation Z AC CY rp ← word MOVW rp,#word AX ← (saddrp) AX,saddrp (saddrp) ← AX saddrp,AX AX ← rp AX,rp Note rp ← AX rp,AX Note AX ↔ rp XCHW AX,rp Note A,CY ←...
Page 245 CHAPTER 20 INSTRUCTION SET Flag Mnemonic Operands Byte Clock Operation Z AC CY A,CY ← A – byte – CY × × × SUBC A,#byte (saddr),CY ← (saddr) – byte – CY × × × saddr,#byte A,CY ← A – r – CY ×...
Page 246 CHAPTER 20 INSTRUCTION SET Flag Mnemonic Operands Byte Clock Operation Z AC CY × × × A,#byte A – byte × × × saddr,#byte (saddr) – byte × × × A – r × × × A,saddr A – (saddr) ×...
Page 247 CHAPTER 20 INSTRUCTION SET Flag Mnemonic Operands Byte Clock Operation Z AC CY (SP – 1) ← (PC + 3) , (SP – 2) ← (PC + 3) CALL !addr16 PC ← addr16, SP ← SP – 2 (SP – 1) ← (PC + 1) , (SP –...
Page 248: Instructions Listed By Addressing Type
CHAPTER 20 INSTRUCTION SET 20.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte saddr !addr16 [DE] [HL] [HL+byte] $addr16 None 1st Operand Note...
Page 249 CHAPTER 20 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word Note saddrp None 1st Operand ADDW MOVW MOVW MOVW SUBW XCHW CMPW MOVW MOVW Note INCW DECW PUSH saddrp MOVW MOVW Note Only when rp = BC, DE, or HL.
Page 250 CHAPTER 20 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand !addr16 [addr5] $addr16 1st Operand Basic Instructions CALL CALLT Compound Instructions DBNZ (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP User’s Manual U13045EJ2V0UM00...
Page 251: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the µ PD789134 Subseries. Figure A-1 shows the development tool configuration. • Support of the PC98-NX Series Unless otherwise specified, the µ PD789134 Subseries supported by IBM PC/AT™ and compatibles can be used for the PC98-NX Series.
Page 252 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration Language processing software Embedded software • Assembler package • C compiler package • OS • System simulator • Device file • C compiler source file • Integrated debugger Host machine (PC or EWS) Interface adapter Flash memory write environment...
Page 253: Language Processing Software
APPENDIX A DEVELOPMENT TOOLS A.1 Language Processing Software RA78K0S A program that converts a program written in mnemonic into object codes that can Assembler package be executed by microcontrollers. In addition, automatic functions to generate symbol tables and optimize branch instructions are also provided.
Page 254: Flash Memory Writing Tools
APPENDIX A DEVELOPMENT TOOLS A.2 Flash Memory Writing Tools Flashpro III Dedicated flash programmer for microcontrollers incorporating flash memory (Part No. FL-PR3, PG-FP3) Flash programmer FA-30GS Adapter for writing to flash memory and connected to Flashpro III. FA-30MC • FA-30GS: for 30-pin plastic shrink SOP (GS type) Flash memory writing adapter •...
Page 255: Software
APPENDIX A DEVELOPMENT TOOLS A.3.2 Software Control program for debugging the 78K/0S Series. ID78K0S-NS This program provides a graphical user interface. It runs on Windows for personal computer Integrated debugger users and on OSF/Motif™ for engineering work station users, and has visual designs and (Supports in-circuit emulator operationability that comply with these operating systems.
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Page 257: Appendix B Embedded Software
APPENDIX B EMBEDDED SOFTWARE The following embedded software products are available for efficient program development and maintenance of the µ PD789134 Subseries. MX78K0S is a subset OS that is based on the µ ITRON specification. Supplied with the MX78K0S MX78K0S nucleus.
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Page 259: Appendix C Register Index
APPENDIX C REGISTER INDEX C.1 Register Name Index (Alphabetic Order) 8-bit compare register 80 (CR80) ........................ 117 8-bit timer mode control register 80 (TMC80) ..................... 118 8-bit timer register 80 (TM80) ........................117 16-bit compare register 20 (CR20) ......................106 16-bit multiplication result storage register 0 (MUL0) .................
Page 260 APPENDIX C REGISTER INDEX Port mode register 0 (PM0) ..........................83 Port mode register 1 (PM1) ..........................83 Port mode register 2 (PM2) ......................83, 109, 119 Port mode register 5 (PM5) ..........................83 Processor clock control register (PCC) ....................88, 96 Pull-up resistor option register 0 (PU0) ......................
Page 261: Register Symbol Index (Alphabetic Order)
APPENDIX C REGISTER INDEX C.2 Register Symbol Index (Alphabetic Order) ADCR0: A/D conversion result register 0 ....................136 ADM0: A/D converter mode register 0 ....................138 ADS0: A/D input select register 0 ......................139 ASIM20: Asynchronous serial interface mode register 20 ..........168, 175, 178, 190 ASIS20: Asynchronous serial interface status register 20 ..............
Page 262 APPENDIX C REGISTER INDEX RXB20: Receive buffer register 20 ......................166 TCL2: Timer clock select register 2 ...................... 131 TCP20: 16-bit timer capture register 20 ....................106 TM20: 16-bit timer register 20 ....................... 106 TM80: 8-bit timer register 80 ......................... 117 TMC20: 16-bit timer mode control register 20 ..................
Page 263: Appendix D Revision History
APPENDIX D REVISION HISTORY A history of the revisions up to this edition is shown below. “Applied to:” indicates the chapters to which the revision was applied. Edition Major Revisions from Previous Edition Applied to: Deletion of 28-pin plastic shrink DIP Throughout Addition of 30-pin plastic shrink DIP in the "in planning"...
Page 264 [MEMO] User’s Manual U13045EJ2V0UM00...
Page 265 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we’ve taken, you may Name encounter problems in the documentation.

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NEC mPD789101 User Manual

CHAPTER 1 GENERAL ( Μ PD789104, 789114 SUBSERIES)

CHAPTER 2 GENERAL ( Μ PD789124, 789134 SUBSERIES)

Chapter 3 Pin Functions

Chapter 4 Cpu Architecture

Chapter 5 Port Functions

CHAPTER 6 CLOCK GENERATOR ( Μ PD789104, 789114 SUBSERIES)

CHAPTER 7 CLOCK GENERATOR ( Μ PD789124, 789134 SUBSERIES)

Chapter 8 16-Bit Timer Counter

Chapter 9 8-Bit Timer/Event Counter

Chapter 10 Watchdog Timer

CHAPTER 11 8-BIT A/D CONVERTER ( Μ PD789104, 789124 SUBSERIES)

CHAPTER 12 10-BIT A/D CONVERTER ( Μ PD789114, 789134 SUBSERIES)

Chapter 13 Serial Interface 20

Chapter 14 Multiplier

Chapter 15 Interrupt Functions

Chapter 16 Standby Function

Chapter 17 Reset Function

CHAPTER 18 Μ PD78F9116, 78F9136

Chapter 19 Mask Option (Mask Rom Version)

Chapter 20 Instruction Set

Appendix A Development Tools

Appendix B Embedded Software

Appendix C Register Index

Appendix D Revision History

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Summary of Contents for NEC mPD789101

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