Table of Contents
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Core POST Code Table
The following table details the core POST codes and functions used in SecureCore.
POST
Code
0x00
Early Microcode update for CAR
0x01
Enable CAR
0x02
CAR Done, initial stack
0xEE
unknown CPU ID to load uCode
0xEF
unknown DT CPU to load uCode
0xnn
File count found in a volume
0x11
Debug Test driver for debug test PPI 1 (If install debugTest
driver)
0x22
Debug Test driver for debug test PPI 2 (If install debugTest
driver)
0x33
Debug Test driver for debug test PPI 3 (If install debugTest
driver)
0x44
Entry point of loadfile
0x88
Entry point of apMuLoader
0x80
A PEIM found
0x82
PEIM not dispatched yet
0x84
PEIM satisfies depex
0x86
Image loaded but fail on security
0x88
Executing a PEIM
0x8A
Processing notify event for newly installed PPI
0x8C
Handing off to next phase (DXE)
0x8F
Fail to hand off to next phase, system halt
0x90
All PEIM dispatched! Going to DxeIpl
0xCC
AP Micro-code update
0x20
S3 resume entry
0x21
Start running Boot-time bootscripts
0x22
Start running Run-time bootscripts
0x23
End of S3 resume, jump back to Waking vector
0x80
Initialize the chipset
0x81
Initialize the bridge
0x82
Initialize the CPU
0x89
Set Huge Segment
0x83
Initialize system timer
0x84
Initialize system I/O
0x88
Initialize Multi Processor
0x8A
Initialize OEM special code
0x8B
Initialize PIC and DMA
0x8C
Initialize Memory type
0x8D
Initialize Memory size
0x8F
Initialize SMM
0x90
System memory test
Chapter 4
Function
Phase
Component
CEI / SEC
Core
CEI / SEC
Core
CEI / SEC
Core
CEI / SEC
CPU
CEI / SEC
CPU
PEI
Core
PEI
Core
PEI
Core
PEI
Core
PEI
Core
PEI
Core
PEI
Core
PEI
Core
PEI
Core
PEI
Core
PEI
Core
PEI
Core
PEI
Core
PEI
Core
PEI
Core
PEI
Core
S3 resume
Core
S3 resume
Core
S3 resume
Core
S3 resume
Core
Crisis Recovery
Core
Crisis Recovery
Core
Crisis Recovery
Core
Crisis Recovery
Core
Crisis Recovery
Core
Crisis Recovery
Core
Crisis Recovery
Core
Crisis Recovery
Core
Crisis Recovery
Core
Crisis Recovery
Core
Crisis Recovery
Core
Crisis Recovery
Core
Crisis Recovery
Core
137
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