Egold - Siemens S55 Repair Documentation
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Also See for S55:
- Manual (148 pages) ,
- User manual (141 pages) ,
- Operating instructions manual (137 pages)
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5.1.3 EGOLD+
Block Diagram EGOLD+ V3.1
3
Osc.
SSC
RTC
32.768 kHz
SPI
compatible
CAPCOM
16
2 x 8 bit
32 kHz
ID Register
PD-Bus
6
Multicore
MMCI
Debug Support
V5.4
5
8
External
8
16
Bus & Port
21
24
Controller
CS(4:0)
3
AFC Unit
Pulse-Carry Mod.
SIM card
Keypad
Interface
Interface
High Speed
(F=512, D=8/16)
2
6
4
The
EGOLD+
contains a 16-bit micro-controller (µC part), a GSM analog Interface
(EGAIM), a DSP computing core (DSP part) and an interface for application-specific
switch-functions.
The µC part consists of the following:
• Micro-controller
• System interfaces for internal and external peripheries
• On-chip peripheries and memory
The Controller Firmware carries out the following functions:
• Control of the Man Machine Interface (keypad, LCD, sensing element, control of
the illumination,...)
• GSM Layer 1,2,3 /GPRS
• Control of radio part (synthesizer, AGC, AFC, Transmitter, Receiver...),
• Control of base band processing (EGAIM)
• Central operating system functions (general functions, chip select logic, HW driver,
control of mobile phones and accessories...).
V1.00
S55/S57
2
2
Enable Signals to
X- and PD-Bus Peripherals
Clock Generation
ASC0
Peripheral Enable
ASC1
Generator
Autobaud
Detect
Power
GPT1/GPT2
Management
Watchdog
13/26/52 MHz / 32 kHz
READY#
MCU
NMI#
HOLD#
HLDA#
C166S
CLKOUT
X-Bus
RSTOUT#
OCDS
DPEC
Interrupt Controller
80
Dual Port RAM
1k x 16
LM-Bus
SRAM
PROM
1k x 16
256k x 8
I
2
C
Logic
GPRS
Arranger
Cipher Unit
(LPA)
Page 23 of 49
Company Confidential © Copyright Siemens AG
16 bit I/O Ports
6
3
DSP Serial
I2S
Comm. Interface /
DAI
DSP Timer1
DSP Timer2
OAK78 DSP
78 MHz
Interleaving / De-Interleaving
Speech Coding/Decoding
(FR, HR, EFR, AMR)
Level Measurement
Channel Coding/Decoding
(FR, HR, EFR, AMR)
Equalization
Encryption / Decryption
Voice Memo/Voice Dialing
GPRS support
Interrupt Controller
OCEM
Bus
SEIB
Interface
Shared Memory
Unit
Dual Port 512 x 16
GSM
RF Control
TDMA Timer
8
3
4
E-GOLD+ V3.0 Architecture
Single Chip Cellular Baseband Processor
Package: P-LFBGA-208
Interp./
Noise
Viterbi
GMSK
Shaper
HW
Modulator
Accelerator
Interp./
Noise
Shaper
Cipher Unit
Σ∆
ADC
A51/52
Voiceband
Filters
P ROM
60k x 16
RX and TX
Σ∆
DAC
P RAM
4k x 16
Y RAM
Σ∆
2k x 16
Baseband
ADC
Filter/
X RAM
12 bit resolution
Cordic-
15k x 16
Processor
Σ∆
X ROM
ADC
36k x 16
Switch Matrix
Battery & Temperature
Power Control
reference
voltage
TAP Controller
JTAG
Boundary Scan
ICM MP CCQ GRM
12/02
DAC
R-String
2
DAC
R-String
2
2
MUX
2
2
2
2
2
Measurement
RF Output
10 bit DAC
Bandgap
confidential
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