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Related Manuals for GE OpenVPX VPXcel6 SBC622
Summary of Contents for GE OpenVPX VPXcel6 SBC622
- Page 1 Intelligent Platforms Hardware Reference VPXcel6 SBC622* 6U VPX Single Board Computer THE SBC622 IS DESIGNED TO MEET THE EUROPEAN UNION (EU) RESTRICTIONS OF HAZARDOUS SUBSTANCE (ROHS) DIRECTIVE (2002/95/EC) CURRENT REVISION. Publication No: 500-9300527818-000 Rev. B...
- Page 2 Document History Hardware Reference Document Number: 500-9300527818-000 Rev. B March 18, 2011...
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Page 3: Table Of Contents
Table of Contents List of Figures ................. 7 List of Tables . - Page 4 2.2 External Interfaces................44 2.2.1 Form Factor .
- Page 5 3.2.25 Timer 4 Value Register (0x63C) ............58 3.2.26 Timer 1 IRQ Clear (T1IC) .
- Page 6 B.5 Boot Setup Menu ................95 B.6 Security Setup Menu .
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Page 7: List Of Figures
List of Figures Figure 1 SBC622 Convection Cooled Assembly ............11 Figure 2 SBC622 Conduction Cooled Assembly . -
Page 8: List Of Tables
List of Tables Table 1 Fabric Support for SBC622...............10 Table 1-1 Jumpers, Headers, Connectors . - Page 9 Table A-5 PCIe Expansion Plane (P2) ..............71 Table A-6 PCIe Expansion Plane (J2) .
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Page 10: Table 1 Fabric Support For Sbc622
Overview Introduction GE Intelligent Platforms’ VPXcel6 SBC622* is a rugged OpenVPX compliant Single Board Computer (SBC) in 6U VPX form factor designed to meet requirements of a wide range of applications from industrial through fully rugged defense and aerospace programs. ® ® The SBC622 uses the Intel Core™ i7 Processor with the Mobile Intel QM57 Express Chipset Platform Controller Hub (PCH). Core i7 offers integrated graphics and a memory controller, plus dual core processing that operates at speeds up to 2.53 GHz. SBC622ʹs 10 Gigabit Ethernet (GbE) Data Planes, Gigabit Ethernet Control Planes, and PCIe Expansion plane deliver optimum scalability and interoperability. Two onboard PMC/XMC expansion sites allow flexibility to configure the SBC622 according to the precise requirements of the application. An onboard Flash device used for BIOS storage is large enough to optionally host additional pre‐boot applications such as Built‐In Test (BIT). SBC622 is compliant to the OpenVPX profile ʺMOD6‐PAY‐4F1Q2U2T‐12.2.1‐8ʺ. The following table details the fabric support for this product: Table 1 Fabric Support for SBC622 Data Plane Expansion Plane Control Plane UTPs Control Plane TPs 2 Channels of 10GBase-KX4 16 lanes of Gen2 PCIe 2 Channels of 1000Base-BX 2 Channels of 1000Base-T Per Section 5.1.5 of... -
Page 11: Figure 1 Sbc622 Convection Cooled Assembly
Convection Cooled Board (Level 1 and Level 2) The SBC622 convection cooled board is a 6U single‐slot VPX board meeting the mechanical requirements defined in the VITA 46.0 specification. The SBC622 convection option is defined for standard commercial temperature (Level 1 and Level 2) operation in an air cooled chassis. Figure 1 SBC622 Convection Cooled Assembly Conduction Cooled Board (Level 4 and Level 5) The SBC622 conduction cooled board is a 6U single‐slot VPX board meeting the mechanical requirements defined in the VITA 46.0 specification. The SBC622 conduction option is defined for extended temperature (Level 4 and Level 5) operation in rugged environments using a conduction cooled chassis. Conduction cooled assembly does not support front panel connectors and indicators, nor does it provide support for PMC/XMC front panel connectors. Figure 2 SBC622 Conduction Cooled Assembly Overview 11... - Page 12 SBC622 Features The SBC622 provides the following core hardware and firmware resources: • Intel Core i7 Processor up to 2.53 GHz – Integrated two channel DDR3‐1067 memory controller with ECC – Integrated graphics controller • Up to 4 MByte shared cache • Up to 8 GByte soldered DDR3 memory with ECC • Up to 8 GByte NAND Flash (soldered) • Dual onboard mezzanine expansion sites – 2x PCI‐X PMC/XMC • Front I/O (air cooled only) – 1x Gigabit Ethernet port – 2x USB ports – 1x COM port • Rear I/O – x16 or 4x 4 PCIe (NTB capable) – 2x 10 Gigabit Ethernet (GbE) ports – 4x GbE ports – 1x DVI/VGA – 3x SATA Ports – 2x COM Ports –...
- Page 13 Embedded Features • Remote Boot Agent for all Ethernet ports • Watchdog and general‐purpose timers • GPIO (8 bits) The embedded features of the SBC622 are described in Chapter 3: CPLD Control and Status Registers. Intel Core i7 Processor and Mobile Intel QM57 Express Chipset The SBC622 incorporates the latest Intel chipset technology, built around a Core i7 Dual Core processor with integrated memory controller hub and a Mobile Intel QM57 Express Chipset. Core i7 is the next generation of 64‐bit, multi‐core mobile processors built on 32‐nanometer process technology. The major feature of the Core i7‐ECC is the DDR3 memory and graphics controller integration with the Dual Core CPU. Features of the Core i7 Processor • Intel Intelligent Power Technology allows processors to operate at optimal frequency • Intelligent performance on‐demand with Intel Turbo Boost Technology • Multi‐level shared cache improves performance by reducing latency to fre‐ quently used data • ...
- Page 14 Software Support The SBC622 provides two Core i7 processor cores with a shared memory and I/O resource pool. Customer system applications call for software platforms that support Symmetric Multiprocessing (SMP) operation as well as near real time support of independent application threads. Generally, these different software needs require the support of multiple operating systems, and also require software driver and Board Support Packages (BSP) to support the low level hardware functions. Device Driver Strategy Standard device drivers for the silicon resources are used where possible. The SBC622 software re‐uses existing device drivers for features that are common to previous single board computers. BIOS firmware, Infrastructure Support The SBC622 includes BIOS firmware which provides all functions required by the processor core and chipset. This package also includes the onboard hardware initialization code that is executed following release from reset. The BIOS code is supported via a flash device on the PCH SPI bus. The BIOS also provides ROM code that supports remote booting from any of the Ethernet ports. Target Operating Systems SBC622 hardware supports Windows, Linux, and VxWorks operating systems. The following notes provide information to properly install certain versions of the operating systems. • Windows XP SP3 NOTE There is a known issue with certain brands and models of USB CDROM drives where the USB CDROM path is lost during WindowsXP Install to CompactFlash.
- Page 15 References ANSI/ VITA 46.0 ANSI/ VITA 46.9 XMC and PMC User I/O Mapping for VITA 46 ANSI, NCITS 340‐2000 Information Technology ‐ AT Attachment with Packet Interface ‐ 5 (ATA / ATAPI‐5) Rev 3, February, 2000 European Union Directive 2002/95/EC of the European Parliament of 27 January 2003 on the Restriction of the Use of Certain Hazardous Substances in Electrical and Electronic Equipment (RoHS) European Union, Directive 2002/96/EC of the European Parliament of 27 January 2003 on Waste Electrical and Electronic Equipment (WEEE) IEEE 1149.1‐1990, IEEE Standard Test Access Port and Boundary Scan Architecture June, 1993 IEEE 1386‐2001, IEEE Standard for a Common Mezzanine Card (CMC) Family June, 2001 IEEE 1386.1‐2001, IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards (PMC) June, 2001 Intel, Low Pin Count Interface Specification, Rev 1.1 August, 2002 IPC, IPC‐A‐600 Acceptability of Printed Board Rev F, November, 1999 IPC, IPC‐A‐610, Acceptability of Electronic Assemblies, Rev C January, 2000 IPC, IPC‐CC‐830B, Qualification and Performance of Electrical Insulating Compound for Printed Wiring Assemblies, Rev B August, 2002 Overview 15...
- Page 16 MIL‐HDBK‐217F, Military Handbook, Reliability Prediction of Electronic Equipment December, 1991 PCI Special Interest Group (SIG), PCI Local Bus Specification Revision 2.2 December, 1998 PCI Special Interest Group (SIG), PCI Express Base Specification Rev 1.1 March, 2005 S‐ATA, Serial ATA: High Speed Serialized AT Attachment Rev 1.0a January, 2003 Telecommunications Industry Association, TIA / EIA‐232‐F‐1997, Interface Between Data Terminal Equipment and Data Circuit‐ Terminating Equipment Employing Serial Binary Data Interchange October, 1997 Underwriterʹs Labs, UL‐94, Standard for Tests for Flammability of Plastic Materials for Parts in Devices and Appliance, Edition 5 October, 1996 USB, Universal Serial Bus Specification Rev 2.0 April 2000 Intel Core™ i7‐600, i5‐500, i5‐400 and i3‐300 Mobile Processor Series Datasheet Volume 1 Intel Document Number 322812 January 2010 Intel Core i7‐600, i5‐500, i5‐400 and i3‐300 Mobile Processor Series Datasheet Volume 2 Intel Document Number 322813 January 2010 Intel Core i7‐600, i5‐500, i5‐400 and i3‐300 Mobile Processor Series Specification Update Intel Document Number 322814 January 2010 Intel 5 Series Chipset and Intel 340 Series Chipset Datasheet Intel Document Number 322169 September 2009 ExpressLane PEX 8648‐AA, AB, and BA 48‐Lane/12‐Port PCI Express Gen 2 Switch Data Book April 2008 16 SBC622 Hardware Reference Manual...
- Page 17 Intel 82599 10 GbE Controller Datasheet Intel Document Number 322429‐002 July 2009 The following documents are continuously updated and are available at: http://www.intel.com/products/processor/manuals/ Intel 64 and IA‐32 Architectures Software Developerʹs Manual Volume 1: Basic Architecture Intel 64 and IA‐32 Architectures Software Developerʹs Manual Volume 2A: Instruction Set Reference, A‐M Intel 64 and IA‐32 Architectures Software Developerʹs Manual Volume 2B: Instruction Set Reference, N‐Z Intel 64 and IA‐32 Architectures Software Developerʹs Manual Volume 3A: System Programming Guide Part 1 Intel 64 and IA‐32 Architectures Software Developerʹs Manual Volume 3B: System Programming Guide Part 2 Intel 64 Architecture x2APIC Specification Intel 64 and IA‐32 Architectures Application Note TLBs, Paging‐Structure Caches, and Their Invalidation Intel 64 and IA‐32 Architectures Optimization Reference Manual Overview 17...
- Page 18 Organization This Manual is composed of the following chapters and appendices: Overview provides a general description of the SBC622, References, general Safety Summary and symbols. Chapter 1 Installation and Setup describes unpacking, handling and installing the hardware, as well as describing external interfaces. Chapter 2 Standard Features describes the product’s standard features and functionality. Chapter 3 CPLD Control and Status Registers describes the registers provided by the CPLD. Maintenance provides GE’s contact information relative to the care and maintenance of the unit. Appendix A: Connectors and Pinouts illustrates and defines the connectors included in the unit’s I/O ports. Appendix B: BIOS Setup Utility describes the setup options in the system BIOS firmware. Appendix C: Specifications and Physical Description lists the hardware specifications for the SBC622. 18 SBC622 Hardware Reference Manual...
- Page 19 Safety Summary The following general safety precautions must be observed during all phases of the operation, service and repair of this product. Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design, manufacture and intended use of this product. GE assumes no liability for the customerʹs failure to comply with these requirements. Ground the To minimize shock hazard, the chassis and system cabinet must be connected to System an electrical ground. A three‐conductor AC power cable should be used. The power cable must either be plugged into an approved three‐contact electrical outlet or used with a three‐contact to two‐contact adapter with the grounding wire (green) firmly connected to an electrical ground (safety ground) at the power outlet. Do Not Do not operate the system in the presence of flammable gases or fumes. Operation Operate in an of any electrical system in such an environment constitutes a definite safety hazard. Explosive Atmosphere Keep Away Operating personnel must not remove product covers. Component replacement from Live and internal adjustments must be made by qualified maintenance personnel. Do not replace components with power cable connected. Under certain conditions, Circuits dangerous voltages may exist even with the power cable removed. To avoid injuries, always disconnect power and discharge circuits before touching them. Do Not Service Do not attempt internal service or adjustment unless another person capable of ...
- Page 20 Warnings, WARNING Cautions WARNING denotes a hazard. It calls attention to a procedure, practice, or and Notes condition, which, if not correctly performed or adhered to, could result in injury or death to personnel. CAUTION CAUTION denotes a hazard. It calls attention to an operating procedure, practice, or condition, which, if not correctly performed or adhered to, could result in damage to or destruction of part or all of the system.
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Page 21: Installation And Setup
1.2 Handling Precautions CAUTION Some of the components assembled on GE’s products may be sensitive to electrostatic discharge and damage may occur on boards that are subjected to a high energy electrostatic field. When the board is placed on a bench for configuring, etc., it is suggested that conductive material be inserted under the... -
Page 22: Hardware Setup
1.3 Hardware Setup The SBC622 is factory populated with user‐specified options as part of the SBC622 ordering information. Contact Sales for ordering information at 1‐800‐322‐3616. For option upgrades or for any type of repairs, contact customer care to receive a Return Material Authorization (RMA). GE Customer Care is available at: 1‐800‐433‐2682, 1‐780‐401‐7700. Or, visit our website at: www.ge-ip.com The SBC622 is tested for system operation and shipped with factory‐installed jumpers, headers and connectors. The physical locations of the jumpers, headers and connectors for the SBC with the PMC option are illustrated in Figure 1‐1 Top Assembly Jumpers, Headers, Connectors Locations on page 23. The definitions of the jumpers, headers and connectors are included in Table 1‐1 Jumpers, Headers, Connectors on page 24. All jumpers marked User Configured in the following tables may be changed or modified by the user. All jumpers marked Factory Configured should not be modified by the user. -
Page 23: Figure 1-1 Top Assembly Jumpers, Headers, Connectors Locations
Figure 1-1 Top Assembly Jumpers, Headers, Connectors Locations Key 1 PMC1 Bridge Dual 10 GbE Pericom 82599 PMC2 Bridge E505 Pericom E504 PCIe Switch Quad Key 2 E503 PEX8648 E500 82580 E501 (On Back) E506 R215 E502 XDP Debug Port Debug P104 Port... -
Page 24: Table 1-1 Jumpers, Headers, Connectors
Table 1-1 Jumpers, Headers, Connectors Connector Function VPX Backplane Connector: Power Management VPX Backplane Connector: 10 GbE, Data Plane VPX Backplane Connector: PCIe x16 VPX Backplane Connector: COM 1, PMC1 I/O VPX Backplane Connector: COM2, 4x GbE, 2x USB, XMC 1 I/O , Control Plane , GPIO VPX Backplane Connector: PMC 2 I/O, Audio Speaker VPX Backplane Connector: 3x SATA, XMC 2 I/O, DVI/VGA, 4X USB, 8x GPIO P103... -
Page 25: Jumper Descriptions
1.5 Jumper Descriptions The board has push‐on jumpers included in the standard kit of parts; additional jumpers may be obtained on request. These are suitable for Level 1 to 3 low vibration applications. See Figure 1‐1 Top Assembly Jumpers, Headers, Connectors Locations on page 23 for Jumper locations. For Level 4 and 5 products, connect jumpers by wire-wrapping between the pin posts and then cover these wire wrapped connections with the same conformal coating as that used on the board. This provides a reliable connection under heavy shock and vibration conditions and prevents oxidation of the connection due to moisture ingress. -
Page 26: Table 1-5 E501 Xmc2 Nv Memory Write Enable/Disable; Smbus Disable/Enable
Table 1-5 E501 XMC2 NV Memory Write Enable/Disable; SMBus Disable/Enable E501 Position Not Installed Installed NVRAM Memory Write Disable NVRAM Memory Write Enable SMBus Disable SMBus Enable Note: *When installed, E501 overrides the behavior of the VPX backplane NVMRO signal for the XMC site. Table 1-6 E502 RTC Reg Clr;... -
Page 27: Installation And Power Up/Reset
1.6.2 Board Installation Notes • Keying may dictate the backplane slot(s) into which the board can be inserted. • Air‐cooled versions have an injector/ejector handle to ensure that the back‐ plane connectors mate properly with the backplane. The captive screws at the top and bottom of the front panel allow the board to be tightly secured in position, which provides continuity with the chassis ground of the system. • Conduction‐cooled versions have screw‐driven wedge locks at the top and bottom of the board to provide the necessary mechanical/thermal interface. Correct adjustment requires a calibrated torque wrench with a hexagonal head of size 3/32ʺ (2.38 mm), set to between 0.6 and 0.8 Nm. • In an air‐cooled development enclosure, when taking I/O connections from the backplane connectors, use of GE’s I/O modules (or some equivalent sys‐ tem) ensures optimum operation with regard to EMI. 1.6.3 Power Requirements The SBC622 utilizes the VS1 and VS3 power supplies from the VPX backplane. The SBC622 requires up to 16 W from VS1 (@12V), and 38 W from VS3 (@5 V) . The SBC622 does not connect to the VS2 power pins. Live insertion as defined in VITA 1.4 is not supported on SBC622. • The VS1 and VS3 rails are used for SBC622 circuits and at the PMC site. The VCC_12V_AUX and VCC_‐12V_AUX rails are only used at the PMC sites. Aggregate power load is expected to be 60 W maximum for the main SBC622 board, plus a maximum of 7.5 W for each of the PMC sites. Additional current loading may be supported at the PMC site to the limit of the backplane and PMC site connector capacities. 1. Power measurements made while running BurnInTest Pro CPU Stress Testing at 100% Utilization. -
Page 28: Connecting To Sbc622
1.6.4 Connecting to SBC622 To interact with onboard firmware requires the SBC622 to have, at a minimum, a control terminal or HyperTerminal connection present on the serial COM1 port and a VGA monitor connected to the RGB outputs. An Ethernet connection may also be required for Host/Target interaction. For development systems, connection to the Serial, Ethernet I/O and Graphics ports can be achieved using a rear backplane module. This converts the condensed pinout of the backplane connectors to pinouts suitable for use by industry standard connectors. The following items are required: • The SBC622 • A rear transition module (VPX6UX604*), and an Open VPX‐compliant backplane • A null‐modem 9‐way D to 9‐way D‐type cable for connecting COM1 to a control terminal or HyperTerminal • For the Ethernet port, a CAT5 (or better) straight‐through patch cable for 10/100/1000Base‐TX • A VGA monitor and suitable cables • USB Keyboard Similar antistatic and safety precautions apply when handling and/or installing I/O modules as for the board. 1.6.5 Power-up As the SBC622 runs through its boot sequence, the LEDs illuminate. See section 1.9.2 LEDs, page 36 for a description of the function of the LEDs. 1.6.6 Built-In TEST (BIT) • BIT functionality is provided by hardware in conjunction with optionally installed software. -
Page 29: Installation Of Sbc622 Into Chassis
1.7 Installation of SBC622 into Chassis The SBC622 conforms to the VPX physical specification for a 6U board. The SBC622 can be configured as the system controller or as a peripheral board. It can be plugged directly into any OpenVPX chassis conforming to a backplane profile compatible with the payload profile of the SBC622. See Figure 1‐2 SBC622 in Chassis on page 30. CAUTION Do not install or remove the board while power is applied. The following steps describe the recommended method for installation and powerup of the SBC622: 1. Make sure power to the equipment is off. 2. Connect a PMC or an XMC module to the SBC622 (if it is to be used) prior to board installation. See 1.8 Installing or Removing a PMC Card on page 32. Refer to the Product Manual for the XMC/PMC module for configuration and setup. NOTE Air flow as measured at the output side of the heatsink is to be greater than 450 LFM. 3. ... -
Page 30: Figure 1-2 Sbc622 In Chassis
Figure 1-2 SBC622 in Chassis VPX Backplane SBC622 inserted into Chassis 30 SBC622 Hardware Reference Manual... -
Page 31: Clear Cmos/Rtc/Password
1.7.1 Clear CMOS/RTC/Password NOTE The BIOS has the capability of password protecting casual access to the unit’s CMOS setup screens. The CMOS Clear switch allows the user to clear the password in the case of a forgotten password. This also clears all CMOS settings and restores factory defaults. To clear the CMOS password: 1. ... -
Page 32: Installing Or Removing A Pmc Card
1.8 Installing or Removing a PMC Card The SBC622 incorporates PMC expansion sites that support the PCI‐X bus. The PMC sites are on private PCI‐X bus segments allowing for maximum data transfer rates of 1064 MByte/s between the processors and the PMC device. The PMC sites are capable of up to 133 MHz operation and support for 3.3 V or 5 V signaling and VIO. They are compatible with the earlier PCI interface versions (33/66 MHz, 32/64‐bit). NOTE For best performance, PMC card drivers should use DMA. The following procedure is applicable for both removal and installation of PMC modules and fully populated PMC cards. See Figure 1‐3 PMC Installed onto 2‐ PMC Site Model on page 33. 1. Remove the mezzanine screws. 2. Separate the mezzanine connector while lifting and rotating the mezzanine board. Pull away from the front panel. 3. Remove the PMC modules by removing two mounting screws per module. This step will be necessary when initially installing a PMC card into a SBC622. Follow the reverse sequence to install a PMC card or a PMC module. 1.8.1 Installing 3.3 V or 5.0 V VIO Keypin The SBC622 supports both 3.3 V and 5.0 V VIO via the placement of the PMC ... -
Page 33: Figure 1-3 Pmc Installed Onto 2-Pmc Site Model
Figure 1-3 PMC Installed onto 2-PMC Site Model Installation and Setup 33... -
Page 34: Front Panel Of Sbc622 (Convection Cooled Version)
1.9 Front Panel of SBC622 (Convection Cooled Version) 1.9.1 Connectors Front panel I/O connectors load only on convection cooled versions of the SBC622. The SBC622 Front Panel provides access to: • XMC/PMC1 XMC/PMC Site 1 slot • XMC/PMC2 XMC/PMC Site 2 slot • RST Manual reset switch • BPHF Status LEDs • COM3 COM3 serial port • LAN 10/100/1000 Ethernet Connector • USB Two USB Serial Ports NOTE If a board reset is required via the manual reset switch, ensure that the switch is not repeatedly pressed during the power up/reset cycle. -
Page 35: Figure 1-4 Front Panel Layout/Led Status (Convection Cooled) Sbc622
Figure 1-4 Front Panel Layout/LED Status (Convection Cooled) SBC622 B P H F Installation and Setup 35... -
Page 36: Leds
1.9.2 LEDs Front Panel The SBC622 convection cooled front panel provides the following indicators: Indicators The four general status LEDs provide status information as follows (left to right on the panel): • Boot status (RED): illuminates during BIOS boot and power‐on self test operation only • Power (GREEN): illuminates when all internal rail voltages are within oper‐ ating tolerances • Hard Drive Activity (YELLOW): illuminates while S‐ATA drive accesses are in progress • BIT Fail (RED): illuminates when onboard BIT (optional) has detected an error condition. When the Processor/PCH are in the Power Management state, S5, all four front panel LEDs illuminate. The two LEDs integrated in the RJ45 receptacle for GbE ports provide link activity and link speed status information for the Ethernet ports on SBC622 as follows (left to right on the panel): • Link Activity [GREEN]: illuminates during link, flashing during active data transfers on the port • Link Speed [YELLOW/GREEN]: link speed is 1 Gb/s when Green, 100 Mb/s when yellow, 10 Mb/s when extinguished The Reset switch is a standard push‐button. When activated, this switch forces a hardware reset to the SBC622 assembly. Signal assignments for the front panel connectors are provided in Appendix A: Connectors and Pinouts. 36 SBC622 Hardware Reference Manual... -
Page 37: Figure 1-5 Front Panel Sbc622 (Isometric View (Convection Cooled))
Figure 1-5 Front Panel SBC622 (Isometric View (Convection cooled)) Installation and Setup 37... -
Page 38: Sbc622 Rear I/O Support
1.10 SBC622 Rear I/O Support The SBC622 provides rear I/O support for VPX with x16 or 4 x4 PCIe, two 10 GbE ports, four GbE ports, DVI/VGA, six USB ports, two COM2 (RS232/RS422), up to three SATA drives, eight GPIOs, two sets of XMC/PMC I/O signals. See Section 2.3 Open VPX Backplane Interface on page 44. These signals are accessed by the use of a rear transition module (RTM) which terminates the signals into industry standard connectors. Connector pinouts and orientation for the SBC622, are defined in Appendix A: Connectors and Pinouts. The SBC622 processor board is designed to support RTM VPX6U604. Other RTMs may not support all available SBC622 rear I/O mentioned above. RTM connections are defined in the appropriate RTM Installation Guides. Figure 1-6 SBC622 VPX Backplane SBC622 backplane 38 SBC622 Hardware Reference Manual... -
Page 39: Standard Features
2 • Standard Features Figure 2-1 Block Diagram Front IO PCIe to PCI-X XMC/PMC Site 2 Quad 2/4 GByte DDR3 QM57 Core i7 CPLD Super 2/4 GByte DDR3 XMC/PMC Site 1 PCIe SATA PCIe to Switch to PATA PCI-X 10 GbE NAND Flash x16/... -
Page 40: Functional Definitions
2.1 Functional Definitions 2.1.1 Core i7 Dual Core Processor The SBC622 offers the Core i7 Dual Core processor with an integrated memory controller hub, the Mobile Intel QM57 Express Chipset Platform Controller Hub (PCH). The Core i7 processor functions are as follows: • Two execution cores with 18/25/35W options • Separate L1 data/instruction caches of 32 KByte each for each core • Separate L2 256 KByte (shared) data/instruction caches for each core • Up to 4 MByte of shared L3 • Graphics controller • Integrated dual channel (DDR3) 1067 MHz memory controllers with ECC – Configured for 2x Refresh to support compatibility with extended temperature operation – 800 MHz for 1.06 GHz CPU Option. • SIMD SSE 4.1/4.2 • Root complex for PMC/XMC site #1, the 10 GbE Ethernet Controller, and the VPX PCIe expansion plane – x16 PCIe interface to onboard switch 2.1.2 Mobile Intel QM57 Express Chipset The Mobile Intel QM57 Express Chipset contains a DMI serial link interface to the ... -
Page 41: Volatile Memory Ddr3 Main Memory Array
The Mobile Intel QM57 Express Chipset also includes a number of local processor peripheral resources, including general purpose timers, an interrupt controller, and Real‐Time Clock (RTC) circuit. See the Section Software Support on page 14. 2.1.3 Volatile Memory DDR3 Main Memory Array The SBC622 provides volatile memory via the dual channel DDR3 memory controller integrated into the Core i7 processor. The main memory array on SBC622 is as follows: • Two channels of DDR3‐1067 SDRAM components on a 72‐bit data bus with ECC support (Total of 8 GBytes max). • Bank 0 is a 4 GByte maximum array on Channel 0 with components soldered to the main SBC622 PCB. Bank 1 is a 4 GByte maximum array on Channel 1 with components soldered to the main SBC622 PCB. 2.1.4 Non-Volatile Memories NAND Flash Up to 8 GByte of NAND flash is soldered to the board and presents itself to the system as one or two SATA drives. The onboard flash drives may be disabled with jumper E505. C/SMBus The SBC622 assembly includes EEPROM memory of at least 512 Kbit accessible resources via the SMBus of the PCH. 2.1.5 SPI Bus Resources The SBC622 supports BIOS firmware code using the Mobile Intel QM57 Express Chipset SPI bus channel. The BIOS firmware is contained in one 4 MByte size SPI bus Flash part. The SPI flash parts can be in‐circuit programmed with updates after initial programming of the SPI bus parts which occurs off of the unit. 2.1.6 LPC Bus Resources The LPC bus on SBC622 supports the following resources: • ... -
Page 42: Quad Gbe Ports Via The Front Panel And Backplane
2.1.9 Quad GbE Ports via the Front Panel and Backplane The SBC622 supports four Ethernet LANs with four Intel Ethernet controllers provided by the Intel 82580. Front panel or backplane selection of the GbE port is made by the onboard jumper, E7 at points 5‐6; 10Base‐T, 100Base‐TX and 1000Base‐T options are supported via a front panel RJ45 connector or selectable to the backplane by routing to P4 per Open VPX and VITA 46.7. • Front Panel selection of the GbE port includes two status LEDs displaying speed and link activity on the RJ45 receptacle • Backplane selection of the GbE port provides no LED support • Ports 1 and 2 provide 10/100/1000‐T support and routed to P4 (one channel mux’d with the Front Panel) • Ports 3 and 4 provide 10/100/1000‐BX support and routed to P4 GbE ports support remote boot from either the Front or Rear configuration. 2.1.10 Dual 10 GbE The SBC622 supports Dual 10 GbE Ports 1 and 2 that are controlled by the Intel 82599 Ethernet Controller. • Dual 10 GbE (1000BASE‐KX4) is routed to P1. 2.1.11 Remote Boot BIOS The SBC622 supports remote booting on the GbE Quad ports 1‐4 and Dual 10 GbE ports 1‐2 using the Intel PXE Boot firmware Ethernet BIOS firmware. Refer to ... -
Page 43: Temperature Sensor
2.1.12 Temperature Sensor • Monitors core temperatures of critical components such as the CPU • Monitors ambient temperature • Connected via SMBus 2.1.13 BMM The SBC622 is equipped with a Board Management Micro‐controller (BMM) with the following capabilities. • Connected to COM4 • Powered from P3V3_AUX supply allowing for operation when SBC main power is off • Connected via SMBus • Connected to VPX geographic address • Firmware to support BMM functionality may be optionally provided 2.1.14 ETI The SBC622 provides elapsed‐time recorder via the Maxim DS1682 offering a 32‐bit, nonvolatile, elapsed time counter (ETC) with quarter‐second resolution and provides thirty‐four years of total time accumulation. 2.1.15 Trusted Platform module (TPM) The SBC622 provides trusted platform support via the Atmel AT97SC3204 TPM offering: • Hardware asymmetric crypto engine • 2048‐bit RSA sign • ... -
Page 44: External Interfaces
2.2 External Interfaces As noted in the Overview, the SBC622 board layout supports both conduction and convection cooled mechanicals. This section provides an overview of the functionality associated at each port, while detailed signal assignments on the backplane connectors are provided in Appendix A: Connectors and Pinouts. 2.2.1 Form Factor The SBC622 size and shape is 6U single height form factor per VITA 46.0. The SBC622 supports both convection and conduction cooled operational environment via build levels. 2.2.2 Electrical Interfaces • RS422B/485A Interface • Two balanced pair serial interfaces provided in accordance with ANSI/TIA/EIA‐485‐A Mar 1998 and ANSI/EIA/TIA‐422‐B Jan 2000 • The RS485/422 interfaces support baud rates up to and including 115.2 kBaud 2.2.3 Power Entry and Distribution Definitions The backplane VS1 and VS3 power rails are accessed by the SBC622 following the functional requirements for VPX boards in VITA 46.0. This circuit also controls the Power LED on the front panel of the assembly (See Section 1.9.2 LEDs on page 36). Live insertion as defined in VITA 1.4 is not supported on the SBC622. • The VS1 and VS3 rails are used for SBC622 circuits and at the PMC site. The VCC_12V_AUX and VCC_‐12V_AUX rails are only used at the PMC sites. Aggregate power load is expected to be 60 W maximum for the main SBC622 board, plus a maximum of 7.5 W for each of the PMC sites. Additional current loading may be supported at the PMC site, to the limit of the backplane and PMC ... -
Page 45: Gpio
2.3.1 GPIO GPIO 8 bits of general purpose IO routed to P4/6. • GPIO capable of generating interrupts • All GPIO capable of input/output operation 2.3.2 USB 2.0 Six USB channels are routed to P4/6 and two USB 2.0 channels are routed to the Front Panel (J1 and J3). The onboard USB controller supports the standard USB interface Rev. 2.0. 2.3.3 Video Graphics Adapter The Mobile Intel QM57 Express Chipset DVI/VGA interface is routed to the VPX P6 connector. The SBC622 supports high‐resolution graphics and multimedia‐quality video using the Intel HD graphics controller. Screen resolutions up to 1,600 x 1,200 colors (single view mode) are supported by the graphics adapter. NOTE Under simultaneous heavy processor and graphics activity with the 1.07 GHz processor option, video quality may degrade slightly. VGA Interface The VGA interface can be accessed using an included adapter to adapt from the ... -
Page 46: Digital Visual Interface (Dvi-D)
2.3.4 Digital Visual Interface (DVI-D) The SBC622 supports a Digital Visual Interface that provides a high‐speed digital connection for visual data types that are display technology independent. DVI‐D is a display interface developed in response to the proliferation of digital flat‐panel displays. DVI output is routed to the backplane via P6. Table 2-2 Partial List of Display Modes Supported for Digital Bits Per Pixel (Frequency) in Hz Resolution 16-bit 32-bit 640 x 480* 800 x 600 1024 x 768 1600 x 1200 60, 75, 85, 100 60, 75, 85, 100 *The Intel Extreme Graphics driver 14.36.3.4990 does not load at 640x480 resolution as set by BIOS. -
Page 47: Pci Mezzanine Card (Pmc) Interface
2.3.9 PCI Mezzanine Card (PMC) Interface The SBC622 SBC has two PCI mezzanine card (PMC) interfaces per the following: • Conforms to IEEE 1386‐2001, ʺIEEE Standard for a Common Mezzanine Card (CMC) Familyʺ and to IEEE 1386.1‐2001, ʺIEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards (PMC)ʺ. • Connector pins are assigned in accordance with IEEE 1386.1‐2001, ʺIEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards (PMC)ʺ. • Interfacesʹ signal characteristics and the power available to each PCI mezza‐ nine card conform to PCI Local Bus Specification, Rev 2.2, 1998. • Supports PCI‐X signaling at up to 133 MHz. 2.3.10 PCI Device/Vendor IDs and Bus Number The following table details the PCI Vendor/Device IDs as well as the bus number of the device without any PMC cards installed. Table 2-3 PCI Device/Vendor IDs and Bus Number Device Component Device ID Vendor ID Device Function... -
Page 48: Front Panel Interface
2.3.11 Front Panel Interface The convection cooled version of the SBC622 supports the Front Panel option which includes: • Reset Switch • Four status LEDs. The functional definition for each LED is provided in sec‐ tion 1.9.2 LEDs, page 36 • COM3 Communications port via RS232/RS422 Serial Port • Dual USB Ports – Two USB ports on the front panel are a Type A (host) interface, capable of supporting USB 1.0, 1.1, and 2.0 targets. – Front Panel USB Ports are capable of supporting 1.5A power. • One GbE via RJ45 For further information on the Front Panel, See Section 1.9 Front Panel of SBC622 (Convection Cooled Version) on page 34. 2.4 Built-In TEST (BIT) BIT functionality is provided by hardware in conjunction with installed software. BIT is included for fault detection/isolation and real time determination of operational status in all modes of operation. Contact the factory to order configurations of the SBC622 that support BIT. 48 SBC622 Hardware Reference Manual... -
Page 49: Cpld Control And Status Registers
3 • CPLD Control and Status Registers GE’s SBC622 features additional capabilities beyond those of a typical desktop computer system. The units provide two software‐controlled, general‐purpose timers along with a programmable Watchdog Timer for synchronizing and controlling multiple events in embedded applications. The SBC622 provides a bootable NAND Flash system and 512 KBits of non‐volatile SEEPROM. 3.1 CPLD Description The SBC622 CPLD provides a general purpose I/O port, Watchdog Timer, and general purpose timers. The block diagram for the CPLD is shown in the figure below. Figure 3-1 Block Diagram for CPLD 32-bit Timer 32-bit Timer IO addr: 0x600+ LFRAME# LAD[3..0] PCI CLK Board ID Interface RESET# BMM Ctrl. Reg. -
Page 50: Control And Status Registers
3.2 Control and Status Registers These registers are provided by the CPLD and appear in the I/O memory map (for reading and writing) starting at address 0x600. They can also be read back in memory space under ID7 + address 0x04000000. Table 3-1 Control/Status Registers ISA I/O Port (Hex) Register Description Access Board ID Register Read Only Board Revision Register Read Only Board Configuration Register 1 Read Only Board Configuration Register 2 Read Only Board Configuration Register 3 Read Only VPX Geographical Address (GA) (0x605) -
Page 51: Board Id Register (0X600)
The control and status registers exist for controlling or reading the status of the hardware. The addresses are as seen by the processor. In the following register descriptions, the bit significance is shown in little‐endian mode (i.e. from the viewpoint of the processor). MSB = D7, LSB = D0 3.2.1 Board ID Register (0x600) This reads back 0x56, the number assigned to the SBC622. 3.2.2 Board Revision Register (0x601) This provides information on the build state of the SBC622. Table 3-2 Board Revision Register (0x601) Bits Meaning D7 to D5 Number revision (artwork level) of the hardware build state: 1 = Revision 1 2 = Revision 2 3 = Revision 3 4 = Revision 4... -
Page 52: Board Configuration Register 3 (0X604)
3.2.5 Board Configuration Register 3 (0x604) The SBC622 only implements bit 7 of this register. Table 3-4 Board Configuration Register 3 (0x604) Meaning ISP DATA (read) 1 = Signal high 0 = Signal low RESERVED. Reads '0' Main Hub Write Protect 1 = Write-protected 0 = Write-enabled Main Boot Flash Write Enable by Software Lock 1 = Write-protected 0 = Writes enabled Flash Hard Drive installed... -
Page 53: Vpx Geographical Address (Ga) (0X605)
3.2.6 VPX Geographical Address (GA) (0x605) This register is not implemented on the SBC622. 3.2.7 Board Status Register 1 (Alarm Status Register) (0x606) The SBC622 only implements bit D7 of this register. Table 3-5 Board Status Register 1 (Alarm Status Register) (0x606) Meaning PEX8624 Fatal Error, GPI5 input 1 = Fatal error 0 = No error CPU too Hot (direct from CPU), GPI5 input 1 = Alarm 0 = No alarm... -
Page 54: Board Id String Registers (0X610 To 0X615)
The mapping of the bits in this register are as follows: Table 3-6 Watchdog Timer Control Status Register (WCSR) Field Bits Read or Write SERR/RST Select WCSR [16] Read/Write WDT Timeout Select WCSR [10..8] Read/Write WDT Enable WCSR [0] Read/Write All of these bits default to “0” after system reset. All other bits are Reserved. The ʺWDT Timeout Selectʺ field is used to select the timeout value of the ... -
Page 55: Control Register 1 (0X620)
3.2.14 Control Register 1 (0x620) The SBC622 only implements bit 0‐5, and bit 7 of this register. Table 3-8 Control Register 1 (0x620) Meaning Sticky BIT (used by BIOS to know when board has been power cycled) This bit is cleared to logic '0' by a power cycle Watchdog WDT_TOUT Reset enable 1 = Enabled 0 = Disabled (default) COM1/2 Buffer Enable... -
Page 56: Control Register 3 (0X622)
3.2.16 Control Register 3 (0x622) The SBC622 only implements bit 6 of this register. This controls the LEDs. Table 3-10 Control Register 3 (0x622) Bits Meaning BIT Pass (Green LED) 1 = LED lit 0 = LED off (default) BIT Fail (Red LED) 1 = LED lit (default) 0 = LED off BIT Status 1 (Yellow LED) 1 = LED lit 0 = LED off (default) -
Page 57: Timer Enable Register (0X60C)
3.2.20 Timer Enable Register (0x60C) The timers are enabled via the Timer Enable Register located at offset 0x0C from base I/O address 0x600. The mapping of the bits in this register are as follows: Table 3-11 TCSR1 Bit Mapping Field Bits Read or Write Description Timer 1 Enable TE[0] 0=disable, 1=enable Timer 2 Enable TE[1] 0=disable, 1=enable Timer 3 Enable TE[2] 0=disable, 1=enable Timer 4 Enable TE[3] 0=disable, 1=enable Read Latch Select TE[4]... -
Page 58: Timer 1 Value Register (0X634)
The ʺIRQ Enableʺ bit must be set to a ʺ1ʺ for the timer to be able to generate an interrupt. Each timer has an independently selectable clock source which is selected by the bit pattern in the ʺTimer x Clock Selectʺ field as follows: Table 3-14 Timer x Clock Select Clock Rate Bit 2 Bit 1 2 MHz 1 MHz 500 KHz 250 KHz The ʺRead Timerʺ bit selects between reading the current timer value or reading the timer load value when the timer data is read. Setting this bit to ʺ0ʺ will enable the reading of the current timer value. Setting this bit to a ʺ1ʺ will enable the reading of the value that was loaded into the timer. When the timer generates an interrupt, the ʺInterruptʺ bit is read as a ʺ1ʺ and is cleared with a write to the appropriate ʺTimer x IRQ Clearʺ register. Alternately, writing a ʺ0ʺ to TCSR[7] will also clear the interrupt. When this bit is read as a ʺ0ʺ, the timer has not created an interrupt. When a ʺ1ʺ is written into this bit, a single interrupt will be generated when the timerʹs ʺIRQ Enableʺ bit is enabled. 3.2.22 Timer 1 Value Register (0x634) Timer 1 is not implemented on SBC622. 3.2.23 Timer 2 Value Register (0x636) Timer 2 is not implemented on SBC622. -
Page 59: Timer 3 Irq Clear (T3Ic, 0X632)
3.2.28 Timer 3 IRQ Clear (T3IC, 0x632) The Timer 3 IRQ Clear (T3IC) register is used to clear an interrupt caused by Timer 3. Writing to this register, located at offset 0x32 from base I/O address 0x600, causes the interrupt from Timer 3 to be cleared. This can also be done by writing a ʺ0ʹ to TCSR3[7]. The T3IC register is write only and the data written is irrelevant. 3.2.29 Timer 4 IRQ Clear (T4IC, 0x633) The Timer 4 IRQ Clear (T4IC) register is used to clear an interrupt caused by Timer 4. Writing to this register, located at offset 0x33 from base I/O address 0x600, causes the interrupt from Timer 4 to be cleared. This can also be done by writing a ʺ0ʺ to TCSR4[7]. The T4IC register is write only and the data written is irrelevant. 3.2.30 CPLD GPIO LPC Interface Access Port and General Configuration Registers The SBC622 provides eight lines of General Purpose I/O through the P4/P6 connector. The lines are able to tolerate 5V input voltages and the signals are isolated whenever the SBC622 is powered down. Figure 3-2 CPLD GPIO Interface Access Max 5 V Onboard Logic... -
Page 60: Gpio Out Register (0X640)
All GPIO inputs are double sampled at 33 MHz before being used by any internal logic of the CPLD. For valid operation, input states must be valid for longer than 33 nS; pulses shorter than this may be missed due to the sampling of the inputs at 33 MHz. If rise and fall times of the GPIO are slow (>10 μS), then edge mode should not be used as any noise on the edges can cause false triggering. On really slow edges, software may need to filter the inputs. 3.2.31 GPIO Out Register (0x640) This holds the GPIO out data. Table 3-15 GPIO Out Register (0x640) GPIO Pin GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 NOTE This register is only cleared on a power cycle. 3.2.32 GPIO In Register (0x641) This reflects the current state of the GPIO pins regardless of whether they are ... -
Page 61: Gpio Direction Register (0X642)
3.2.33 GPIO Direction Register (0x642) This defines which GPIO pins are used as outputs and which are inputs. Table 3-17 GPIO Direction Register (0x642) Meaning GPIO7 direction 1 = Output 0 = Input (default) GPIO6 direction 1 = Output 0 = Input (default) GPIO5 direction 1 = Output 0 = Input (default) GPIO4 direction 1 = Output 0 = Input (default) -
Page 62: Gpio Level/Edge Register (0X644)
3.2.35 GPIO Level/Edge Register (0x644) This defines whether GPIO interrupts are edge or level sensitive. Table 3-19 GPIO Level/Edge Register (0x644) Meaning GPIO7 interrupt sensitivity 1 = Edge 0 = Level (default) GPIO6 interrupt sensitivity 1 = Edge 0 = Level (default) GPIO5 interrupt sensitivity 1 = Edge 0 = Level (default) GPIO4 interrupt sensitivity 1 = Edge 0 = Level (default) -
Page 63: Gpio Both Edges Register (0X646)
3.2.37 GPIO Both Edges Register (0x646) This allows the GPIO interrupts to be sensitive to both edges when in edge mode. Table 3-21 GPIO Both Edges Register (0x646) Meaning GPIO7 both edges 1 = Both edges 0 = Off (default) GPIO6 both edges 1 = Both edges 0 = Off (default) GPIO5 both edges 1 = Both edges 0 = Off (default) GPIO4 both edges... -
Page 64: Remote Ethernet Booting
3.3 Remote Ethernet Booting The SBC622 is capable of booting from a server using the 10/100/1000 Mbit Ethernet ports and the 10 GbE ports over a network utilizing the Intel Boot Agent. The Intel Boot Agent gives you the ability to remotely boot the SBC622 using the PXE protocol. The Ethernet must be connected through one of the front panel (RJ45) connectors to boot remotely. This feature allows users to create systems without the worry of disk drive reliability, or the extra cost of adding NAND Flash drives. BootWare • PXE boot support Features: • Unparalleled boot sector virus protection • Detailed boot configuration screens • Optional disabling of local boots • Dual‐boot option lets users select network or local booting 64 SBC622 Hardware Reference Manual... -
Page 65: Maintenance
Maintenance If a GE product malfunctions, please verify the following: 1. Software version resident on the product 2. System configuration 3. Electrical connections 4. Jumper or configuration options 5. Boards are fully inserted into their proper connector location 6. Connector pins are clean and free from contamination 7. No components or adjacent boards were disturbed when inserting or remov‐ ing the board from the chassis 8. Quality of cables and I/O connections If products must be returned, contact GE for a Return Material Authorization (RMA) Number. This RMA Number must be obtained prior to any return from Customer Care. RMA request forms can be obtained from: repairs.huntsville.ip@ge.com GE Customer Care is available at: 1‐800‐433‐2682 in North America, or +1‐780‐401‐7700 for international calls. Or, visit our website at: www.ge-ip.com Maintenance Prints User level repairs are not recommended. The drawings and diagrams in this manual are for reference purposes only. Maintenance 65... -
Page 66: A • Appendix A: Connectors And Pinouts
A • Appendix A: Connectors and Pinouts The SBC622 board contains six VPX Connectors defined by VITA 46. This appendix provides the contact signal assignments for VPX connectors located on the backplane, other rear I/O connectors and front panel connectors. In the tables listed in this appendix, active low signals are identified with a trailing ʹ‐ʹ, ʹ#ʹ, or ʹNʹ attached to the signal name. Active high signals in a signal pair may have a trailing ʹ+ʹ or ʹPʹ attached to the signal name. Appendix A: Connectors and Pinouts 66... -
Page 67: Figure A-1 Connector Locations Sbc622
Figure A-1 Connector Locations SBC622 Key 1 PMC1 Bridge Dual 10 GbE Pericom 82599 PMC2 Bridge E505 Pericom E504 PCIe Switch Quad Key 2 E503 PEX8648 E500 82580 E501 (On Back) E506 R215 E502 XDP Debug Port Debug P104 Port P103 LEDS Intel... -
Page 68: Vpx Connector Pin Assignments
A.1 VPX Connector Pin Assignments The 6U VPX backplane specification requires all backplane slots to have three guide pins: one above the P0 connector, one below the P2 connector, and one below the P6 connector. In addition to providing correct alignment, these pins are keyed to prevent cards being inserted into incorrect backplane slot(s) to avoid electrical incompatibility. The SBC622 board contains P0, P1, P2, P3, P4, P5 and P6 connectors per VITA 46.0, plus several connectors on the front panel. This appendix provides the contact signal assignments for these connectors. It also displays the signals for J0, J1, J2, J3, J4, J5, and J6 of the backplane pinouts when the SBC622 is plugged in. The power, ground, and signal assignments on the backplane connectors are defined by a combination of the following specifications: OpenVPX, VITA 46.0, VITA 46.4, VITA 46.6, and VITA 46.9. The following tables shows these signal assignments and pin fields for these connections. The VPX Connector table pin field assignments are structured according to the following color legend: Color Legend for VPX Pin Assignments Color Assignments Bright Yellow 5.0 V; Control Plane (UTP) Pale Yellow Control Plane (TP) Orange 12.0 V Lime... -
Page 69: Backplane P0/J0 Connector
A.1.1 Backplane P0/J0 Connector VPX P0/J0 connects to power management. Table A-1 Power Management (P0) P1 Pin Row G Row F Row E Row D Row C Row B Row A -12V Aux SYSRESET# NVMRO GA4# 3v3 Aux SMB_CLK SMB_DAT GA3# GA2# +12V Aux GA1# GA0# TRST# Table A-2 Power Management (J0) -
Page 70: Backplane P1/J1 Connector
A.1.2 Backplane P1/J1 Connector VPX P1/J1 connects to GbE 10 and the data plane. Table A-3 10 GbE (KX4) Data Plane (P1) P1 Pin Row G Row F Row E Row D Row C Row B Row A VPX_GDISC1# 10G1_T0- 10G1_T0+ 10G1_R0- 10G1_R0+ 10G1_T1- 10G1_T1+ 10G1_R1- 10G1_R1+ VBAT 10G1_T2- 10G1_T2+ 10G1_R2- 10G1_R2+... -
Page 71: Backplane P2/J2 Connector
A.1.3 Backplane P2/J2 Connector VPX P2/J2 connects to the PCIe Expansion plane. Table A-5 PCIe Expansion Plane (P2) P2 Pin Row G Row F Row E Row D Row C Row B Row A Reserved PCIE_TX0- PCIE_TX0+ PCIE_RX0- PCIE_RX0+ PCIE_TX1- PCIE_TX1+ PCIE_RX1- PCIE_RX1+ Reserved PCIE_TX2- PCIE_TX2+ PCIE_RX2- PCIE_RX2+ PCIE_TX3- PCIE_TX3+... -
Page 72: Backplane P3/J3 Connector
A.1.4 Backplane P3/J3 Connector VPX P3/J3 connects to PMC I/O Site 1 and COM1. Table A-7 PMC I/O (Site #1) and COM1 (P3) Row G Row G Row F Row E Row D Row C Row B Row A RS232 Mode RS 422 Mode COM1_RX COM1 RXD- J14-1 J14-3 J14-2 J14-4 J14-5... -
Page 73: Backplane P4/J4 Connector
A.1.5 Backplane P4/J4 Connector VPX P4/J4 connects to XMC I/O Site 1, control plane, COM2, GbE, GPIO and USB. Table A-9 XMC I/O (Site #1), COM2, Control Plane, and Misc. I/O (P4) Row G Row G Row F Row E Row D Row C Row B Row A RS232 Mode RS 422 Mode COM2_RX COM2_RXD- J16-A5 J16-B5... -
Page 74: Backplane P5/J5 Connector
A.1.6 Backplane P5/J5 Connector VPX P5/J5 connects to PMC I/O Site 2 and the Audio/Speaker. Table A-11 PMC I/O (Site #2), Audio, Speaker (P5) Row G Row F Row E Row D Row C Row B Row A HDA_SDO J24-1 J24-3 J24-2 J24-4 J24-5 J24-7 J24-6 J24-8 HDA_RST# J24-9 J24-11 J24-10 J24-12 J24-13... -
Page 75: Backplane P6/J6 Connector
A.1.7 Backplane P6/J6 Connector VPX P6/J6 connects to XMC I/O Site 2, SATA, DVI/VGA, USB andGPIO. Table A-13 XMC I/O (Site #2), Video, USB, SATA (P6) Row G Row F Row E Row D Row C Row B Row A J26-A5 J26-B5 J26-D5 J26-E5 J26-A7 J26-B7 J26-D7 J26-E7 VGA_DDC_CLK J26-A9 J26-B9 J26-D9 J26-E9 J26-A15... -
Page 76: Serial Port Connector Rj45 (J10)
A.2 Serial Port Connector RJ45 (J10) The COM 3 Serial Port Connector located on the Front Panel, is a standard RJ45 connector as shown in the figure and table below: Figure A-3 Serial Connector (J10) Table A-15 Serial Connector Pinout (J10) RS232 (Default) Mode RS422 Mode DCD# RXD+ RTS# RTS- TXD+ TXD- RXD- CTS+ CTS# CTS- DTR# RTS+ NOTE: See the appropriate table of jumper and switch settings for configuring. A cable is available (PN:42G7602-0003) to convert from the RJ45 connector to a standard DB9 Male connector. -
Page 77: Gigabit Ethernet Connector And Pinout (J2) 82580
A.4 Gigabit Ethernet Connector and Pinout (J2) 82580 The pinout diagram for the Gigabit Ethernet connector is shown in the following figure and table: Figure A-5 GbE Connector (J2) Table A-17 Ethernet Connectors 10/100/1000 Mbit (J2) Signals Signals MDI0+ TX/RX0+ MDI0- TX/RX0- MDI1+ TX/RX1+ MDI2+ TX/RX2+ MDI2- TX/RX2- MDI1- TX/RX1- MDI3+ TX/RX3+ MDI3- TX/RX3- 77 SBC622 Hardware Reference Manual... -
Page 78: Pmc Site 1 Connector And Pinouts
A.5 PMC Site 1 Connector and Pinouts The PCI Mezzanine Card (PMC) carries the same signals as the PCI standard; however, the PMC standard uses a completely different form factor. Table A‐18 through Table A‐21 are the pinouts for the XMC/PMC connectors (J11, J12, J13 and J14). A.5.1 PMC Connector and Pinouts (J11) Figure A-6 PMC Site 1 Connector and Pinouts (J11) Table A-18 PMC Site 1 Connector Pinouts (J11) PMC Connector (J11) PMC Connector (J11) Left Side Right Side Left Side... -
Page 79: Pmc Connector And Pinouts (J12)
A.5.2 PMC Connector and Pinouts (J12) Figure A-7 PMC Site 1 Connector and Pinouts (J12) Table A-19 PMC Site 1 Connector Pinouts (J12) PMC Connector (J12) PMC Connector (J12) Left Side Right Side Left Side Right Side Name Name Name Name +12 V JTAG_TRST... -
Page 80: Pmc Connector And Pinouts (J13)
A.5.3 PMC Connector and Pinouts (J13) Figure A-8 PMC Site 1 Connector and Pinouts (J13) Table A-20 PMC Site 1 Connector Pinouts (J13) PMC Connector (J13) PMC Connector (J13) Left Side Right Side Left Side Right Side Name Name Name Name AD[48] CBE[7]#... -
Page 81: Pmc Connector And Pinouts (J14)
A.5.4 PMC Connector and Pinouts (J14) Figure A-9 PMC Site 1 Connector and Pinouts (J14) Table A-21 PMC Site 1 Connector Pinouts (J14) Connected To Connected To Connected To Connected To P3-E1 P3-B1 P3-D1 P3-A1 P3-F2 P3-C2 P3-E2 P3-B2 P3-E3 P3-B3 P3-D3 P3-A3... -
Page 82: Xmc Connectors Site 1
A.6 XMC Connectors Site 1 A.6.1 Pinouts for XMC Connector Site 1 (J15) Figure A-10 XMC Site 1 Connector and Pinouts (J15) Table A-22 XMC1 Site 1 Connector Pinouts (J15) Row A Row B Row C Row D Row E Row F RX0+ RX0-... -
Page 83: Pinouts For Xmc Connector Site 1 (J16)
A.6.2 Pinouts for XMC Connector Site 1 (J16) Figure A-11 XMC Site 1 Connector (J16) Table A-23 XMC1 Site 1 Connector Pinouts (J16) Row F Row E Row D Row C Row B Row A P4-A1 P4-B1 P4-D1 P4-E1 P4-B2 P4-C2 P4-E2 P4-F2... -
Page 84: Pmc Site 2 Connectors (J21, J22, J23, J24)
A.7 PMC Site 2 Connectors (J21, J22, J23, J24) The PCI Mezzanine Card (PMC) carries the same signals as the PCI standard; however, the PMC standard uses a completely different form factor. Table A‐24 through Table A‐27 are the pinouts for the PMC connectors (J21, J22, J23 and J24). A.7.1 PMC Connector and Pinouts (J21) Figure A-12 PMC Site 2 Connector and Pinouts (J21) Table A-24 PMC Site 2 Connector Pinouts (J21) PMC Connector (J21) PMC Connector (J21) Left Side Right Side Left Side... -
Page 85: Pmc Connector And Pinouts (J22)
A.7.2 PMC Connector and Pinouts (J22) Figure A-13 PMC Site 2 Connector and Pinouts (J22) Table A-25 PMC Site 2 Connector Pinouts (J22) PMC Connector (J22) PMC Connector (J22) Left Side Right Side Left Side Right Side Name Name Name Name +12 V JTAG_TRST... -
Page 86: Pmc Connector And Pinouts (J23)
A.7.3 PMC Connector and Pinouts (J23) Figure A-14 PMC Site 2 Connector and Pinouts (J23) Table A-26 PMC Site 2 Connector Pinouts (J23) PMC Connector (J23) PMC Connector (J23) Left Side Right Side Left Side Right Side Name Name Name Name AD[48] CBE[7]#... -
Page 87: Pmc Connector And Pinouts (J24)
A.7.4 PMC Connector and Pinouts (J24) Figure A-15 PMC Site 2 Connector and Pinouts (J24) Table A-27 PMC Connector and Pinouts (J24) Connected To Connected To Connected To Connected To P5-E1 P5-B1 P5-D1 P5-A1 P5-F2 P5-C2 P5-E2 P5-B2 P5-E3 P5-B3 P5-D3 P5-A3 P5-F4... -
Page 88: Pinouts For Xmc Connector Site 2 (J25)
A.7.5 Pinouts for XMC Connector Site 2 (J25) Figure A-16 XMC Site 2 Connector and Pinouts (J25) Table A-28 XMC2 Site 2 Connector Pinouts (J25) Row A Row B Row C Row D Row E Row F RX0+ RX0- 3.3V RX1+ RX1- TRST#... -
Page 89: Pinouts For Xmc Connector Site 2 (J26)
A.7.6 Pinouts for XMC Connector Site 2 (J26) Figure A-17 XMC Site 2 Connector and Pinouts (J26) Table A-29 Pinouts for XMC Connector Site 2 (J26) Row F Row E Row D Row C Row B Row A P6-A1 P6-B1 P6-D1 P6-E1 P6-B2... -
Page 90: B • Appendix B: Bios Setup Utility
B • Appendix B: BIOS Setup Utility This appendix gives a brief description of the setup options in the system BIOS firmware. Due to the custom nature of GE’s SBCs, your BIOS firmware, options may vary from the options discussed in this appendix. To Access the First Boot setup screen, press the key at the beginning of boot. To access the setup screens, press the key at the beginning of boot. B.1 First Boot Menu The SBC622 has a First Boot menu enabling the user to, on a one time basis, select a drive device to boot from. This feature is useful when installing from a bootable disk. For example, when installing an operating system from a CD, enter the First Boot menu and use the arrows keys to highlight ATAPI CD‐ROM Drive. Press to continue with system boot. ENTER This feature is accessed by pressing the key at the very beginning of the boot cycle. The selection made from this screen applies to the current boot only, and will not be used during the next boot‐up of the system. If you have trouble accessing this feature, disable the QuickBoot Mode in the Main BIOS firmware, setup screen. Exit, saving changes and retry accessing the First Boot menu. Table B-1 BIOS Firmware, First Boot Menu Please select boot device: SanDisk U3 Cruzer Micro 2.18... -
Page 91: Main Menu
B.2 Main Menu The Main next‐generation BIOS firmware, setup menu screen has two main areas. The left frame displays the options that can be configured. The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white and a text message in the right frame gives a brief description of the option. The Main menu reports the BIOS firmware, revision, processor type and clock speed, and allows the user to set the system’s clock and calendar. Use the left and right arrow keys to select other screens. NOTE Below is a sample of the Main screen. The information displayed on your screen will reflect your actual system. Table B-2 BIOS Main Menu Aptio Setup Utility - Copyright (C) 2009 American Megatrends, Inc. Main Advanced Chipset... -
Page 92: Advanced Setup Menu
B.3 Advanced Setup Menu The Advanced BIOS firmware, Setup menu allows the user to configure some CPU settings, the IDE bus, SCSI devices and other external devices and internal drives. Select the Advanced tab from the setup screen to enter the Advanced BIOS firmware, Setup screen. You can select the items in the left frame of the screen, such as Super I/O Configuration, to go to the sub menu for that item. You can display an Advanced BIOS firmware, Setup option by highlighting it using the <Arrow> keys. A sample of the Advanced BIOS firmware, Setup screen is shown below. NOTE Changes in this screen can cause the system to malfunction. If problems are noted after changes have been made, reboot the system and access the BIOS firmware. From the Exit menu select ‘ Load ’... -
Page 93: Chipset Setup Menu
B.4 Chipset Setup Menu Select the various options for chipsets located in the system (for example, the CPU configuration and configurations for the North and South Bridge). The settings for the chipsets are processor dependent and care must be used when changing settings from the defaults set at the factory. Below is a sample of the Chipset Setup screen; the actual options on your system may vary. NOTE Changes in this screen can cause the system to malfunction. If problems are noted after changes have been made, reboot the system and access the BIOS firmware. From the Exit menu select ‘Load Failsafe Defaults’... -
Page 94: Enabling/Disabling The Gbe Boot-From-Lan Bios Firmware
B.4.1 Enabling/Disabling the GbE boot-from-LAN BIOS firmware The Gigabit Ethernet boot‐from‐LAN BIOS firmware, provides support for booting over the network. NOTE In order to boot from the network, some operating systems require that the network driver be set to “boot” within the Control Panel. The Gigabit Ethernet boot‐from‐LAN BIOS firmware, defaults to Disabled in the BIOS firmware, Setup Utility. The Chipset menu of the BIOS firmware, Setup Utility allows the boot‐from‐LAN BIOS firmware, to be Enabled or Disabled. Table B‐4 on page 93 shows the Chipset Menu. Use the arrow keys to highlight the Onboard Device Configuration. Select ʹGigE Option ROMʹ in the submenu’s list and enter <+> until the option is set to Enabled or Disabled. Press F10 to Save and Exit the BIOS firmware, Setup Utility. Appendix B: BIOS Setup Utility 94... -
Page 95: Boot Setup Menu
B.5 Boot Setup Menu Use the Boot Setup menu to set the priority of the boot devices, including booting from a remote network. The devices shown in this menu are the bootable devices detected during POST. If a drive is installed that does not appear, verify the hardware installation. Also available in this screen are “Boot Settings” which allow the user to set how the basic system will act, for example, support for PS/2 mouse and whether to use “Quick Boot” or not. Table B-5 BIOS Boot Menu Aptio Setup Utility - Copyright (C) 2009 American Megatrends, Inc. Main Advanced Chipset Boot Security Save & Exit Boot Configuration Enables/Disables Quiet Boot UEFI Boot [Disabled] option. -
Page 96: Security Setup Menu
B.6 Security Setup Menu The Security setup provides both a Supervisor and a User password. If you use both passwords, the Supervisor password must be set first. The system can be configured so that all users must enter a password every time the system boots or when setup is executed, using either the Supervisor password or User password. Table B-6 BIOS Security Menu Aptio Setup Utility - Copyright (C) 2009 American Megatrends, Inc. Main Advanced Chipset Boot Security Save & Exit Password Description Set Setup Administrator Password. If ONLY the Administrator’s password is set, then this only limits access to Setup and is only asked for when entering Setup. -
Page 97: Save & Exit Menu
B.7 Save & Exit Menu Select the Save & Exit tab from the setup screen to enter the Save & Exit BIOS firmware, Setup screen. You can display a Save & Exit BIOS firmware, Setup option by highlighting it using the <Arrow> keys. The Save & Exit BIOS firmware, Setup screen is shown below. Table B-7 BIOS Save & Exit Menu Aptio Setup Utility - Copyright (C) 2009 American Megatrends, Inc. Main Advanced Chipset Boot Security Save & Exit Save Changes and Exit Enables/Disables Quiet Boot Discard Changes and Exit option. -
Page 98: C • Appendix C: Specifications And Physical Description
C • Appendix C: Specifications and Physical Description The SBC622 assembly offers the ability of targeting multiple levels of environmental support. The following tables list Level 1, 2, 4, and 5 support: C.1 Specifications Table C-1 Environmental Specifications by Level Level 1 Level 2 Level 4 Level 5 Cooling Method Convection Convection Conduction Conduction Conformal Coating Optional Standard Standard Standard 0°C το 55°C -20°C το... - Page 99 © 2011 GE Intelligent Platforms Embedded Systems, Inc. All rights reserved. Information Centers For more information, please visit * indicates a trademark of GE Intelligent Platforms, Inc. and/or its affiliates. All other the GE Intelligent Platforms Embedded Americas: trademarks are the property of their respective...