hit counter script

Ret; Ret.d - Epson S1C17 Series Manual

Cmos 16-bit single chip microcontroller
Hide thumbs Also See for S1C17 Series:
Table of Contents

Advertisement

7 DETAILS OF INSTRUCTIONS

ret

ret.d

Function
Return from subroutine
Standard)
Extension 1) Unusable
Extension 2) Unusable
15 14 13 12 11 10
Code
0
0
0
|
|
0
0
0
|
|
IE
C
V
Flag
|
|
Mode
CLK
ret
ret.d
Description
(1) Standard
ret
Restores the PC value (return address) that was saved into the stack when the call/calla
instruction was executed for returning the program flow from the subroutine to the routine that
called the subroutine. The SP is incremented by four bytes.
If the SP has been modified in the subroutine, it is necessary to return the SP value before
executing the ret instruction.
(2) Delayed branch (d bit (bit 7) = 1)
ret.d
For the ret.d instruction, the next instruction becomes a delayed slot instruction. A delayed
slot instruction is executed before the program returns from the subroutine. Interrupts are
masked in intervals between the ret.d instruction and the next instruction, so no interrupts
occur.
Example
ret.d
add
%r0,%r1
Caution
When the ret.d instruction (delayed branch) is used, be careful to ensure that the next instruction
is limited to those that can be used as a delayed slot instruction. If any other instruction is executed,
the program may operate indeterminately. For the usable instructions, refer to the instruction list in
the Appendix.
7-114
pc ← A[sp](23:0), sp ← sp + 4
9
8
7
6
|
0
0
0
0
1
0
0
|
|
|
|
|
|
|
0
0
0
0
1
1
0
|
|
|
|
|
|
Z
N
|
|
Three cycles
Two cycles (when a one-cycle delayed slot instruction follows), Three cycles (other)
; Executed before return from the subroutine
Seiko Epson Corporation
5
4
3
2
1
0
|
1
0
0
0
0
0
|
|
|
|
|
|
1
0
0
0
0
0
|
|
|
|
|
ret
ret.d
S1C17 CORE MANUAL
(REV. 1.2)

Advertisement

Table of Contents
loading

Table of Contents