Spa Architecture; 4-Port Oc-3C/Stm-1 Pos Spa Architecture; Path Of A Packet In The Ingress Direction; Path Of A Packet In The Egress Direction - Cisco ASR 1000 Configuration Manual
Aggregation services routers sip and spa software
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- Software configuration manual (602 pages) ,
- Configuration manual (126 pages) ,
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SPA Architecture
SPA Architecture
This section provides an overview of the architecture of the POS SPAs and describes the path of a packet
in the ingress and egress directions. Some of these areas of the architecture are referenced in the SPA
software and can be helpful to understand when troubleshooting or interpreting some of the SPA CLI
and show command output.
4-Port OC-3c/STM-1 POS SPA Architecture
Figure 12-1
shows the four ports that are supported by the 4-Port OC-3c/STM-1 POS SPA only.
Figure 12-1
Optics
Every incoming and outgoing packet on the 4-Port OC-3c/STM-1 POS SPA goes through the
SONET/SDH framer and field-programmable gate array (FPGA) devices.
Path of a Packet in the Ingress Direction
The following steps describe the path of an ingress packet through the 4-Port OC-3c/STM-1 POS SPA:
1.
2.
3.
4.
Path of a Packet in the Egress Direction
The following steps describe the path of an egress packet through the 4-Port OC-3c/STM-1 POS SPA:
1.
2.
3.
Cisco ASR 1000 Series Aggregation Services Routers SIP and SPA Software Configuration Guide
12-6
identifies some of the hardware devices that are part of the POS SPA architecture. The figure
4-Port OC-3c/STM-1 POS SPA Architecture
SONET/SDH
Streams
SONET/SDH
Framer
The framer receives SONET/SDH streams from the SFP optics, extracts clocking and data, and
processes the section, line, and path overhead.
The framer extracts the POS frame payload and verifies the frame size and frame check sequence
(FCS).
The framer passes valid frames to the field-programmable gate array (FPGA) on the SPA.
The FPGA on the SPA transfers frames to the host through the SPI4.2 bus for further processing and
switching.
The host sends packets to the FPGA on the SPA using the SPI4.2 bus.
The FPGA on the SPA stores the data in the appropriate channel first-in first-out (FIFO) queue.
The FPGA on the SPA passes the packet to the framer.
Chapter 12
Packets
Packets
FPGA
Overview of the POS SPAs
SPA
Connector
To
Host
From
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Troubleshooting
