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Hitachi H8/3152 Hardware Manual
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Hitachi H8/3152 Hardware Manual

Hitachi H8/3152 Hardware Manual

Single-chip microcomputer h8/3150 series
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ADE-602-182
Rev. 1.0
3/11/99
Hitachi, Ltd.
Hitachi Single-Chip Microcomputer
H8/3150 Series
H8/3152
HD6483152
H8/3153
HD6483153
H8/3155
HD6483155
H8/3156
HD6483156
H8/3158
HD6483158
Hardware Manual

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Summary of Contents for Hitachi H8/3152

  • Page 1 Hitachi Single-Chip Microcomputer H8/3150 Series H8/3152 HD6483152 H8/3153 HD6483153 H8/3155 HD6483155 H8/3156 HD6483156 H8/3158 HD6483158 ADE-602-182 Hardware Manual Rev. 1.0 3/11/99 Hitachi, Ltd.
  • Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
  • Page 3 Preface The H8/3150 series is a single-chip microcomputer built around a high-speed H8/300 CPU core. On-chip facilities include an EEPROM, a ROM, a RAM, two I/O ports, a random number generator (RNG), and a watchdog timer (WDT). On-chip EEPROM makes the H8/3150 series ideal for applications requiring nonvolatile data storage, including smart cards and portable data banks.

  • Page 4: Table Of Contents

    Contents Section 1 Overview..................1 Overview..........................Block Diagram........................Pin Arrangement and Functions ..................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions......................Section 2 CPU....................9 Overview..........................2.1.1 Features ........................ 2.1.2 CPU Registers ...................... 11 Register Descriptions......................2.2.1 General Registers....................12 2.2.2 Control Registers....................
  • Page 5 2.7.4 Reset Start Timing....................41 Power-Down State ......................42 2.8.1 Overview ......................42 2.8.2 Transition to Sleep Mode ..................2.8.3 Exit from Sleep Mode ..................43 Section 3 Memory Maps.................. 45 Section 4 Random Number Generator (RNG)..........51 Overview..........................51 4.1.1 Features ........................
  • Page 6 Section 8 EEPROM ..................77 Overview..........................77 8.1.1 Features ........................ 77 8.1.2 Block Diagram...................... 78 8.1.3 Memory Organization ..................79 8.1.4 Register Configuration ..................Register Descriptions......................8.2.1 EEPROM Control Register (ECR)............... 8.2.2 EEPROM Protection Register (EPR) ..............EEPROM Read Operation ....................83 EEPROM Write and Erase Operations................
  • Page 7 12.2.2 AC Characteristics (5 V, CPU operates at half of the external clock frequency) 110 12.2.3 DC Characteristics (5 V, CPU operates at the external clock frequency).... 111 12.2.4 AC Characteristics (5 V, CPU operates at the external clock frequency).... 112 12.2.5 DC Characteristics (3 V, CPU operates at half of the external clock frequency) 114 12.2.6 AC Characteristics (3 V, CPU operates at half of the external clock frequency) 115 12.2.7 DC Characteristics (3 V, CPU operates at the external clock frequency)....

  • Page 8: Section 1 Overview

    Section 1 Overview Overview The H8/3150 series is a single-chip microcomputer unit (MCU) built around a high-speed H8/300 CPU core. An EEPROM, a ROM, a RAM, two I/O ports, a random number generator (RNG), and a watchdog timer (WDT) are integrated onto the H8/3150 series chip. Operating at a maximum 5-MHz internal clock rate at 5 V, the H8/300 CPU rapidly executes bit- manipulation instructions, arithmetic and logic instructions, and data transfer instructions.
  • Page 9 On-chip memory EEPROM H8/3152: 8 kbytes + 256 bytes (32 bytes x (256 + 8) pages) H8/3153: 16 kbytes + 512 bytes (64 bytes x (256 + 8) pages) H8/3155: 1 kbyte + 128 bytes (16 bytes x (64 + 8) pages)
  • Page 10 Table 1.1 Features (cont) Item Specification • Watchdog timer Issues a UDF interrupt at a required interval. (WDT) • Issues an EWE interrupt before an EEPMOV instruction is executed. (option) • Stops the on-chip functions when the halt flag is set. •...

  • Page 11: Block Diagram

    Block Diagram Figure 1.1 shows an internal block diagram of the H8/3150 series. I/O-1/IRQ I/O port I/O-2/IRQ H8/300 CPU Address bus Data bus System control logic Security logic EEPROM Clock divider Figure 1.1 Block Diagram...

  • Page 12: Pin Arrangement And Functions

    Pin Arrangement and Functions 1.3.1 Pin Arrangement Figure 1.2 shows the standard COT (chip on tape) pattern of the H8/3150 series. Figure 1.3 shows the bonding pad arrangement of the wafer product. The COT is mounted on a tape. I/O-1/IRQ Figure 1.2 Standard COT Pattern (Electrode Surface)
  • Page 13 I/O-1/IRQ I/O-2/IRQ User PAD Note: This figure shows the relative locations of the bonding pads on the chip. For accurate locations and chip dimensions, refer to the separately supplied specifications. Figure 1.3 Bonding Pad Arrangement...

  • Page 14: Pin Functions

    1.3.2 Pin Functions Table 1.2 lists the functions of the H8/3150 series pins. Table 1.2 Pin Functions Type Symbol Name and Description Power supply Power supply: 4.5 V to 5.5 V or 2.7 V to 3.3 V Ground: 0 V Clock Clock: External clock input RES*...

  • Page 15: Section 2 Cpu

    Section 2 CPU Overview The H8/3150 series has an H8/300 CPU: an 8-bit central processing unit with a speed-oriented architecture featuring sixteen 8-bit general registers (or eight 16-bit general registers). This section describes the CPU features and functions, including a concise description of the addressing modes and instruction set.
  • Page 16 • High-speed operation  Every frequently-used instruction is executed in two to four states  Maximum clock rate is 5-MHz internal clock (at 5 V) • 8- or 16-bit register-register add or subtract: 0.4 µs • 8 × 8-bit multiply: 2.8 µs •...

  • Page 17: Cpu Registers

    2.1.2 CPU Registers Figure 2.1 shows the register structure of the H8/300 CPU. There are two groups of registers: general registers and control registers. General registers (Rn) (SP) Control registers (CR) Legend: Stack pointer Program counter CCR: Condition code register Interrupt mask bit User bit Half-carry flag...

  • Page 18: Register Descriptions

    Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
  • Page 19 (2) Condition Code Register (CCR): This 8-bit register contains internal CPU status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts when set to 1. This bit is set to 1 at the beginning of exception handling.

  • Page 20: Initial Register Values

    2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is loaded from the vector table and the I bit in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized.

  • Page 21: Data Formats In General Registers

    2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2.3. Data type Register no. Data format 1-bit data Don’t care 1-bit data Don't care Byte data Don’t care Byte data Don’t care Word data...

  • Page 22: Memory Data Formats

    2.3.2 Memory Data Formats Figure 2.4 indicates the data formats in memory. Word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0. If an odd address is specified, no address error occurs but the access is performed at the preceding even address.

  • Page 23: Addressing Modes

    Addressing Modes 2.4.1 Addressing Modes The H8/300 CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes Addressing Mode Symbol Register direct Register indirect Register indirect with displacement @(d:16, Rn) Register indirect with post-increment @Rn+...
  • Page 24 (4) Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn: • Register indirect with post-increment— @Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand.

  • Page 25: Effective Address Calculation

    (8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255).
  • Page 26 Table 2.2 Effective Address Calculation Addressing Mode, Effective Address Instruction Format Calculation Effective Address Register direct Rn regn regm regm regn Operands are contained in registers m and n Register indirect 16-bit register contents Register indirect with displacement @(d:16, Rn) 16-bit register contents 16-bit register contents disp...
  • Page 27 Table 2.2 Effective Address Calculation (cont) Addressing Mode, Effective Address Instruction Format Calculation Effective Address Absolute address @aa:8 H'FF Absolute address @aa:16 Immediate #xx:8 Operand is 1-byte immediate data Immediate #xx:16 Operand is 2-byte immediate data PC-relative @(d:8, PC) PC contents Sign extension disp disp...

  • Page 28: Instruction Set

    Instruction Set The H8/3150 series can use a total of 55 instructions, shown grouped by function in table 2.3. Note: The H8/300 CPU has 57 basic instructions, but the H8/3150 series uses only 55 of them. The MOVFPE and MOVTPE instructions are not used. Table 2.3 Instruction Set Function...
  • Page 29 Tables 2.4 to 2.11 give a concise summary of the instructions in each functional group. The following notation is used in these tables to describe the operations performed. Operation Notation General register (destination) General register (source) General register (EAd) Destination operand (EAs) Source operand Condition code register...

  • Page 30: Data Transfer Instructions

    2.5.1 Data Transfer Instructions Table 2.4 describes the data transfer instructions. Table 2.4 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
  • Page 31 Figure 2.5 shows the object code formats of the data transfer instructions. Rm → Rn @Rm ← → Rn @(d:16, Rm) ← → Rn disp @Rm+ → Rn, Rn → @–Rm @aa:8 ← → Rn @aa:16 ← → Rn #xx8 → Rn #xx16 →...

  • Page 32: Arithmetic Operations

    2.5.2 Arithmetic Operations Table 2.5 describes the arithmetic instructions. Table 2.5 Arithmetic Instructions Instruction Size* Function Rd ± Rs → Rd, Rd + #IMM → Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register.

  • Page 33: Logic Operations

    2.5.3 Logic Operations Table 2.6 describes the instructions that perform logic operations. Table 2.6 Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data.
  • Page 34 Figure 2.6 shows the object code formats of the arithmetic, logic, and shift instructions. ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT MULXU, DIVXU ADD, ADDX, SUBX, CMP (#xx:8) AND, OR, XOR (Rm) AND, OR, XOR (#xx:8) SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Legend:...

  • Page 35: Bit Manipulations

    2.5.5 Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Table 2.8 Bit-Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
  • Page 36 Table 2.8 Bit-Manipulation Instructions (cont) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR Exclusive-ORs the C flag with a specified bit in a general register or memory and stores the result in the C flag. C ⊕ [~ (<bit-No.> of <EAd>)] → C BIXOR Exclusive-ORs the C flag with the inverse of a specified bit in a general register or memory and stores the result in the C flag.
  • Page 37 Figure 2.7 shows the object code formats of the bit manipulation instructions. BSET, BCLR, BNOT, BTST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: register direct (Rm) Operand: absolute (@aa:8)
  • Page 38 BIAND, BIOR, BIXOR, BILD, BIST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: absolute(@aa:8) Bit No.: immediate (#xx:3) Legend: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Object Code Formats (cont)

  • Page 39: Branching Instructions

    2.5.6 Branching Instructions Table 2.9 describes the branching instructions. Table 2.9 Branching Instructions Instruction Size Function — Branches to a specified address if condition cc is true. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false)
  • Page 40 Figure 2.8 shows the object code formats of the branching instructions. disp JMP (@Rm) JMP (@aa:16) JMP (@@aa:8) disp JSR (@Rm) JSR (@aa:16) JSR (@@aa:8) Legend: Operation field Condition field Register field disp: Displacement abs: Absolute address Figure 2.8 Branching Instruction Object Code Formats...

  • Page 41: System Control Instructions

    2.5.7 System Control Instructions Table 2.10 describes the system control instructions. Table 2.10 System Control Instructions Instruction Size* Function — Returns from an exception-handling routine. SLEEP — Causes a transition to the power-down state. Rs → CCR, #IMM → CCR Moves immediate data or general register contents to the condition code register.

  • Page 42: Eeprom Write Instruction

    Figure 2.9 shows the object code formats of the system control instructions. RTE, SLEEP, NOP LDC, STC (Rn) ANDC, ORC, XORC, LDC (#xx:8) Legend: Operation field Register field IMM: Immediate data Figure 2.9 System Control Instruction Object Code Formats 2.5.8 EEPROM Write Instruction Table 2.11 describes the EEPROM write instruction.

  • Page 43: Operating States

    Figure 2.10 shows the object code format of the EEPROM write instruction. EEPMOV Legend: op: Operation field Figure 2.10 EEPROM Write Instruction Object Code Format Operating States 2.6.1 Overview The CPU operates in three states: the program execution state, exception-handling state, and power-down state.

  • Page 44: Power-Down State

    Program execution state End of exception SLEEP instruction handling RES = 0 I/O-1/IRQ = 0 or I/O-2/IRQ Exception-handling state Sleep mode RES = 1 RES = 0 Power-down state Reset state Figure 2.12 State Transitions 2.6.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 2.6.3 Exception-Handling State This is a transitory state entered in response to a reset or interrupt.

  • Page 45: Exception Handling

    Exception Handling 2.7.1 Overview In the H8/3150 series, exception handling is performed in response to a reset or interrupt. Table 2.12 summarizes the exception handling priority order and timing. Table 2.13 describes the exception vector table. Table 2.12 Exception Handling Priority Order and Timing Start of Exception Handling Mask by Priority...

  • Page 46: Reset

    2.7.2 Reset The H8/3150 series begins reset exception handling when the RES input changes from low to high. RES must also be low whenever power is switched on or off. At power-up, RES must be held low for at least 20 external clock cycles after the input clock signal (CLK) stabilizes. Similarly, when the chip is reset during operation, RES must be held low for at least 20 external clock cycles.

  • Page 47: Reset Start Timing

    SP–4 SP (R7) CCR* SP–3 SP+1 SP–2 SP+2 SP–1 SP+3 Even SP (R7) SP+4 address Stack area Before After Save on stack Legend: : Upper 8 bits of program counter (PC) : Lower 8 bits of program counter (PC) CCR: Condition code register Stack pointer Notes: 1.

  • Page 48: Power-Down State

    Power-Down State 2.8.1 Overview The H8/3150 series has a sleep mode, a power-down state in which CPU functions are halted to conserve power. Table 2.14 summarizes the conditions for transition to sleep mode, the state of the CPU and on- chip peripheral modules in sleep mode, and the conditions for exit from sleep mode.

  • Page 49: Transition To Sleep Mode

    DDR7 ← 0 DDR6 ← 0 Program execution state (EN = 0) CCR(I) ← 0 Execute SLEEP instruction Sleep mode Figure 2.14 Transition to Sleep Mode Note: When sleep mode is entered, set DDR to 0 to use the pins as I/O input ports before executing a SLEEP instruction.
  • Page 50 Sleep mode I/O-1/IRQ = low I/O-2/IRQ = low Execution of interrupt- handling routine RTE instruction Figure 2.15 Recovery from Sleep Mode Note: The RES, I/O-1/IRQ, and I/O-2/IRQ signals must be held high during sleep mode. CLK = 0 MHz to t CCR I bit I/O-1/IRQ or I/O-2/IRQ...

  • Page 51: Section 3 Memory Maps

    H'FFFC TCSR Registers for WDT H'FFFD TCNT H'FFFE Registers for I/O port H'FFFF : Access possible : Access not possible Note: Shaded areas are unavailable to the user. User programs must not access these areas. Figure 3.1 H8/3152 Memory Map...
  • Page 52 Access Address Address Word Byte H'0000 Exception vectors Reset H'0000/H'0001 H'0002/H'0003 H'0004/H'0005 H'0006/H'0007 H'0008/H'0009 EWE interrupt H'000A/H'000B (Read (Read UDF interrupt H'000C/H'000D (32 kbytes) only) only) H'7FFF Switched by EPR H'8000 (PBM bit) EEPROM EEPROM data area protection area (Read (16 kbytes) PBM = 1 PBM = 0 H'BFFF...
  • Page 53 Access Address Address Word Byte H'0000 Exception vectors Reset H'0000/H'0001 H'0002/H'0003 H'0004/H'0005 H'0006/H'0007 (Read (Read H'0008/H'0009 (16 kbytes) only) only) H'3FFF EWE interrupt H'000A/H'000B UDF interrupt H'000C/H'000D H'6000 Switched by EPR EEPROM (PBM bit) EEPROM data area protection area (Read (1 kbyte) H'63FF only)
  • Page 54 Access Address Address Word Byte H'0000 Reset H'0000/H'0001 Exception vectors H'0002/H'0003 H'0004/H'0005 H'0006/H'0007 (Read (Read H'0008/H'0009 only) only) (16 kbytes) EWE interrupt H'000A/H'000B UDF interrupt H'000C/H'000D H'3FFF H'6000 Switched by EPR EEPROM (PBM bit) EEPROM data area protection area (Read (2 kbytes) H'67FF only)
  • Page 55 Access Address Address Word Byte H'0000 Exception vectors Reset H'0000/H'0001 H'0002/H'0003 H'0004/H'0005 H'0006/H'0007 H'0008/H'0009 EWE interrupt H'000A/H'000B (Read (Read UDF interrupt H'000C/H'000D (46 kbytes) only) only) H'B7FF Switched by EPR H'B800 (PBM bit) EEPROM EEPROM data area (Read protection area (16 kbytes) PBM = 1 PBM = 0 only)

  • Page 56: Random Number Generator (Rng)

    Section 4 Random Number Generator (RNG) Overview The H8/3150 series has a random number generator (RNG) which generates 16-bit random numbers. A random number generated by the RNG is written to a 16-bit register. Using the RNG enables a unique value to be generated inside the chip, which improves the system security. 4.1.1 Features •...
  • Page 57 Register Descriptions 4.2.1 RNG Control Status Register (RCSR) RCSR is an 8-bit register whose bit 6 is readable and writable while the other bits are read-only. RCSR has a GE bit and an RRDY bit; the GE bit controls the RNG operation and the RRDY bit indicates whether a random number has been written to RNRR.

  • Page 58: Rng Result Register (Rnrr)

    Bit 6: GE Description Stops the RNG operation (Initial value) Starts the RNG operation Bits 5 to 0—Reserved: Always read as 1 and cannot be written to. Although not used at present, the reserved bits may be used in the future. When writing to RCSR, write 0 to these bits.

  • Page 59: Operation

    Operation A 16-bit uniform random number can be generated by the following steps: • Write 1 to the GE bit. • Read RNRR while the GE bit is 1. Figure 4.1 shows the procedure for writing the required length of a random number to the RAM. Start Write 1 to GE RRDY = 1 ?

  • Page 60: Notes On Usage

    The following shows a coding example of 80-bit random-number generation. --- Coding example of random-number generation (80-bit random number) --- RNGstart: MOV.W #RNSA,R0 ;Random number store address (bottom) MOV.B #5,R1L ;R1L = 80 (bit length) / 16 MOV.B #H'40,R2L MOV.B R2L,@RCSR ;GE <- 1 RRDYwait: BTST...

  • Page 61: Watchdog Timer (Wdt)

    Section 5 Watchdog Timer (WDT) Overview Specify whether to operate or stop the WDT for each ROM code. When stopped, the WDT does not issue interrupts. The H8/3150 series has a single-channel watchdog timer (WDT) for monitoring system operations; that is, monitoring whether the application program is properly executed and whether the EEPROM is correctly written to.

  • Page 62: Block Diagram

    5.1.2 Block Diagram Figure 5.1 shows a block diagram of the WDT. Interrupt UDF interrupt control EWE interrupt CLK/32 CLK/64 CLK/128 Internal reset Reset control CLK/256 ECR controller TCSR TCNT TCWA Internal data bus (upper eight bits) TCNT: Timer counter TCSR: Timer control/status register TCWA: Timer control write address Figure 5.1 WDT Block Diagram...
  • Page 63 5.1.4 Vector Configuration Figure 5.2 shows the memory map of the WDT vector area. Address H'000A/H'000B EWE interrupt vector UDF interrupt vector H'000C/H'000D Figure 5.2 WDT Vectors Register Descriptions 5.2.1 Timer Counter (TCNT) Bit: Initial value: Read/Write: TCNT is an 8-bit readable and writable down-counter. Before TCSR is written to after reset, TCNT decrements the value by counting internal clocks for the CPU regardless of the CS1 and CS0 bit settings in TCSR.

  • Page 64: Timer Control/Status Register (Tcsr)

    to TCNT in the 4-kbyte area defined by TCWA. Any value can be specified as an operand (write data) of the reloading instruction; the initially written data is always reloaded to TCNT. In sleep mode, or during EEPMOV instruction execution, TCNT suspends counting without being initialized.

  • Page 65: Timer Counter Write Address (Tcwa)

    Bit 5—Reserved: Always read as 1 and cannot be written to. Although not used at present, the reserved bit may be used in the future. When writing to TCSR, write 0 into bit 5. Bit 4—Halt Flag (HLT): Controls operation of all the on-chip functions. When the HLT bit is set to 1, all the on-chip functions stop.
  • Page 66 Bits 7 to 4—Instruction Address (IA15 to IA12): These bits specify the high-order four bits (bits 15 to 12) of the address pointing to the area storing the write instruction for reloading the TCNT value. When specifying the IA15 to IA12 bits, set the WAD bit to 0 at the same time. For example, when H'X is specified in the IA15 to IA12 bits, the write instruction for reloading TCNT must be placed in the 4-kbyte area ranging from address H'X000 to address H'XFF7 in the ROM area;...

  • Page 67: Operation

    Operation 5.3.1 Checking Application Program Execution Area As shown in figure 5.3, when the counter underflows, the WDT sets the UDF bit to 1 and issues a UDF interrupt. Since the TCNT initial value cannot be changed, a UDF interrupt is issued at regular intervals until reset.
  • Page 68 In this case, system operation can be stopped by writing 1 to the HLT flag, or the external systems can be notified of the abnormal execution by outputting a signal to an I/O pin. --- Example of program in UDF interrupt routine --- UDFentry: BTST #7,@TCSR...

  • Page 69: Checking The Procedure For Writing To Eeprom

    5.3.2 Checking the Procedure for Writing to EEPROM The WDT issues an EWE interrupt when 1 is written to the EWE bit. The EWE interrupt is accepted at the end of the instruction following the instruction in which 1 is written to the EWE bit.
  • Page 70 instruction are correct. If they are not correct, EEPROM will be incorrectly written to due to invalid register settings. In this case, system operation can be stopped by writing 1 to the HLT flag, or the external systems can be notified of the abnormal operation by outputting a signal to an I/O pin. --- Example of program in EWE interrupt routine --- EWEentry: BTST...

  • Page 71: Reloading Tcnt By Tcwa Function

    Opcode Mnemonic FC20 MOV.B #H'20, R4L 7905FF00 MOV.W #H'FF00, R5 79066010 MOV.W #H'6010, R6 SP+1 (CCR) 790040FC MOV.W #H'40FC, R0 SP+2 interrupt 6A88FFFC MOV.B R0H, @TCSR SP+3 6A80FFF8 MOV.B R0L, @ECR Stack area 7B5C598F EEPMOV Application program area PC marked with *1 points to address marked with *2 Figure 5.6 Memory Contents for Checking EEPROM Writing Procedure 5.3.3 Reloading TCNT by TCWA Function...
  • Page 72 To reload the initial value to TCNT using the TCWA function, an instruction that writes to TCNT is used. Specify, in TCWA, the address where the instruction that writes to TCNT is stored, before initializing TCSR and TCNT in the WDT initializing routine. At the same time, set the WAD bit in TCWA to 0.

  • Page 73: Initializing Wdt

    5.3.4 Initializing WDT The WDT initialization procedure is described below. Figure 5.9 shows the initialization flow. (1) Set CPUCS0 bit of SYSCR to select the CPU operating clock. (2) Set TCWA to specify the allocation address of the reloading instruction. (3) Set CS1 and CS0 to select the clock to be input to TCNT.

  • Page 74: Notes On Usage

    Notes on Usage 1. When a SLEEP instruction is executed in the UDF interrupt routine, the sleep mode cannot be canceled. Also when a SLEEP instruction is executed between an EWE interrupt acceptance and an EEPMOV instruction execution, the sleep mode cannot be canceled. In sleep mode, the WDT suspends operation.

  • Page 75: Section 6 Ram

    Section 6 RAM Overview The H8/3150 series has an on-chip static RAM (H8/3152, H8/3155, and H8/3156: 512 bytes; H8/3153 and H8/3158: 1024 bytes). The RAM is connected to the CPU by a 16-bit data bus. Both byte data and word data are accessed in two states, enabling rapid data transfer.
  • Page 76 Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FBC0 H'FBC1 H'FBC2 H'FBC3 On-chip RAM (1024 bytes) H'FFBE H'FFBF Even addresses Odd addresses Figure 6.2 RAM Block Diagram (H8/3153 and H8/3158)

  • Page 77: Section 7 Rom

    Section 7 ROM Overview The H8/3150 series has an on-chip ROM (H8/3152: 24 kbytes; H8/3153: 32 kbytes; H8/3155 and H8/3156: 16 kbytes; H8/3158: 46 kbytes). The ROM is connected to the CPU by a 16-bit data bus. Both byte data and word data are accessed in two states, enabling rapid data transfer.
  • Page 78 Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0001 H'0002 H'0003 On-chip ROM (32 kbytes) H'7FFE H'7FFF Even addresses Odd addresses Figure 7.2 ROM Block Diagram (H8/3153) Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0001...
  • Page 79 Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0001 H'0002 H'0003 On-chip ROM (46 kbytes) H'B7FE H'B7FF Even addresses Odd addresses Figure 7.4 ROM Block Diagram (H8/3158)

  • Page 80: Section 8 Eeprom

    The features of the EEPROM are listed below. • Configuration: Allocated on the CPU address space Product EEPROM Capacity Page Size Number of Pages H8/3152 8 kbytes + 256 bytes 32 bytes 256 + 8 pages H8/3153 16 kbytes + 512 bytes...

  • Page 81: Block Diagram

    8.1.2 Block Diagram Figure 8.1 shows a block diagram of the EEPROM. The built-in timer generates the write/erase sequence. The clock pulses for this timer are obtained from an on-chip oscillator and are independent of the CPU clock. Changing the CPU clock rate (external clock) does not affect the EEPROM write/erase timing.

  • Page 82: Memory Organization

    H'601E H'601F Page 1 H'6020 H'6021 H'603E H'603F Page 263 H'80E0 H'80E1 H'80FE H'80FF Selector Data Figure 8.2 EEPROM Memory Organization (H8/3152) 64 bytes Page 0 H'8000 H'8001 H'803E H'803F Page 1 H'8040 H'8041 H'807E H'807F Page 263 H'C1C0 H'C1C1...
  • Page 83 16 bytes Page 0 H'6000 H'6001 H'600E H'600F Page 1 H'6010 H'6011 H'601E H'601F Page 71 H'6470 H'6471 H'647E H'647F Selector Data Figure 8.4 EEPROM Memory Organization (H8/3155) 16 bytes Page 0 H'6000 H'6001 H'600E H'600F Page 1 H'6010 H'6011 H'601E H'601F Page 135 H'6870...

  • Page 84: Register Configuration

    64 bytes Page 0 H'B800 H'B801 H'B83E H'B83F Page 1 H'B840 H'B841 H'B87E H'B87F Page 263 H'F9C0 H'F9C1 H'F9FE H'F9FF Selector Data Figure 8.6 EEPROM Memory Organization (H8/3158) 8.1.4 Register Configuration Writing and erasing of the EEPROM are controlled by the registers listed in table 8.1. Table 8.1 EEPROM Registers Register...
  • Page 85 Register Descriptions 8.2.1 EEPROM Control Register (ECR) ECR is an 8-bit register that controls the type of write or erase operation performed on the EEPROM. Bit: — — — — — — Initial value: Read/Write: Bits 7 to 2—Reserved: Always read as 1 and cannot be written to. Although not used at present, reserved bits may be used in the future.

  • Page 86: Eeprom Read Operation

    8.2.2 EEPROM Protection Register (EPR) Bit: — — — — — — — Initial value: Read/Write: EPR is an 8-bit register that enables the writing of EEPROM write/erase protect bits. Bit 7—Protect Bit Mode (PBM): This bit selects the EEPROM data area or protection area. The protection area is selected when the PBM bit is cleared to 0.

  • Page 87: Eeprom Write And Erase Operations

    EEPROM Write and Erase Operations 8.4.1 Write/Erase Sequence The EEPROM is written or erased using the EEPMOV block data transfer instruction. The EEPMOV instruction transfers a block of data stored in RAM to a single page in EEPROM. The data transfer from RAM to EEPROM is controlled by parameters set in CPU registers R4L, R5, and R6 as shown in figure 8.7.
  • Page 88 Table 8.2 EEPMOV Instruction Parameters and Their Valid Ranges Register Name Description Valid Range* Final Value Byte counter Byte length of block to be 1 to 64 H'00 written in EEPROM (H'01 to H'40) RAM address Starting address of source H'FBC0 to H'FFBF R5 + R4L register...

  • Page 89: Rewrite

    A single rewrite operation can modify contiguous bytes located in the same EEPROM page; 1 to 32 contiguous bytes in the H8/3152, 1 to 64 contiguous bytes in the H8/3153 and H8/3158, and 1 to 16 contiguous bytes in the H8/3155 and H8/3156 can be modified.

  • Page 90: Erase

    8.4.3 Erase When the EEPMOV instruction is executed with OC1 = 1 and OC0 = 0, the relevant EEPROM page is erased. The entire page containing the byte addressed by the EEPROM address register (R6) is erased. All data in the page is changed to 1 when erased. The byte counter (R4L) and RAM address register (R5) can be set to any valid values.

  • Page 91: Write/Erase Protection

    Write/Erase Protection 8.5.1 Protect Bits EEPROM data can be protected from accidental writing and erasing. Each page can be protected individually. Each page has its own protect bits. Write/erase protection is conferred by writing a protection code (H'78) to the protect bits. Once a page is protected, the protection cannot be canceled.

  • Page 92: Protection Procedure

    Data area Protection area Page 0 H'FF Page 1 H'FC Page 2 H'FF Can be written only once Page 263 H'FC : Write/erase-protected pages Figure 8.13 Example of Write/Erase Protection (H8/3153) 8.5.2 Protection Procedure To protect a page, software must set the EPR and ECR registers, then write the protection code (H'78) to the protect bits.
  • Page 93 START EWE ← 1* PBM ← 0 OC1 ← 0 Protect bits ← H'78 Note: EWE does not need to be set when the WDT is disabled. Figure 8.14 Protection Flowchart Note that the EWE bit in TCSR must be set to 1 before the PBM bit in EPR is cleared to 0. However, when the WDT is disabled, the EWE does not need to be set.

  • Page 94: Reading The Protect Bits

    8.5.3 Reading the Protect Bits After the EWE bit in TCSR is set to 1 and the PBM bit in EPR is cleared to 0, the protect bits can be read. The EWE bit continues holding 1 until the EEPMOV instruction is completed. To clear the EWE bit, execute the EEPMOV instruction at OC1 = OC0 = 1.

  • Page 95: Notes On Usage

    Notes on Usage When using the EEPROM, note the following points. (1) Write/Erase Abort: If an external reset is input during write or erase operation, the write or erase operation in progress is aborted and the control registers are initialized. In this case, data written to the EEPROM is not guaranteed.
  • Page 96 Case 1 Page N Case 2 Page N : Rewrite/overwrite execution area : Rewrite/overwrite operations are not executed in this area Figure 8.16 Rewrite/Overwrite Operations (for H8/3153) (4) Use the EEPMOV Instruction: When writing to the EEPROM, use the EEPMOV instruction. Do not use the MOV instruction for writing.

  • Page 97: Notes On Usage Of H8/3153

    Notes on Usage of H8/3153 The H8/3153 has several usage restrictions. Note that when developing software, a violation of these restrictions cannot be detected by the emulator. (1) Target Users: users that specify the ROM code to operate the WDT for the H8/3153. (2) Usage Restrictions: 1.

  • Page 98: Section 9 I/O Ports

    Section 9 I/O Ports Overview The H8/3150 series has two I/O ports. Software can select whether to use each I/O bit for data input or output. The I/O ports have a data register (DR) for latching output data, and a data direction register (DDR) for specifying input or output.
  • Page 99 Internal data bus Sleep mode DDR7 Input pull-up MOS (always switched-on) DDR write I/O-1/ Output buffer DR write DR read Input buffer Sleep mode External interrupt Falling edge request (to CPU) detector Sleep mode DDR6 Input pull-up MOS (always switched-on) DDR write I/O-2/ Output buffer...

  • Page 100: Register Configuration

    9.1.2 Register Configuration Table 9.1 lists the I/O port registers. Table 9.1 I/O Port Registers Name Abbr. Address Data register H'FFFE Data direction register H'FFFF Register Descriptions 9.2.1 Data Register (DR) Bit: — — — — — — Initial value: —...

  • Page 101: Data Direction Register (Ddr)

    9.2.2 Data Direction Register (DDR) Bit: DDR7 DDR6 — — — — — — Initial value: — — — — — — Read/Write: — — — — — — The data direction register specifies the direction (input or output) of the I/O ports. Bit 7—Data Direction Register Bit 7 (DDR7): Specifies the direction of the I/O-1 signal: 1 selects output;...
  • Page 102 Table 9.2 I/O-1/IRQ and I/O-2/IRQ Pin States DDR Value Operating Mode 0 (Initial Value) Normal operation Input port Output port IRQ input pin Sleep mode Must not be set* Note: When sleep mode is entered or canceled, the output from the I/O ports will collide with the IRQ input.

  • Page 103: Section 10 Clock Pulse Generator

    Section 10 Clock Pulse Generator 10.1 Overview The H8/3150 series includes an on-chip clock divider that generates the system clock for CPU (ø) from an external clock input. The external clock is input to the CLK pin. The CPU system clock frequency is one-half the external clock frequency when supplied through the divider, or it is the same frequency as the external clock frequency when directly supplied.

  • Page 104: System Control Register

    10.2 System Control Register The system control register (SYSCR) selects the clock for the CPU. Table 10.1 System Control Register Register Abbr. Initial Value Address System control register SYSCR H'00 H'FFF4 Bit: — — — — — — — CPUCS0 Initial value: Read/Write: SYSCR is initialized to H'00 at reset, but not reset in sleep mode.

  • Page 105: Section 11 Security

    Section 11 Security 11.1 Overview The H8/3150 series has the following security functions. The high-frequency, high-voltage, low- frequency, and low-voltage errors are detected outside the range of the operating frequency and power voltage. When an error is detected, all the internal functions are reset. To recover from the error detection state, enter the reset state by inputting a low level to the RES pin.

  • Page 106: Section 12 Electrical Characteristics

    Section 12 Electrical Characteristics 12.1 Absolute Maximum Ratings Item Symbol Rating Unit Power supply voltage –0.3 to +7.0 Input voltage –0.3 to V + 0.3 °C Operating temperature –25 to +85 °C Storage temperature –25 to +85 Note: Permanent damage may occur to the chip if maximum ratings are exceeded. Normal operation should be under the recommended operating conditions.

  • Page 107: Electrical Characteristics

    12.2 Electrical Characteristics The electrical characteristics are shown in sections 12.2.1, 12.2.2, 12.2.5, and 12.2.6 when the CPU operates at half of the external clock frequency. The electrical characteristics are shown in sections 12.2.3, 12.2.4, 12.2.7, and 12.2.8 when the CPU operates at the external clock frequency. See section 10, Clock Pulse Generator, for setting the CPU operating frequency.

  • Page 108: Dc Characteristics (5 V, Cpu Operates At Half Of The External Clock Frequency)

    12.2.1 DC Characteristics (5 V, CPU operates at half of the external clock frequency) Conditions: V = 4.5 to 5.5 V, V = 0 V, T = –25 to +85°C, unless otherwise specified. Item Symbol Min Unit Test Conditions × 0.8 — Input high + 0.3 V voltage...

  • Page 109: Ac Characteristics (5 V, Cpu Operates At Half Of The External Clock Frequency)

    12.2.2 AC Characteristics (5 V, CPU operates at half of the external clock frequency) Conditions: V = 4.5 to 5.5 V, V = 0 V, T = –25 to +85°C, unless otherwise specified. Item Symbol Unit Test Conditions µs Clock cycle time H8/3153 —...

  • Page 110: Dc Characteristics (5 V, Cpu Operates At The External Clock Frequency)

    12.2.3 DC Characteristics (5 V, CPU operates at the external clock frequency) Conditions: V = 4.5 to 5.5 V, V = 0 V, T = –25 to +85°C, unless otherwise specified. Item Symbol Min Unit Test Conditions × 0.8 — Input high + 0.3 V voltage...

  • Page 111: Ac Characteristics (5 V, Cpu Operates At The External Clock Frequency)

    12.2.4 AC Characteristics (5 V, CPU operates at the external clock frequency) Conditions: V = 4.5 to 5.5 V, V = 0 V, T = –25 to +85°C, unless otherwise specified. Item Symbol Unit Test Conditions µs Clock cycle time —...
  • Page 112 × 0.7 × 0.7 I/O port (input) 0.825 V 0.825 V Figure 12.2 I/O Port Input Waveform (V = 4.5 V to 5.5 V) 4.5 V 0.8 V × 0.7 0.5 V 0.66 V 0.66 V 0.66 V 0.66 V , CLK, and RES should be low (GND level) at power-on and after power-off.

  • Page 113: Dc Characteristics (3 V, Cpu Operates At Half Of The External Clock Frequency)

    12.2.5 DC Characteristics (3 V, CPU operates at half of the external clock frequency) Conditions: V = 2.7 to 3.3 V, V = 0 V, T = –25 to +85°C, unless otherwise specified. Item Symbol Unit Test Conditions × 0.8 — Input high + 0.3 voltage...

  • Page 114: Ac Characteristics (3 V, Cpu Operates At Half Of The External Clock Frequency)

    12.2.6 AC Characteristics (3 V, CPU operates at half of the external clock frequency) Conditions: V = 2.7 to 3.3 V, V = 0 V, T = –25 to +85°C, unless otherwise specified. Item Symbol Unit Test Conditions µs Clock cycle time H8/3153 0.25 —...

  • Page 115: Dc Characteristics (3 V, Cpu Operates At The External Clock Frequency)

    12.2.7 DC Characteristics (3 V, CPU operates at the external clock frequency) Conditions: V = 2.7 to 3.3 V, V = 0 V, T = –25 to +85°C, unless otherwise specified. Item Symbol Unit Test Conditions × 0.8 — Input high + 0.3 voltage ×...

  • Page 116: Ac Characteristics (3 V, Cpu Operates At The External Clock Frequency)

    12.2.8 AC Characteristics (3 V, CPU operates at the external clock frequency) Conditions: V = 2.7 to 3.3 V, V = 0 V, T = –25 to +85°C, unless otherwise specified. Item Symbol Unit Test Conditions µs Clock cycle time 0.25 —...
  • Page 117 × 0.7 × 0.7 I/O port (input) × 0.2 × 0.2 Figure 12.6 I/O Port Input Waveform (V = 2.7 V to 3.3 V) 2.7 V 0.8 V × 0.7 × 0.2 × 0.2 × 0.2 × 0.2 × 0.2 , CLK, and RES should be low (GND level) at power-on and after power-off.

  • Page 118: Appendix A Instruction Set

    Appendix A Instruction Set Operation Notation Rd8/16 8- or 16-bit general register (destination) Rs8/16 8- or 16-bit general register (source) Rn8/16 8- or 16-bit general register Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Program counter Stack pointer...
  • Page 119 Table A.1 Instruction Set Addressing Mode/ Instruction Length Mnemonic Operation Condition Code I H N Z V C #xx:8 → Rd8 MOV.B #xx:8, Rd — — — Rs8 → Rd8 MOV.B Rs, Rd — — — @Rs16 → Rd8 MOV.B @Rs, Rd —...
  • Page 120 Table A.1 Instruction Set (cont) Addressing Mode/ Instruction Length Mnemonic Operation Condition Code I H N Z V C Rd8+#xx:8 → Rd8 ADD.B #xx:8, Rd — Rd8+Rs8 → Rd8 ADD.B Rs, Rd — Rd16+Rs16 → Rd16 ADD.W Rs, Rd — Rd8+#xx:8+C →...
  • Page 121 Table A.1 Instruction Set (cont) Addressing Mode/ Instruction Length Mnemonic Operation Condition Code I H N Z V C SHAL SHAL.B Rd — — SHAR SHAR.B Rd — — SHLL SHLL.B Rd — — SHLR SHLR.B Rd — — ROTXL ROTXL.B Rd —...
  • Page 122 Table A.1 Instruction Set (cont) Addressing Mode/ Instruction Length Mnemonic Operation Condition Code I H N Z V C (#xx:3 of @Rd16) ← 0 BCLR BCLR #xx:3, @Rd — — — — — — (#xx:3 of @aa:8) ← 0 (cont) BCLR #xx:3, @aa:8 —...
  • Page 123 Table A.1 Instruction Set (cont) Addressing Mode/ Instruction Length Mnemonic Operation Condition Code Branch I H N Z V C Condition C → (#xx:3 of @Rd16) BIST BIST #xx:3, @Rd — — — — — — C → (#xx:3 of @aa:8) (cont) BIST #xx:3, @aa:8 —...
  • Page 124 Table A.1 Instruction Set (cont) Addressing Mode/ Instruction Length Mnemonic Operation Condition Code Branch I H N Z V C Condition BMI d:8 — — — — — — — if true then PC ← PC+d:8 N⊕V=0 (cont) BGE d:8 —...
  • Page 125 Table A.1 Instruction Set (cont) Addressing Mode/ Instruction Length Mnemonic Operation Condition Code I H N Z V C CCR∨#xx:8 → CCR ORC #xx:8, CCR CCR⊕#xx:8 → CCR XORC XORC #xx:8, CCR PC ← PC+2 — — — — — —...

  • Page 126: Appendix B Operation Code Map

    Appendix B Operation Code Map Table B.1 is a map of the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Some pairs of instructions have identical first bytes. These instructions are differentiated by the most significant bit (MSB) of the second byte (bit 7 of the first instruction word).
  • Page 127 Table B.1 Operation Code Map NOP SLEEP STC ORC XORC ANDC LDC ADDS ADDX DAA SHLL SHLR ROTXL ROTXR DEC SUBS SUBX DAS SHAL ROTL ROTR SHAR BRA * BRN * BCC * BCS * MULXU DIVXU MOV * BIST BSET BNOT BCLR BTST BXOR BAND...

  • Page 128: Appendix C Register Field

    Appendix C Register Field Register Field (1) Bit Names Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFF0 RCSR RRDY GE — — — — — — H'FFF1 —...

  • Page 129: Register Field (2)

    Register Field (2) RCSR RNG Control Status Register RRDY — — — — — — Initial value Read/Write Generation Enabled Stops RNG operation Starts RNG operation Random Number Ready [Clearing condition] • When 0 is written to the GE bit •...
  • Page 130 SYSCR System Control Register Clock Pulse Generator — — — — — — — CPUCS0 Initial value Read/Write CPU Clock Select 0 One-half frequecny of the external clock External clock frequency TCWA Timer Counter Write Address IA15 IA14 IA13 IA12 —...
  • Page 131 TCSR Timer Control/Status Register — — — Initial value R/(W)* Read/Write Clock Select 1 and 0 CLK/32 CLK/64 CLK/128 CLK/256 Halt Flag Normal operation On-chip functions stop ECR Write Enable [Clearing condition] When EEPMOV instruction execution ends [Setting conditon] When 1 is written to this bit while it is 0 Underflow Flag [Clearing condition] When RTE instruction is executed while UDF = 1...
  • Page 132 EEPROM Control Register EEPROM — — — — — — Initial value Read/Write Operation Control 1 and 0 Rewrite Overwrite Page erase Write/erase disabled EEPROM Protection Register EEPROM — — — — — — — Initial value Read/Write Protect Bit Mode Protection area Data area...
  • Page 133 Data Register — — — — — — Initial value — — Read/Write Data Register Bit 6 Output data latch of I/O-2 Data Register Bit 7 Output data latch of I/O-1 Data Direction Register DDR7 DDR6 — — — — —...

  • Page 134: Appendix D Comparison With H8/3102, H8/3103

    H8/3155: 16 kbytes H8/3156: 16 kbytes H8/3158: 46 kbytes EEPROM 8 kbytes 16 kbytes H8/3152: 8 kbytes + 256 bytes (addresses: H8/3153: 16 kbytes + 512 bytes H'6000 to H'9FFF) H8/3155: 1 kbytes + 128 bytes H8/3156: 2 kbyte + 128 bytes...
  • Page 135 H8/3103 H8/3150 Series EEPROM Organization 32 bytes 64 bytes H8/3152: 32 bytes x 264 pages × 256 pages x 256 pages H8/3153: 64 bytes x 264 pages H8/3155: 16 bytes x 72 pages H8/3156: 16 bytes x 136 pages H8/3158: 64 bytes x 264 pages...
  • Page 136 Table D.1 Comparison between H8/3102, H8/3103, and H8/3150 Series (cont) Item H8/3102 H8/3103 H8/3150 Series If writing to ROM is attempted, Notes on memory Writing to ROM is Writing to ROM is accesses ignored. ignored. the LSI is reset. Word accesses to Word accesses to Word accesses to addresses addresses H'FFF8...

  • Page 137: Appendix E H8/3150 Series Dp-64S Pin Arrangement

    Appendix E H8/3150 Series DP-64S Pin Arrangement A working sample is available in 64-pin plastic shrink DIP (DP-64S) form. I/O-1/IRQ 64-pin plastic shrink DIP I/O-2/IRQ Top View Note: Pins without names in this figure must be left open. Figure E.1 H8/3150 Series DP-64S Pin Arrangement...
  • Page 138 Publication Date: 1st Edition, March 1999 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Group Hitachi, Ltd. Edited by: Technical Documentation Group UL Media Co., Ltd. Copyright © Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.

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