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Note: The RES, I/O-1/IRQ, and I/O-2/IRQ signals must be held high during sleep mode.
CLK
CCR I bit
I/O-1/IRQ or
I/O-2/IRQ
State
Operating state
CCR I bit cleared to 0
44
Sleep mode
I/O-1/IRQ = low
I/O-2/IRQ = low
Execution of interrupt-
handling routine
RTE instruction
Figure 2.15 Recovery from Sleep Mode
CLK = 0 MHz to t
Power-down state
SLEEP instruction
Figure 2.16 Interrupt Timing in Sleep Mode
or
cyc
Sleep mode
IRQ
Operating state
Interrupt exception
handling
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