Page 1 Hitachi 16-Bit Single-Chip Microcomputer H8S/2646 Series H8S/2646 HD6432646 H8S/2645 HD6432645 H8S/2647 HD6432647 H8S/2648 HD6432648 H8S/2646R F-ZTAT™ HD64F2646R H8S/2648R F-ZTAT™ HD64F2648R Hardware Manual ADE-602-207C Rev. 4.0 9/20/02 Hitachi, Ltd.
Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 3 General Precautions on the Handling of Products 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 5 Note: * F-ZTAT™ is a trademark of Hitachi, Ltd. Target Users: This manual was written for users who will be using the H8S/2646 Series in the design of application systems. Members of this audience are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.
Page 6 H8S/2646 Series manuals: Manual Title ADE No. H8S/2646 Series Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083 Users manuals for development tools: Manual Title ADE No. C/C++ Complier, Assembler, Optimized Linkage Editor User's Manual ADE-702-247 Simulator Debugger (for Windows) Users Manual...
Page 7 List of Items Revised or Added for This Version Section Page Description 2.10.2 Caution to 76, 77 Newly added observe when using The BSET, BCLR, BNOT, BST and BIST instructions read data in a unit of byte, bit manipulation then, after bit manipulation, they write data in a unit of byte. Therefore, caution instructions must be exercised when executing any of these instructions for registers and ports that include write-only bits.
Page 8 Section Page Description 9.13.2 Register Part F Data Register (PFDR) Configuration — PF6DR PF5DR PF4DR PF3DR PF2DR — PF0DR Initial value : undefined — 2nd line changed as follows PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF6 to PF2, PF0).
Page 9 Section Page Description 15.3.2 Initialization 565 to Bit Rate and Bit Timing Settings: As bit rate settings, a baud rate setting and bit timing after Hardware setting must be made each time a CAN node begins communication. The baud rate and bit timing settings are made in the bit configuration register (BCR).
Page 10 Section Page Description 15.3.2 Initialization 565 to Example: With a 1 Mb/s baud rate and a 20 MHz input clock: after Hardware 20 MHz Reset 1 Mb/s = 2 × (0 + 1) × (3 + 4 + 3) Bit Rate and Bit Set Values Actual Values Timing Settings...
Page 11 Section Page Description Error warning interrupt (TEC ≥ 96) 15.3.7 Interrupt IRR3 Interface Error warning interrupt (REC ≥ 96) IRR4 Table 15-5 HCAN IRR7 Overload frame transmission interrupt Interrupt Sources 15.5 Usage Notes Newly added 9. HTxD pin output HTxD pin output in error passive state in error passive state If the HRxD pin becomes fixed at 1 during message transmission or 10.
Page 12 Section Page Description 23.1 Absolute Input voltage (OSC1, OSC2) –0.3 +3.5 Maximum Ratings lnput voltage (XTAL, EXTAL) –0.3 to A +0.3 Input voltage (ports 4 and 9) –0.3 to AV +0.3 Table 23-1 Input voltage (ports A, B, C, D, E, –0.3 to LPV +0.3 Absolute Maximum...
Page 13 Section Page Description B.2 Functions TXACK—Transmit Acknowledge Register H'F80A HCAN TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 — Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* — TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 Initial value R/(W)* R/(W)* R/(W)* R/(W)*...
Page 14 Section Page Description B.2 Functions RFPR—Remote Request Register H'F810 HCAN RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8 Initial value R/(W)* R/(W)* R/(W)* R/(W)*...
Page 15 Section Page Description B.2 Functions UMSR—Unread Message Status Register H'F81A HCAN UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 Initial value R/(W)* R/(W)* R/(W)*...
Page 17: Table Of Contents
Contents Section 1 Overview..................1 Overview..........................Internal Block Diagram...................... Pin Description........................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions in Each Operating Mode..............10 1.3.3 Pin Functions ......................20 Section 2 CPU....................27 Overview..........................27 2.1.1 Features ......................... 27 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU........28 2.1.3 Differences from H8/300 CPU ................
Page 18 Basic Timing........................71 2.9.1 Overview....................... 71 2.9.2 On-Chip Memory (ROM, RAM)................71 2.9.3 On-Chip Supporting Module Access Timing ............73 2.9.4 On-Chip HCAN Module Access Timing.............. 75 2.9.5 External Address Space Access Timing ............... 76 2.10 Usage Note ......................... 76 2.10.1 TAS Instruction ....................
Page 19 Section 5 Interrupt Controller ................101 Overview..........................101 5.1.1 Features ......................... 101 5.1.2 Block Diagram...................... 102 5.1.3 Pin Configuration....................103 5.1.4 Register Configuration..................103 Register Descriptions ......................104 5.2.1 System Control Register (SYSCR)............... 104 5.2.2 Interrupt Priority Registers A to H, J, K, M (IPRA to IPRH, IPRJ, IPRK, IPRM)..............
Page 20 6.2.3 Break Control Register A (BCRA) ............... 132 6.2.4 Break Control Register B (BCRB) ............... 134 6.2.5 Module Stop Control Register C (MSTPCRC) ............ 134 Operation..........................135 6.3.1 PC Break Interrupt Due to Instruction Fetch............135 6.3.2 PC Break Interrupt Due to Data Access ............... 135 6.3.3 Notes on PC Break Interrupt Handling..............
Page 21 Write Data Buffer Function ....................178 Bus Arbitration........................179 7.8.1 Overview ......................179 7.8.2 Operation ......................179 7.8.3 Bus Transfer Timing ..................... 179 Resets and the Bus Controller.................... 180 Section 8 Data Transfer Controller (DTC) ............181 Overview..........................181 8.1.1 Features ......................... 181 8.1.2 Block Diagram......................
Page 22 9.2.3 Pin Functions ......................224 Port 2..........................232 9.3.1 Overview....................... 232 9.3.2 Register Configuration..................232 9.3.3 Pin Functions ......................234 Port 3..........................242 9.4.1 Overview....................... 242 9.4.2 Register Configuration..................242 9.4.3 Pin Functions ......................245 Port 4..........................247 9.5.1 Overview....................... 247 9.5.2 Register Configuration..................
Page 23 9.12.2 Register Configuration..................277 9.12.3 Pin Functions ......................279 9.12.4 MOS Input Pull-Up Function................279 9.13 Port F..........................281 9.13.1 Overview....................... 281 9.13.2 Register Configuration..................282 9.13.3 Pin Functions ......................284 9.14 Port H ..........................287 9.14.1 Overview....................... 287 9.14.2 Register Configuration..................287 9.14.3 Pin Functions ......................
Page 24 10.4.3 Synchronous Operation ..................345 10.4.4 Buffer Operation ....................347 10.4.5 Cascaded Operation ....................351 10.4.6 PWM Modes ......................353 10.4.7 Phase Counting Mode ................... 358 10.5 Interrupts ..........................365 10.5.1 Interrupt Sources and Priorities ................365 10.5.2 DTC Activation ....................367 10.5.3 A/D Converter Activation..................
Page 25 12.1.4 Register Configuration..................416 12.2 Register Descriptions ......................417 12.2.1 Timer Counter (TCNT)..................417 12.2.2 Timer Control/Status Register (TCSR) ..............417 12.2.3 Reset Control/Status Register (RSTCSR) ............422 12.2.4 Notes on Register Access..................423 12.3 Operation..........................425 12.3.1 Watchdog Timer Operation .................. 425 12.3.2 Interval Timer Operation ..................
Page 26 14.3.6 Data Transfer Operations..................518 14.3.7 Operation in GSM Mode ..................525 14.3.8 Operation in Block Transfer Mode ............... 526 14.4 Usage Notes ........................527 Section 15 Hitachi Controller Area Network (HCAN) ........531 15.1 Overview..........................531 15.1.1 Features ......................... 531 15.1.2 Block Diagram...................... 532 15.1.3 Pin Configuration....................
Page 27 15.2.15 Transmit Error Counter (TEC)................554 15.2.16 Unread Message Status Register (UMSR)............555 15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH) ........... 556 15.2.18 Message Control (MC0 to MC15)................ 557 15.2.19 Message Data (MD0 to MD15) ................561 15.2.20 Module Stop Control Register C (MSTPCRC) ............ 561 15.3 Operation..........................
Page 28 17.1.4 Register Configuration..................615 17.2 Register Descriptions ......................616 17.2.1 PWM Control Registers 1 and 2 (PWCR1, PWCR2)........... 616 17.2.2 PWM Output Control Registers 1 and 2 (PWOCR1, PWOCR2)......617 17.2.3 PWM Polarity Registers 1 and 2 (PWPR1, PWPR2) ........... 618 17.2.4 PWM Counters 1 and 2 (PWCNT1, PWCNT2) ...........
Page 29 19.3 Operation..........................655 19.4 Usage Notes ........................655 Section 20 ROM....................657 20.1 Features ..........................657 20.2 Overview..........................658 20.2.1 Block Diagram...................... 658 20.2.2 Mode Transitions ....................659 20.2.3 On-Board Programming Modes................660 20.2.4 Flash Memory Emulation in RAM ............... 662 20.2.5 Differences between Boot Mode and User Program Mode........
Page 30 20.11.8 Programmer Mode Transition Time ..............707 20.11.9 Notes on Memory Programming ................708 20.12 Flash Memory and Power-Down States ................709 20.12.1 Notes on Power-Down States ................709 20.13 Flash Memory Programming and Erasing Precautions............710 Section 21 Clock Pulse Generator ..............715 21.1 Overview..........................
Page 31 22.6.5 Usage Notes ......................744 22.7 Hardware Standby Mode ....................745 22.7.1 Hardware Standby Mode ..................745 22.7.2 Hardware Standby Mode Timing................746 22.8 Watch Mode ........................746 22.8.1 Watch Mode......................746 22.8.2 Exiting Watch Mode ..................... 747 22.8.3 Notes ........................747 22.9 Sub-Sleep Mode .........................
Page 32 Appendix C I/O Port Block Diagrams............1075 Port 1 Block Diagrams ...................... 1075 Port 2 Block Diagrams ......................1081 Port 3 Block Diagrams ...................... 1083 Port 4 Block Diagram ....................... 1090 Port 5 Block Diagrams ...................... 1091 Port 9 Block Diagram ....................... 1095 Port A Block Diagram.......................
Page 33: Section 1 Overview
Section 1 Overview Overview The H8S/2646 Series is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2600 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space.
Page 34 Table 1-1 Overview Item Specification • General-register machine  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control  Maximum clock rate: 20 MHz  High-speed arithmetic operations 8/16/32-bit register-register add/subtract : 50 ns 16 ×...
Page 35 Segment output pins may be selected four at a time as ports • On-chip power supply division resistor Notes: *1 In the H8S/2646, H8S/2646R, and H8S/2645. *2 In the H8S/2648, H8S/2648R, and H8S/2647. • 92 I/O pins, 16 input-only pins...
Page 36 2 kbytes H8S/2647 • Seven external interrupt pins (NMI, IRQ0 to IRQ5) Interrupt controller • Internal interrupt sources  43 (H8S/2646, H8S/2646R, H8S/2645)  47 (H8S/2648, H8S/2648R, H8S/2647) • Eight priority levels settable Power-down states • Medium-speed mode • Sleep mode •...
Page 37 Item Specification Product lineup Model Name Mask ROM Version F-ZTAT Version ROM/RAM (Bytes) Packages HD6432646 HD64F2646R 128 k/4 k FP-144J HD6432645 — 64 k/2 k FP-144G HD6432648 HD64F2648R 128 k/4 k FP-144J HD6432647 — 64 k/2 k FP-144G The HD64F2646R and HD64F2648R use an FP-144J package.
Page 38: Internal Block Diagram
P93/AN11 P92/AN10 P91/AN9 Port 1 Port H Port J Port 4 P90/AN8 Notes: *1 Flash memory version only. *2 The FWE pin is for compatibility with the flash memory version. Figure 1-1 (1) H8S/2646, H8S/2646R, and H8S/2645 Internal Block Diagram...
Page 39 Port D Port E PA7/A23/SEG40 PA6/A22/SEG39 OSC2 PA5/A21/SEG38 OSC1 PA4/A20/SEG37 EXTAL PA3/A19/COM4 XTAL PA2/A18/COM3 PLLCAP PA1/A17/COM2 H8S/2600 CPU PLLVSS PA0/A16/COM1 STBY PB7/A15/SEG32 PB6/A14/SEG31 PB5/A13/SEG30 PB4/A12/SEG29 HTxD Interrupt controller PB3 / A11/SEG28 HRxD PB2/A10/SEG27 PB1/A9/SEG26 PC break controller PF7/ø PB0/A8/SEG25 PF6/AS/SEG36 PC7/A7/SEG24 PF5/RD/SEG35 PC6/A6/SEG23...
Page 40: Pin Description
Pin Description 1.3.1 Pin Arrangement Figure 1-2 (1) shows the pin arrangement of the H8S/2646, H8S/2646R, and H8S/2645, and figure 1-2 (2) shows that of the H8S/2648, H8S/2648R, and H8S/2647. HTxD PWMVSS HRxD PJ7/PWM2H PJ6/PWM2G PJ5/PWM2F PJ4/PWM2E P20/TIOCA3 PWMVCC P21/TIOCB3...
Page 41 HTxD PWMVSS HRxD PJ7/PWM2H P50/TxD2 PJ6/PWM2G P51/RxD2 PJ5/PWM2F P52/SCK2 PJ4/PWM2E P20/TIOCA3 PWMVCC P21/TIOCB3 PJ3/PWM2D P22/TIOCC3 PJ2/PWM2C P23/TIOCD3 PJ1/PWM2B P25/TIOCB4 PJ0/PWM2A PWMVSS P24/TIOCA4 PH7/PWM1H PH6/PWM1G P27/TIOCB5 PH5/PWM1F PH4/PWM1E P26/TIOCA5 PWMVCC PH3/PWM1D Top View AVCC PH2/PWM1C Vref (FP-144J, FP-144G) PH1/PWM1B P40/AN0 PH0/PWM1A P41/AN1 PWMVSS P42/AN2...
Page 42: Pin Functions In Each Operating Mode
1.3.2 Pin Functions in Each Operating Mode Tablse 1-2 (1) and 1-2 (2) show the pin functions in each of the operating modes. Table 1-2 (1) Pin Functions in Each Operating Mode (H8S/2646, H8S/2646R, H8S/2645) Pin Name Pin No. Mode 4...
Page 43 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 PC6/A6/SEG7 PC6/SEG7 PC7/A7/SEG8 PC7/SEG8 PB0/A8/SEG9 PB0/A8/SEG9 PB0/A8/SEG9 PB0/SEG9 PB1/A9/SEG10 PB1/A9/SEG10 PB1/A9/SEG10 PB1/SEG10 PB2/A10/SEG11 PB2/A10/SEG11 PB2/A10/SEG11 PB2/SEG11 PB3/A11/SEG12 PB3/A11/SEG12 PB3/A11/SEG12 PB3/SEG12 PB4/A12/SEG13 PB4/A12/SEG13 PB4/A12/SEG13 PB4/SEG13 PB5/A13/SEG14 PB5/A13/SEG14 PB5/A13/SEG14 PB5/SEG14 PB6/A14/SEG15 PB6/A14/SEG15 PB6/A14/SEG15...
Page 44 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 PWMVss PWMVss PWMVss PWMVss PJ0/PWM2A PJ0/PWM2A PJ0/PWM2A PJ0/PWM2A PJ1/PWM2B PJ1/PWM2B PJ1/PWM2B PJ1/PWM2B PJ2/PWM2C PJ2/PWM2C PJ2/PWM2C PJ2/PWM2C PJ3/PWM2D PJ3/PWM2D PJ3/PWM2D PJ3/PWM2D PWMVcc PWMVcc PWMVcc PWMVcc PJ4/PWM2E PJ4/PWM2E PJ4/PWM2E PJ4/PWM2E PJ5/PWM2F PJ5/PWM2F PJ5/PWM2F...
Page 45 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 XTAL XTAL XTAL XTAL EXTAL EXTAL EXTAL EXTAL PF0/IRQ2 PF0/IRQ2 PF0/IRQ2 PF0/IRQ2 PF3/LWR/ADTRG/IRQ3 PF3/LWR/ADTRG/IRQ3 PF3/LWR/ADTRG/IRQ3 PF3/ADTRG/IRQ3 PF7/φ PF7/φ PF7/φ PF7/φ P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/...
Page 46 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 P27/TIOCB5 P27/TIOCB5 P27/TIOCB5 P27/TIOCB5 P26/TIOCA5 P26/TIOCA5 P26/TIOCA5 P26/TIOCA5 AVcc AVcc AVcc AVcc Vref Vref Vref Vref P40/AN0 P40/AN0 P40/AN0 P40/AN0 P41/AN1 P41/AN1 P41/AN1 P41/AN1 P42/AN2 P42/AN2 P42/AN2 P42/AN2 P43/AN3 P43/AN3 P43/AN3...
Page 47 Table 1-2 (2) Pin Functions in Each Operating Mode (H8S/2648, H8S/2648R, H8S/2647) Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 PE0/D0/SEG1 PE0/D0/SEG1 PE0/D0/SEG1 PE0/SEG1 PE1/D1/SEG2 PE1/D1/SEG2 PE1/D1/SEG2 PE1/SEG2 PE2/D2/SEG3 PE2/D2/SEG3 PE2/D2/SEG3 PE2/SEG3 PE3/D3/SEG4 PE3/D3/SEG4 PE3/D3/SEG4 PE3/SEG4 PE4/D4/SEG5 PE4/D4/SEG5 PE4/D4/SEG5...
Page 48 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 PC6/A6/SEG23 PC6/SEG23 PC7/A7/SEG24 PC7/SEG24 PB0/A8/SEG25 PB0/A8/SEG25 PB0/A8/SEG25 PB0/SEG25 PB1/A9/SEG26 PB1/A9/SEG26 PB1/A9/SEG26 PB1/SEG26 PB2/A10/SEG27 PB2/A10/SEG27 PB2/A10/SEG27 PB2/SEG27 PB3/A11/SEG28 PB3/A11/SEG28 PB3/A11/SEG28 PB3/SEG28 PB4/A12/SEG29 PB4/A12/SEG29 PB4/A12/SEG29 PB4/SEG29 PB5/A13/SEG30 PB5/A13/SEG30 PB5/A13/SEG30 PB5/SEG30 PB6/A14/SEG31 PB6/A14/SEG31 PB6/A14/SEG31...
Page 49 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 PWMVss PWMVss PWMVss PWMVss PJ0/PWM2A PJ0/PWM2A PJ0/PWM2A PJ0/PWM2A PJ1/PWM2B PJ1/PWM2B PJ1/PWM2B PJ1/PWM2B PJ2/PWM2C PJ2/PWM2C PJ2/PWM2C PJ2/PWM2C PJ3/PWM2D PJ3/PWM2D PJ3/PWM2D PJ3/PWM2D PWMVcc PWMVcc PWMVcc PWMVcc PJ4/PWM2E PJ4/PWM2E PJ4/PWM2E PJ4/PWM2E PJ5/PWM2F PJ5/PWM2F PJ5/PWM2F...
Page 50 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 XTAL XTAL XTAL XTAL EXTAL EXTAL EXTAL EXTAL PF0/IRQ2 PF0/IRQ2 PF0/IRQ2 PF0/IRQ2 PF3/LWR/ADTRG/IRQ3 PF3/LWR/ADTRG/IRQ3 PF3/LWR/ADTRG/IRQ3 PF3/ADTRG/IRQ3 PF7/φ PF7/φ PF7/φ PF7/φ P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/...
Page 51 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 P27/TIOCB5 P27/TIOCB5 P27/TIOCB5 P27/TIOCB5 P26/TIOCA5 P26/TIOCA5 P26/TIOCA5 P26/TIOCA5 AVcc AVcc AVcc AVcc Vref Vref Vref Vref P40/AN0 P40/AN0 P40/AN0 P40/AN0 P41/AN1 P41/AN1 P41/AN1 P41/AN1 P42/AN2 P42/AN2 P42/AN2 P42/AN2 P43/AN3 P43/AN3 P43/AN3...
Page 52: Pin Functions
1.3.3 Pin Functions Table 1-3 outlines the pin functions of the H8S/2646. Table 1-3 Pin Functions Type Symbol Name and Function Power Input Power supply: For connection to the power supply. All Vcc pins should be connected to the system power supply.
Page 53 Mode pins: These pins set the operating mode. control The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2646 Series is operating. Operating Mode —...
Page 54 Type Symbol Name and Function Bus control Output High write: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. Output Low write: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled.
Page 55 Transmit data: Data output pins. communication interface (SCI)/ Smart Card RxD1, RxD0 Input Receive data: Data input pins. interface H8S/2646, SCK1, SCK0 I/O Serial clock: Clock I/O pins. H8S/2646R, The SCK0 output type is NMOS push-pull. H8S/2645 Serial TxD2 to Output Transmit data: Data output pins.
Page 56 Type Symbol Name and Function SEG24 to Output LCD segment output: LCD segment output pins controller/driver SEG1 (H8S/2646, H8S/2646R, H8S/2645) SEG40 to SEG1 (H8S/2648, H8S/2648R, H8S/2647) COM4 to Output LCD common output: LCD common output pins COM1 I/O ports P17 to P10 Port 1: 8-bit I/O pins.
Page 57 Type Symbol Name and Function I/O ports PF7 to PF2, Port F: 7-bit I/O pins. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). PH7 to PH0 Port H: 8-bit I/O pins. Input or output can be designated for each bit by means of the port H data direction register (PHDDR).
Page 59: Section 2 Cpu
Section 2 CPU Overview The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control.
Page 60: Differences Between H8S/2600 Cpu And H8S/2000 Cpu
 32 ÷ 16-bit register-register divide : 1000 ns • Two CPU operating modes  Normal mode*  Advanced mode Note: * Not available in the H8S/2646 Series. • Power-down state  Transition to power-down state by SLEEP instruction  CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
Page 61: Differences From H8/300 Cpu
 Normal mode* supports the same 64-kbyte address space as the H8/300 CPU.  Advanced mode supports a maximum 16-Mbyte address space. Note: * Not available in the H8S/2646 Series. • Enhanced addressing  The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.
Page 62: Cpu Operating Modes
Note: * Not available in the H8S/2646 Series. Figure 2-1 CPU Operating Modes (1) Normal Mode (Not Available in the H8S/2646 Series) The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed.
Page 63 Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 2-2).
Page 64 Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-3. When EXR is invalid, it is not pushed onto the stack.
Page 65 Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-4). For details of the exception vector table, see section 4, Exception Handling.
Page 66 Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-5. When EXR is invalid, it is not pushed onto the stack.
Page 67: Address Space
(architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used by the H8S/2646 Series H'FFFFFFFF (a) Normal Mode* (b) Advanced Mode Note: * Not available in the H8S/2646 Series. Figure 2-6 Memory Map...
Page 68: Register Configuration
Interrupt mask bits Overflow flag CCR: Condition-code register Carry flag Interrupt mask bit MAC: Multiply-accumulate register User bit or interrupt mask bit* Note: * Cannot be used as an interrupt mask bit in the H8S/2646 Series. Figure 2-7 CPU Registers...
Page 69: General Registers
2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Page 70: Control Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-9 shows the stack. Free area SP (ER7) Stack area Figure 2-9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),...
Page 71 Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
Page 72: Initial Register Values
Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, Instruction List. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
Page 73: Data Formats
Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 74 Data Type Register Number Data Format Word data Word data Longword data Legend ERn: General register ER General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2-10 General Register Data Formats (cont)
Page 75: Memory Data Formats
2.5.2 Memory Data Formats Figure 2-11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
Page 76: Instruction Set
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. *2 Bcc is the general name for conditional branch instructions. *3 Not available in the H8S/2646 Series. *4 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Page 77: Instructions And Addressing Modes
2.6.2 Instructions and Addressing Modes Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2-2 Combinations of Instructions and Addressing Modes...
Page 79: Table Of Instructions Classified By Function
2.6.3 Table of Instructions Classified by Function Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) (EAd) Destination operand (EAs)
Page 80 Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE Cannot be used in the H8S/2646 Series. MOVTPE Cannot be used in the H8S/2646 Series. @SP+ → Rn Pops a register from the stack.
Page 81 Type Instruction Size Function Rd ± Rs → Rd, Rd ± #IMM → Rd Arithmetic B/W/L operations Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register.
Page 82 Type Instruction Size Function Rd ÷ Rs → Rd Arithmetic DIVXS operations Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16- bit remainder.
Page 83 Type Instruction Size Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Logic B/W/L operations Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 84 Type Instruction Size Function 1 → (<bit-No.> of <EAd>) Bit- BSET manipulation Sets a specified bit in a general register or memory instructions operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 85 Type Instruction Size Function C ⊕ (<bit-No.> of <EAd>) → C Bit- BXOR manipulation Exclusive-ORs the carry flag with a specified bit in a instructions general register or memory operand and stores the result in the carry flag. C ⊕ [¬ (<bit-No.> of <EAd>) ] → C BIXOR Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand...
Page 86 Type Instruction Size Function Branch — Branches to a specified address if a specified condition instructions is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never C ∨ Z = 0 High C ∨...
Page 87 Type Instruction Size Function System control TRAPA — Starts trap-instruction exception handling. instructions — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR.
Page 88: Basic Instruction Formats
Type Instruction Size Function if R4L ≠ 0 then Block data EEPMOV.B — Repeat @ER5+ → @ER6+ transfer R4L–1 → R4L instruction Until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next;...
Page 89 Figure 2-12 shows examples of instruction formats. (1) Operation field only NOP, RTS, etc. (2) Operation field and register fields ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field EA (disp) BRA d:16, etc...
Page 90: Addressing Modes And Effective Address Calculation
Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
Page 91 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) H'000000 to H'FFFFFF Program instruction 24 bits (@aa:24) address Note: * Not available in the H8S/2646 Series.
Page 92 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Note: * Not available in the H8S/2646 Series.
Page 93: Effective Address Calculation
(a) Normal Mode * (b) Advanced Mode Note: * Not available in the H8S/2646 Series. Figure 2-13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address.
Page 94 Table 2-6 Effective Address Calculation...
Page 97: Processing States
Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-14 shows a diagram of the processing states. Figure 2-15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped.
Page 98: Reset State
End of bus request Bus request Program execution state Bus-released state Sleep mode External interrupt request Software standby mode Exception handling state RES= High STBY= High, RES= Low Reset state Hardware standby mode Power-down state From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: *1 goes low.
Page 99: Exception-Handling State
2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions.
Page 100 (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. The CPU enters the reset state when the RES is low. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address.
Page 101 (b) Interrupt control mode 2 Advanced mode Reserved (24 bits) (24 bits) (c) Interrupt control mode 0 (d) Interrupt control mode 2 Notes: *1 Ignored when returning. *2 Not available in the H8S/2646 Series. Figure 2-16 Stack Structure after Exception Handling (Examples)
Page 102: Program Execution State
2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. Bus masters other than the CPU is data transfer controller (DTC).
Page 103: Basic Timing
Basic Timing 2.9.1 Overview The H8S/2600 CPU is driven by a system clock, denoted by the symbol ø. The period from one rising edge of ø to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states.
Page 104 Bus cycle ø Address bus Held High High HWR, LWR High Data bus High-impedance state Figure 2-18 Pin States during On-Chip Memory Access...
Page 105: On-Chip Supporting Module Access Timing
2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2-19 shows the access cycle for the on-chip supporting modules. Figure 2-20 shows the pin states. Bus cycle ø...
Page 106 Bus cycle ø Held Address bus High High HWR, LWR High Data bus High-impedance state Figure 2-20 Pin States during On-Chip Supporting Module Access...
Page 107: On-Chip Hcan Module Access Timing
2.9.4 On-Chip HCAN Module Access Timing On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access cycle is shown in figures 2-21 and 2-22, and the pin states in figure 2-23.
Page 108: External Address Space Access Timing
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used.
Page 109 The BCLR instruction can be used to clear the flag of an internal I/O register to 0. In that case, if it is clearly known that the pertinent flag is set to 1 in an interrupt processing routine or other processing, there is no need to read the flag in advance.
Page 111: Section 3 Mcu Operating Modes
3.1.1 Operating Mode Selection The H8S/2646 Series has four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0).
Page 112: Register Configuration
The H8S/2646 Series can be used only in modes 4 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Register Configuration...
Page 113: System Control Register (Syscr)
3.2.2 System Control Register (SYSCR) MACS — INTM1 INTM0 NMIEG — — RAME Initial value — — SYSCR is an 8-bit readable-writable register that selects saturating or non-saturating calculation for the MAC instruction, selects the interrupt control mode, selects the detected edge for NMI, and enables or disenables on-chip RAM.
Page 114: Pin Function Control Register (Pfcr)
Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG Description An interrupt is requested at the falling edge of NMI input (Initial value) An interrupt is requested at the rising edge of NMI input Bit 2—...
Page 115 Bit 3 Bit 2 Bit 1 Bit 0 Description A8–A23 address output disabled (Initial value*) A8 address output enabled; A9–A23 address output disabled A8, A9 address output enabled; A10–A23 address output disabled A8–A10 address output enabled; A11–A23 address output disabled A8–A11 address output enabled;...
Page 116: Operating Mode Descriptions
Operating Mode Descriptions 3.3.1 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C, function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals.
Page 117: Pin Functions In Each Operating Mode
*: After reset Address Map in Each Operating Mode A address maps of the H8S/2646 Series are shown in figures 3-1 (1) and 3-1 (2). The address space is 16 Mbytes in modes 4 to 7 (advanced modes). The address space is divided into eight areas for modes 4 to 7. For details, see section 7, Bus...
Page 118 On-chip RAM* On-chip RAM* On-chip RAM H'FFFFFF H'FFFFFF H'FFFFFF Note: * External addresses can be accessed by clearing th RAME bit in SYSCR to 0. Figure 3-1 (1) Address Map in Each Operating Mode in the H8S/2646, H8S/2646R, H8S/2648, and H8S/2648R...
Page 119 Modes 4 and 5 Mode 6 Mode 7 (advanced expanded modes (advanced expanded mode (advanced single-chip mode) with on-chip ROM disabled) with on-chip ROM enabled) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM H'00FFFF H'00FFFF H'010000 H'010000 External address space Reserved area Reserved area H'01FFFF H'01FFFF...
Page 121: Section 4 Exception Handling
Section 4 Exception Handling Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, direct transition, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Page 122: Exception Handling Operation
Reset Trace Exception External interrupts: NMI, IRQ5 to IRQ0 sources Internal interrupts: Interrupts from on-chip supporting modules Interrupts 43 sources in the H8S/2646, H8S/2646R, and H8S/2645 47 sources in the H8S/2648, H8S/2648R, and H8S/2647 Trap instruction Figure 4-1 Exception Sources...
Page 123 Table 4-2 Exception Vector Table Vector Address Exception Source Vector Number Advanced Mode Reset H'0000 to H'0003 Reserved for system use H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 Trace H'0014 to H'0017 Direct Transition H'0018 to H'001B External interrupt H'001C to H'001F Trap instruction (4 sources)
Page 124: Reset
Immediately after a reset, interrupt control mode 0 is set. When the RES pin goes from low to high, reset exception handling starts. The H8S/2646 Series can also be reset by overflow of the watchdog timer. For details see section 12, Watchdog Timer.
Page 125 Vector Internal Prefetch of first program fetch processing instruction ø Internal address bus Internal read signal Internal write High signal Internal data (1) (3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) Start address ((5) = (2) (4)) First program instruction Figure 4-2 Reset Sequence (Modes 6 and 7)
Page 126: Interrupts After Reset
Vector Internal Prefetch of first program fetch processing instruction Ø Address bus HWR, LWR High D15 to D0 (1) (3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) Start address ((5) = (2) (4)) First program instruction Note: * 3 program wait states are inserted.
Page 127: State Of On-Chip Supporting Modules After Reset Release
4.2.4 State of On-Chip Supporting Modules after Reset Release After reset release, MSTPCRA to MSTPCRD are initialized to H'3F, H'FF, H'FF, and B'11****** , respectively, and all modules except the DTC, enter module stop mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited.
Page 128: Interrupts
Interrupt exception handling can be requested by seven external sources (NMI, IRQ5 to IRQ0) and internal sources (43 sources in the H8S/2646, H8S/2646R, and H8S/2645, and 47 sources in the H8S/2648, H8S/2648R, and H8S/2647) in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources and the number of interrupts of each type.
Page 129: Trap Instruction
Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code.
Page 130: Stack Status After Exception Handling
(a) Interrupt control mode 0 (b) Interrupt control mode 2 Note: * Ignored on return. Figure 4-5 (1) Stack Status after Exception Handling (Normal Modes: Not Available in the H8S/2646 Series) Reserved* (24 bits) (24 bits) (a) Interrupt control mode 0 (b) Interrupt control mode 2 Note: * Ignored on return.
Page 131: Notes On Use Of The Stack
Notes on Use of the Stack When accessing word data or longword data, the H8S/2646 Series assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W...
Page 133: Section 5 Interrupt Controller
Overview 5.1.1 Features The H8S/2646 Series controls interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two interrupt control modes  Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR).
Page 134: Block Diagram
5.1.2 Block Diagram A block diagram of the interrupt controller is shown in Figure 5-1. INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit Interrupt request IRQ input unit IRQ input Vector number Priority ISCR determination Internal interrupt request I2 to I0 SWDTEND to Interrupt controller Legend...
Page 135: Pin Configuration
5.1.3 Pin Configuration Table 5-1 summarizes the pins of the interrupt controller. Table 5-1 Interrupt Controller Pins Name Symbol Function Nonmaskable interrupt Input Nonmaskable external interrupt; rising or falling edge can be selected IRQ5 to IRQ0 Input External interrupt Maskable external interrupts; rising, falling, or requests 5 to 0 both edges, or level sensing, can be selected 5.1.4...
Page 136: Register Descriptions
Register Descriptions 5.2.1 System Control Register (SYSCR) MACS — INTM1 INTM0 NMIEG — — RAME Initial value — — SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR).
Page 137: Interrupt Priority Registers A To H, J, K, M (Ipra To Iprh, Iprj, Iprk, Iprm)
Notes: *1 Reserved. These bits are always read as 1 and cannot be modified. *2 In the H8S/2646, H8S/2646R, and H8S/2645 these are reserved bits that are always read as 1 and should only be written with H'7. In the H8S/2648, H8S/2648R, and...
Page 138: Irq Enable Register (Ier)
As shown in table 5-3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt.
Page 139: Irq Sense Control Registers H And L (Iscrh, Iscrl)
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH — — — — IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ5 to IRQ0.
Page 140: Irq Status Register (Isr)
5.2.5 IRQ Status Register (ISR) — — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt requests.
Page 141: Interrupt Sources
There are seven external interrupts: NMI and IRQ5 to IRQ0. Of these, NMI and IRQ5 to IRQ0 can be used to restore the H8S/2646 Series from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits.
Page 142: Internal Interrupts
There are 47 sources in the H8S/2648, H8S/2648R, and H8S/2647 and 43 sources in the H8S/2646, H8S/2646R, and H8S/2645 for internal interrupts from on-chip supporting modules. • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts.
Page 143 Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address Origin of Interrupt Vector Advanced Interrupt Source Source Number Mode Priority External H'001C High IRQ0 H'0040 IPRA6 to 4 IRQ1 H'0044 IPRA2 to 0 IRQ2 H'0048 IPRB6 to 4 IRQ3 H'004C IRQ4...
Page 144 Vector Address Origin of Interrupt Vector Advanced Interrupt Source Source Number Mode Priority TGI1A (TGR1A input H'00A0 IPRF2 to 0 High capture/compare match) channel 1 TGI1B (TGR1B input H'00A4 capture/compare match) TCI1V (overflow 1) H'00A8 TCI1U (underflow 1) H'00AC TGI2A (TGR2A input H'00B0 IPRG6 to 4 capture/compare match)
Page 145 — H'01B8 H'01BC Reserved for system use — H'01C0 — H'01FC Notes: *1 Lower 16 bits of the start address. *2 These vectors are used in the H8S/2648, H8S/2648R, and H8S/2647. They are reserved in the H8S/2646, H8S/2646R, and H8S/2645.
Page 146: Interrupt Operation
5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2646 Series differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt.
Page 147 Figure 5-4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 Interrupt acceptance control Default priority Interrupt source Vector number determination 8-level mask control I2 to I0 Interrupt control mode 2 Figure 5-4 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR.
Page 148 8-Level Control: In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level.
Page 149: Interrupt Control Mode 0
5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1.
Page 150 Program execution status Interrupt generated? Hold pending IRQ0 IRQ1 HCAN Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0...
Page 151: Interrupt Control Mode 2
5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5-6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller.
Page 152 Program execution status Interrupt generated? Level 7 interrupt? Level 6 interrupt? Mask level 6 Level 1 interrupt? or below? Mask level 5 or below? Mask level 0? Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in...
Page 153: Interrupt Exception Handling Sequence
5.4.4 Interrupt Exception Handling Sequence Figure 5-7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Figure 5-7 Interrupt Exception Handling...
Page 154: Interrupt Response Times
5.4.5 Interrupt Response Times The H8S/2646 Series is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high- speed processing. Table 5-9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine.
Page 155: Usage Notes
Table 5-10 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus 16 Bit Bus Internal 2-State 3-State 2-State 3-State Symbol Memory Access Access Access Access Instruction fetch 6+2m Branch address read Stack manipulation Legend m: Number of wait states in an external device access.
Page 156: Instructions That Disable Interrupts
TIER0 write cycle by CPU TCIV exception handling ø Internal TIER0 address address bus Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5-8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.
Page 157: Interrupts During Execution Of Eepmov Instruction
5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle.
Page 158: Operation
Interrupt DTC activation request request vector Selection number circuit Select interrupt signal Control logic Clear signal DTCER Interrupt source On-chip Clear signal clear signal supporting module DTVECR SWDTE CPU interrupt clear signal request vector number Determination of priority I, I2 to I0 Interrupt controller Figure 5-9 Interrupt Control for DTC 5.6.3...
Page 159 Table 5-11 Interrupt Source Selection and Clearing Control Settings Interrupt Source Selection/Clearing Control DTCE DISEL ∆ ∆ ∆ Legend ∆ : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used.
Page 161: Pc Break Controller (Pbc)
Section 6 PC Break Controller (PBC) Overview The PC break controller (PBC) provides functions that simplify program debugging. Using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC: instruction fetch, data read, data write, and data read/write.
Page 162: Block Diagram
6.1.2 Block Diagram Figure 6-1 shows a block diagram of the PC break controller. BARA BCRA Mask control Control Comparator logic Match signal Internal address PC break interrupt Access status Control Comparator logic Match signal Mask control BARB BCRB Figure 6-1 Block Diagram of PC Break Controller...
Page 163: Register Configuration
6.1.3 Register Configuration Table 6-1 shows the PC break controller registers. Table 6-1 PC Break Controller Registers Initial Value Name Abbreviation Reset Address Break address register A BARA H'XX000000 H'FE00 Break address register B BARB H'XX000000 H'FE04 Break control register A BCRA R/(W) H'00...
Page 164: Break Address Register B (Barb)
6.2.2 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Break Control Register A (BCRA) CMFA BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA Initial value Read/Write R/(W)* Note:* Only a 0 may be written to this bit to clear the flag.
Page 165 Bits 5 to 3—Break Address Mask Register A2 to A0 (BAMRA2–BAMRA0): These bits specify which bits of the break address (BAA23–BAA0) set in BARA are to be masked. Bit 5 Bit 4 Bit 3 BAMRA2 BAMRA1 BAMRA0 Description All BARA bits are unmasked and included in break conditions (Initial value) BAA0 (lowest bit) is masked, and not included in break conditions...
Page 166: Break Control Register B (Bcrb)
6.2.4 Break Control Register B (BCRB) BCRB is the channel B break control register. The bit configuration is the same as for BCRA. 6.2.5 Module Stop Control Register C (MSTPCRC) MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value Read/Write MSTPCRC is an 8-bit readable/writable register that performs module stop mode control.
Page 167: Operation
Operation The operation flow from break condition setting to PC break interrupt exception handling is shown in sections 6.3.1, PC Break Interrupt Due to Instrunction Fetch, and 6.3.2, PC Break Interrupt Due to Data Access, taking the example of channel A. 6.3.1 PC Break Interrupt Due to Instruction Fetch 1.
Page 168: Notes On Pc Break Interrupt Handling
2. Satisfaction of break condition  After execution of the instruction that performs a data access on the set address, a PC break request is generated and the condition match flag (CMFA) is set. 3. Interrupt handling  After priority determination by the interrupt controller, PC break interrupt exception handling is started.
Page 169: Pc Break Operation In Continuous Data Transfer
After execution of the SLEEP instruction, and following the clock oscillation settling time, a transition is made to high-speed (medium-speed) mode via direct transition exception handling. After the transition, PC break interrupt handling is executed, then the instruction at the address after the SLEEP instruction is executed (figure 6-2 (C)). 4.
Page 170: When Instruction Execution Is Delayed By One State
6.3.6 When Instruction Execution is Delayed by One State Caution is required in the following cases, as instruction execution is one state later than usual. 1. When the PBC is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a one-word branch instruction (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, or RTS) located in on- chip ROM or RAM is always delayed by one state.
Page 171: Additional Notes
6.3.7 Additional Notes 1. When a PC break is set for an instruction fetch at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction: Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the instruction fetch at the next address.
Page 173: Section 7 Bus Controller
Section 7 Bus Controller Overview The H8S/2646 Series has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily.
Page 174: Block Diagram
7.1.2 Block Diagram Figure 7-1 shows a block diagram of the bus controller. Internal Area decoder address bus ABWCR External bus control signals ASTCR BCRH BCRL Internal control controller signals Bus mode signal Wait WAIT controller WCRH WCRL CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal...
Page 175: Pin Configuration
7.1.3 Pin Configuration Table 7-1 summarizes the pins of the bus controller. Table 7-1 Bus Controller Pins Name Symbol Function Address strobe Output Strobe signal indicating that address output on address bus is enabled. Read Output Strobe signal indicating that external space is being read.
Page 176: Register Descriptions
Register Descriptions 7.2.1 Bus Width Control Register (ABWCR) ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes 5 to 7 Initial value : Mode 4 Initial value : ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access.
Page 177 ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode.
Page 178: Wait Control Registers H And L (Wcrh, Wcrl)
7.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode.
Page 179 Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 Bit 2 Description Program wait not inserted when external space area 5 is accessed...
Page 180 WCRL Initial value Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
Page 181 Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 Bit 2 Description Program wait not inserted when external space area 1 is accessed...
Page 182: Bus Control Register H (Bcrh)
7.2.4 Bus Control Register H (BCRH) ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 — — — Initial value BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. BCRH is initialized to H'D0 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Page 183: Bus Control Register L (Bcrl)
Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value) Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access.
Page 184: Pin Function Control Register (Pfcr)
Bit 1—Write Data Buffer Enable (WDBE): This bit selects whether or not to use the write buffer function in the external write cycle. Bit 1 WDBE Description Write data buffer function not used (Initial value) Write data buffer function used Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by means of the WAIT pin.
Page 185 Bits 3 to 0—Address Output Enable 3 to 0 (AE3–AE0): These bits select enabling or disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is enabled for address output, the address is output regardless of the corresponding DDR setting. When a pin is disabled for address output, it becomes an output port when the corresponding DDR bit is set to 1.
Page 186: Overview Of Bus Control
7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, it controls a 64-kbyte address space comprising part of area 0. Figure 7-2 shows an outline of the memory map. Note: * Not available in the H8S/2646 Series. H'000000 H'0000...
Page 187: Bus Specifications
7.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller.
Page 188: Memory Interfaces
7.3.3 Memory Interfaces The H8S/2646 Series memory interfaces comprise a basic bus interface that allows direct connection or ROM, SRAM, and so on, and a burst ROM interface that allows direct connection of burst ROM. The memory interface can be selected independently for each area.
Page 189: Interface Specifications For Each Area
7.3.4 Interface Specifications for Each Area The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (sections 7.4, Basic Bus Interface and 7.5, Burst ROM Interface) should be referred to for further details.
Page 190: Basic Bus Interface
Basic Bus Interface 7.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 7-3). 7.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data...
Page 191 16-Bit Access Space: Figure 7-4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions.
Page 192: Valid Strobes
7.4.3 Valid Strobes Table 7-4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
Page 193: Basic Timing
7.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 7-5 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle ø...
Page 194 8-Bit 3-State Access Space: Figure 7-6 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle ø...
Page 195 16-Bit 2-State Access Space: Figures 7-7 to 7-9 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted.
Page 196 Bus cycle ø Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Figure 7-8 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)
Page 197 Bus cycle ø Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Figure 7-9 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)
Page 198 16-Bit 3-State Access Space: Figures 7-10 to 7-12 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted.
Page 199 Bus cycle ø Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Figure 7-11 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)
Page 200 Bus cycle ø Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Figure 7-12 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)
Page 201: Wait Control
7.4.5 Wait Control When accessing external space, the H8S/2646 Series can extend the bus cycle by inserting one or more wait states (T ). There are two ways of inserting wait states: program wait insertion. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T...
Page 202 Figure 7-13 shows an example of wait state insertion timing. By WAIT pin By program wait ø WAIT Address bus Read Data bus Read data HWR, LWR Write Data bus Write data Note: Downward arrows show the timing of WAIT pin sampling. Figure 7-13 Example of Wait State Insertion Timing The settings after a reset are: 3-state access, 3 program wait state insertion.
Page 203: Burst Rom Interface
Burst ROM Interface 7.5.1 Overview In this LSI, the area 0 external space can be set as burst ROM space and burst ROM interfacing performed. Burst ROM space interfacing allows 16-bit ROM capable of burst access to be accessed at high-speed. The BRSTRM bit of BCRH sets area 0 as burst ROM space.
Page 204 Full access Burst access ø Low address only changes Address bus Data bus Read data Read data Read data Figure 7.14 (a) Example Burst ROM Access Timing (AST0=BRSTS1=1) Full access Burst access ø Low address only changes Address bus Data bus Read data Read data Read data Figure 7.14 (b) Example Burst ROM Access Timing (AST0=BRSTS1=0)
Page 205: Wait Control
7.5.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the burst ROM interface initial cycle (full access). See section 7.4.5, Wait Control. Wait states cannot be inserted in the burst cycle.
Page 206: Idle Cycle
Idle Cycle 7.6.1 Operation When the H8S/2646 Series accesses external space , it can insert a 1-state idle cycle (T ) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on.
Page 207 (2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 7-16 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
Page 208 (3) Relationship between Chip Select (CS*) Signal and Read (RD) Signal Depending on the system’s load conditions, the RD signal may lag behind the CS signal*. An example is shown in figure 7-17. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal.
Page 209: Pin States During Idle Cycles
7.6.2 Pin States During Idle Cycles Table 7-5 shows the pin states during idle cycles. Table 7-5 Pin States During Idle Cycles Pins Pin State A23 to A0 Content identical to immediately following bus cycle D15 to D0 High impedance High level High level High level...
Page 210: Write Data Buffer Function
Write Data Buffer Function The H8S/2646 Series has a write data buffer function in the external data bus. Using this function enables external writes to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1.
Page 211: Bus Arbitration
7.8.1 Overview The H8S/2646 Series has a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and DTC which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal.
Page 212: Resets And The Bus Controller
(3 states), a single data transfer, or a register information write (3 states). Resets and the Bus Controller In a reset, the H8S/2646 Series, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued.
Page 213: Data Transfer Controller (Dtc)
Section 8 Data Transfer Controller (DTC) Overview The H8S/2646 Series includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 8.1.1 Features • Transfer possible over any number of channels  Transfer information is stored in memory ...
Page 214: Block Diagram
8.1.2 Block Diagram Figure 8-1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information.
Page 215: Register Configuration
8.1.3 Register Configuration Table 8-1 summarizes the DTC registers. Table 8-1 DTC Registers Name Abbreviation Initial Value Address DTC mode register A — Undefined — DTC mode register B — Undefined — DTC source address register — Undefined — DTC destination address register —...
Page 216: Register Descriptions
Register Descriptions 8.2.1 DTC Mode Register A (MRA) Initial value — — — — — — — — *: Undefined MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer.
Page 217 Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 Bit 2 Description Normal mode Repeat mode Block transfer mode — Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode.
Page 218: Dtc Mode Register B (Mrb)
After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0) Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2646 Series, and should always be written with 0.
Page 219: Dtc Source Address Register (Sar)
8.2.3 DTC Source Address Register (SAR) Initial value — — — — — — — — — — *: Undefined SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 8.2.4 DTC Destination Address Register (DAR) Initial value...
Page 220: Dtc Transfer Count Register B (Crb)
In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00.
Page 221: Dtc Vector Register (Dtvecr)
Bit n—DTC Activation Enable (DTCEn) Bit n DTCEn Description DTC activation by this interrupt is disabled (Initial value) [Clearing conditions] • When the DISEL bit is 1 and the data transfer has ended • When the specified number of transfers have ended DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended...
Page 222: Module Stop Control Register A (Mstpcra)
Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. Bit 7 SWDTE Description DTC software activation is disabled (Initial value) [Clearing conditions] • When the DISEL bit is 0 and the specified number of transfers have not ended •...
Page 223 Bit 6—Module Stop (MSTPA6): Specifies the DTC module stop mode. Bit 6 MSTPA6 Description DTC module stop mode cleared (Initial value) DTC module stop mode set...
Page 224: Operation
Operation 8.3.1 Overview When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage of register information in memory makes it possible to transfer data over any required number of channels.
Page 225 The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed.
Page 226: Activation Sources
8.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0.
Page 227: Dtc Vector Table
The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip RAM. Note: * Not available in the H8S/2646 Series. DTC vector Register information...
Page 228 Table 8-4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Interrupt Vector Vector Interrupt Source Source Number Address DTCE Priority Write to DTVECR Software DTVECR H'0400+ — High (DTVECR [6:0] <<1) IRQ0 External pin H'0420 DTCEA7 IRQ1 H'0422 DTCEA6 IRQ2 H'0424...
Page 229 Origin of Interrupt Vector Vector Interrupt Source Source Number Address DTCE Priority TGI3A (GR3A compare match/ H'0460 DTCEC5 High input capture) channel 3 TGI3B (GR3B compare match/ H'0462 DTCEC4 input capture) TGI3C (GR3C compare match/ H'0464 DTCEC3 input capture) TGI3D (GR3D compare match/ H'0466 DTCEC2 input capture)
Page 230 110 to 124 H'04DC — H'04FC Notes: *1 DTCE bits with no corresponding interrupt are reserved, and should be written with 0. *2 These vectors are used in the H8S/2648, H8S/2648R, and H8S/2647. They are reserved in the H8S/2646, H8S/2646R, and H8S/2645.
Page 231: Location Of Register Information In Address Space
8.3.4 Location of Register Information in Address Space Figure 8-5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address). In the case of chain transfer, register information should be located in consecutive areas.
Page 232: Normal Mode
8.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 8-5 lists the register information in normal mode and figure 8-6 shows memory mapping in normal mode.
Page 233: Repeat Mode
8.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated.
Page 234: Block Transfer Mode
8.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored.
Page 235 First block · SAR or DAR or · Block area · Transfer Nth block Figure 8-8 Memory Mapping in Block Transfer Mode...
Page 236: Chain Transfer
8.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8-9 shows the memory map for chain transfer.
Page 237: Operation Timing
8.3.9 Operation Timing Figures 8-10 to 8-12 show an example of DTC operation timing. ø DTC activation request request Data transfer Vector read Address Read Write Transfer Transfer information read information write Figure 8-10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ø...
Page 238: Number Of Dtc Execution States
ø DTC activation request request Data transfer Data transfer Vector read Address Read Write Read Write Transfer Transfer Transfer Transfer information information information information read write read write Figure 8-12 DTC Operation Timing (Example of Chain Transfer) 8.3.10 Number of DTC Execution States Table 8-8 lists execution statuses for a single DTC data transfer, and table 8-9 shows the number of states required for each execution status.
Page 239 Table 8-9 Number of States Required for Each Execution Status Chip Chip On-Chip I/O Object to be Accessed Registers External Devices Bus width Access states Execution Vector read — — — 6+2m 2 status Register — — — — — —...
Page 240: Procedures For Using Dtc
8.3.11 Procedures for Using DTC Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1.
Page 241: Examples Of Use Of The Dtc
8.3.12 Examples of Use of the DTC Normal Mode: An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0).
Page 242 Chain Transfer: An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU’s TGR in the second half.
Page 243 Software Activation: An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. [1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0).
Page 244: Interrupts
Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control.
Page 245: Section 9 I/O Ports
Section 9 I/O Ports Overview The H8S/2646 Series has 13 I/O ports (ports 1 to 3, 5 and A to F, H, J, K), and two input-only port (ports 4 and 9). Table 9-1 summarizes the port functions. The pins of each port also have other functions.
Page 246 Table 9-1 (1) Port Functions (H8S/2646, H8S/2646R, H8S/2645) Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port 1 • 8-bit I/O P17/PO15/TIOCB2 TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, port /TCLKD TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2), PPG output pins (PO15 to PO8), and interrupt input •...
Page 247 Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port 5 • 3-bit I/O 3-bit I/O port port Port 9 • 8-bit input A/D converter analog input (AN11 to AN8) and 8-bit input port port P93/AN11 P92/AN10 P91/AN9 P90/AN8 Port A •...
Page 248 Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port D • 8-bit I/O PD7/D15 Data bus I/O 8-bit I/O port port PD6/D14 • Built-in PD5/D13 MOS input PD4/D12 pull-up PD3/D11 PD2/D10 PD1/D9 PD0/D8 Port E • 8-bit I/O PE7/D7 8-bit I/O port in 8-bit bus mode 8-bit I/O port...
Page 249 Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port J • 8-bit I/O PJ7/PWM2H Motor control PWM timer (channel 2) output pins (PWM2A to port PWM2H) and 8-bit I/O port PJ6/PWM2G PJ5/PWM2F PJ4/PWM2E PJ3/PWM2D PJ2/PWM2C PJ1/PWM2B PJ0/PWM2A Port K •...
Page 250 Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port 3 • 8-bit I/O SCI (channels 0, 1) I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1), interrupt input pins (IRQ4, IRQ5), and 8-bit I/O port port • Open-drain P35/SCK1/IRQ5 output P34/RxD1...
Page 251 Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port B • 8-bit I/O PB7/A15/SEG32 LCD segment output (SEG25 to SEG32), LCD segment port address output (A15 to A8), and 8-bit I/O port output (SEG25 PB6/A14/SEG31 to SEG32) and •...
Page 252 Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port F • 7-bit I/O PF7/φ If DDR = 0: input port port If DDR = 1: φ output LCD segment output (SEG34 to SEG36) and LCD segment PF6/AS/SEG36 bus control signals (AS, RD, HWR) output (SEG34 PF5/RD/SEG35...
Page 253: Port 1
Port 1 9.2.1 Overview Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and external interrupt pins (IRQ0 and IRQ1). Port 1 pin functions change according to the operating mode.
Page 254: Register Configuration
9.2.2 Register Configuration Table 9-2 shows the port 1 register configuration. Table 9-2 Port 1 Registers Name Abbreviation Initial Value Address* Port 1 data direction register P1DDR H'00 H'FE30 Port 1 data register P1DR H'00 H'FF00 Port 1 register PORT1 Undefined H'FFB0 Note: * Lower 16 bits of the address.
Page 255 Port 1 Register (PORT1) Initial value : —* —* —* —* —* —* —* —* Note: * Determined by state of pins P17 to P10. PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 1 pins (P17 to P10) must always be performed on P1DR.
Page 256: Pin Functions
9.2.3 Pin Functions Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and external interrupt input pins (IRQ0 and IRQ1). Port 1 pin functions are shown in table 9-3.
Page 257 Selection Method and Pin Functions P16/PO14/ The pin function is switched as shown below according to the combination of TIOCA2/ the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 IRQ1 in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bit NDER14 in NDERH, and bit P16DDR.
Page 258 Selection Method and Pin Functions P15/PO13/ The pin function is switched as shown below according to the combination of TIOCB1/TCLKC the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR.
Page 259 Selection Method and Pin Functions P14/PO12/ The pin function is switched as shown below according to the combination of TIOCA1/IRQ0 the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bit NDER12 in NDERH, and bit P14DDR.
Page 260 Selection Method and Pin Functions P13/PO11/ The pin function is switched as shown below according to the combination of TIOCD0/TCLKB the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bit NDER11 in NDERH, and bit P13DDR.
Page 261 Selection Method and Pin Functions P12/PO10/ The pin function is switched as shown below according to the combination of TIOCC0/TCLKA the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bit NDER10 in NDERH, and bit P12DDR.
Page 262 Selection Method and Pin Functions P11/PO9/TIOCB0 The pin function is switched as shown below according to the combination of the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, and bits IOB3 to IOB0 in TIOR0H), bit NDER9 in NDERH, and bit P11DDR.
Page 263 Selection Method and Pin Functions P10/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bit NDER8 in NDERH, SAE0 bit in DMABCRH, and bit P10DDR.
Page 264: Port2
Port 2 9.3.1 Overview Port 2 is an 8-bit I/O port. Port 2 also functions as TPU I/O pins (TIOCB5, TIOCA5, TIOCB4, TIOCA4, TIOCD3, TIOCC3, TIOCB3, TIOCA3). The pin functions of port 2 change with the operating mode. Figure 9-2 shows the pin functions for port 2. Port 2 pins (I/O) / TIOCB5 (I/O) (I/O) / TIOCA5 (I/O)
Page 265 Port 2 Data Direction Register (P2DDR) P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : P2DDR is an 8-bit write-only register that specifies whether individual bits are input or output for each of the pins in port 2. It is not possible to read it. An undefined value is returned if an attempt is made to read it.
Page 266: Pin Functions
P2DDR and P2DR are initialized if a reset occurs and in the hardware standby mode, so the content of PORT2 is determined by the pin states. The previous states are retained in the software standby mode. 9.3.3 Pin Functions The port 2 pins also function as TPU I/O pins (TIOCB5, TIOCA5, TIOCB4, TIOCA4, TIOCD3, TIOCC3, TIOCB3, TIOCA3).
Page 267 Selection Method and Pin Functions P26/TIOCA5 Switches as follows according to the combinations of the TPU channel 5 setting made using bits MD3 to MD0 of TMDR5, bits IOA3 to IOA0 of TIOR5, and bits CCLR1 and CCLR0 of TCR5, as well as the P26DDR bit. TPU Channel 5 Setting Table Below (1)
Page 268 Selection Method and Pin Functions P25/TIOCB4 Switches as follows according to the combinations of the TPU channel 4 setting made using bits MD3 to MD0 of TMDR4, bits IOB3 to IOB0 of TIOR4, and bits CCR1 and CCR0 of TCR4, as well as the P25DDR bit. TPU Channel 4 Setting Table Below (1)
Page 269 Selection Method and Pin Functions P24/TIOCA4 Switches as follows according to the combinations of the TPU channel 4 setting made using bits MD3 to MD0 of TMDR4, bits IOA3 to IOA0 of TIOR4, and bits CCR1 and CCR0 of TCR4, as well as the P24DDR bit. TPU Channel 4 Setting Table Below (1)
Page 270 Selection Method and Pin Functions P23/TIOCD3 Switches as follows according to the combinations of the TPU channel 3 setting made using bits MD3 to MD0 of TMDR3, bits IOD3 to IOD0 of TIOR3L, and bits CCLR2 to CCLR0 of TCR3, as well as the P23DDR bit. TPU Channel 3 Setting Table Below (1)
Page 271 Selection Method and Pin Functions P22/TIOCC3 Switches as follows according to the combinations of the TPU channel 3 setting made using bits MD3 to MD0 of TMDR3, bits IOC3 to IOC0 of TIOR3L, and bits CCR2 to CCR0 of TCR3, as well as the P22DDR bit. TPU Channel 3 Setting Table Below (1)
Page 272 Selection Method and Pin Functions P21/TIOCB3 Switches as follows according to the combinations of the TPU channel 3 setting made using bits MD3 to MD0 of TMDR3, bits IOB3 to IOB0 of TIOR3L, and bits CCR2 to CCR0 of TCR3, as well as the P21DDR bit. TPU Channel 3 Setting Table Below (1)
Page 273 Selection Method and Pin Functions P20/TIOCA3 Switches as follows according to the combinations of the TPU channel 3 setting made using bits MD3 to MD0 of TMDR3, bits IOA3 to IOA0 of TIOR3L, and bits CCR2 to CCR0 of TCR3, as well as the P20DDR bit. TPU Channel 3 Setting Table Below (1)
Page 274: Port3
Port 3 9.4.1 Overview Port 3 is an 8-bit I/O port. Port 3 is a multi-purpose port for SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1), and external interrupt input pins (IRQ4, IRQ5). All of the port 3 pin functions have the same operating mode.
Page 275 Port 3 Data Direction Register (P3DDR) P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value Read/Write P3DDR is an 8-bit write-dedicated register, which specifies the I/O for each port 3 pin by bit. Read is disenabled. If a read is carried out, undefined values are read out. By setting P3DDR to 1, the corresponding port 3 pins become output, and be clearing to 0 they become input.
Page 276 Port 3 Register (PORT3) Initial value —* —* —* —* —* —* —* —* Read/Write Note: * Determined by the state of pins P37 to P30. PORT3 is an 8-bit read-dedicated register, which reflects the state of pins. Write is disenabled. Always carry out writing off output data of port 3 pins (P37 to P30) to P3DR without fail.
Page 277: Pin Functions
9.4.3 Pin Functions The port 3 pins also function as SCI I/O input pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1) and as external interrupt input pins (IRQ4 and IRQ5). The functions of port 3 pins are shown in Table 9-7. Table 9-7 Port 3 Pin Functions Selection Method and Pin Functions...
Page 278 Selection Method and Pin Functions P33/TxD1 Switches as follows according to combinations of bit TE of SCR1 and bit P33DDR. P33DDR — Pin function P33 input pin P33 output pin* TxD1 output pin* Note: * When P33ODR = 1, it becomes NMOS open drain output. P32/SCK0/ Switches as follows according to combinations of bit C/A of SMR0, bits CKE0 and IRQ4...
Page 279: Port 4
Port 4 9.5.1 Overview Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7). Port 4 pin functions are the same in all operating modes. Figure 9-4 shows the port 4 pin configuration.
Page 280: Register Configuration
9.5.2 Register Configuration Table 9-8 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a data direction register or data register. Table 9-8 Port 4 Registers Name Abbreviation Initial Value Address* Port 4 register PORT4 Undefined H'FFB3...
Page 281: Port 5
9-5 (1) and 9-5 (2) show the pin functions for port 5. Port 5 pins Port 5 (I/O) (I/O) (I/O) Figure 9-5 (1) Port 5 Pin Functions (H8S/2646, H8S/2646R, H8S/2645) Port 5 pins Port 5 (I/O) / SCK2 (I/O) (I/O) / RxD2 (input) (I/O) / TxD2 (output)
Page 282: Register Configuration
9.6.2 Register Configuration Table 9-9 shows the port 5 register configuration. Table 9-9 Port 5 Register Configuration Name Abbreviation Initial Value Address Port 5 data direction register P5DDR H'FE34 Port 5 data register P5DR H'FF04 Port 5 register PORT5 H'FFB4 Notes: *1 Lower 16 bits of the address.
Page 283: Pin Functions
H8S/2647, port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2). Table 9-10 (1) Port 5 Pin Functions (H8S/2646, H8S/2646R, H8S/2645) Selection Method and Pin Functions Switches as follows according to the setting of the P52DDR bit.
Page 284 Table 9-10 (2) Port 5 Pin Functions (H8S/2648, H8S/2648R, H8S/2647) Selection Method and Pin Functions P52/SCK2 Switches as follows according to a combination of the C/A bit in SMR and bits CKE0 and CKE1 in SCR of SCI2, and the P52DDR bit. CKE1 —...
Page 285: Port 9
Port 9 9.7.1 Overview Port 9 is an 8-bit input-only port. Port 9 pins also function as A/D converter analog input pins (AN8 to AN11). Port 9 pin functions are the same in all operating modes. Figure 9-6 shows the port 9 pin configuration.
Page 286: Register Configuration
9.7.2 Register Configuration Table 9-11 shows the port 9 register configuration. Port 9 is an input-only port, and does not have a data direction register or data register. Table 9-11 Port 9 Registers Name Abbreviation Initial Value Address* Port 9 register PORT9 Undefined H'FFB8...
Page 287: Port A
Port A is an 8-bit I/O port. Port A pins also function as address bus outputs and LCD driver output pins (H8S/2646, H8S/2646R, H8S/2645: SEG24 to SEG21 and COM4 to COM1, H8S/2648, H8S/2648R, H8S/2647: SEG40 to Seg37 and COM4 to COM1). The pin functions change according to the operating mode.
Page 288: Register Configuration
9.8.2 Register Configuration Table 9-12 shows the port A register configuration. Table 9-12 Port A Registers Name Abbreviation Initial Value Address* Port A data direction register PADDR H'00 H'FE39 Port A data register PADR H'00 H'FF09 Port A register PORTA Undefined H'FFB9 Port A MOS pull-up control register...
Page 289 Port A Data Register (PADR) PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR Initial value : PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA7 to PA0). PADR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.
Page 290: Pin Functions
Port A MOS Pull-Up Control Register (PAPCR) PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value : PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an individual bit basis. In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in LPCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin.
Page 291 Table 9-13 PA7 to PA4 Pin Functions Selection Method and Pin Functions H8S/2646 PA7/A23 Switches as follows according to the combinations of bits SGS3 to SGS0 of LCD H8S/2646R /SEG24 to driver LPCR, bits AE3 to AE0 of PFGR, and bits PA7DDR to PA4DDR of PADDR.
Page 292: Mos Input Pull-Up Function
9.8.4 MOS Input Pull-Up Function Port A has a built-in MOS input pull-up function that can be controlled by software. MOS input pull-up can be specified as on or off on an individual bit basis. In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in LPCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin.
Page 293: Port B
9.9.1 Overview Port B is an 8-bit I/O port. Port B also functions as LCD driver output pins (H8S/2646, H8S/2646R, H8S/2645: SEG16 to SEG9, H8S/2648, H8S/2648R, H8S/2647: SEG32 to SEG9) and as address bus outputs. The pin functions are determined by the operating mode.
Page 294: Register Configuration
9.9.2 Register Configuration Table 9-16 shows the port B register configuration. Table 9-16 Port B Registers Name Abbreviation Initial Value Address* Port B data direction register PBDDR H'00 H'FE3A Port B data register PBDR H'00 H'FF0A Port B register PORTB Undefined H'FFBA Port B MOS pull-up control register...
Page 295 Port B Register (PORTB) Initial value : —* —* —* —* —* —* —* —* Note: * Determined by state of pins PB7 to PB0. PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port B pins (PB7 to PB0) must always be performed on PBDR.
Page 296: Pin Functions
9.9.3 Pin Functions Port B pins also function as LCD driver output pins (H8S/2646, H8S/2646R, H8S/2645: SEG16 to SEG9, H8S/2648, H8S/2648R, H8S/2647: SEG32 to SEG25) and address bus outputs. The pin functions differ between modes 4 to 6 and mode 7. Port B pin functions are shown in table 9-17.
Page 297: Mos Input Pull-Up Function
9.9.4 MOS Input Pull-Up Function Port B has a built-in MOS input pull-up function that can be controlled by software. MOS input pull-up can be specified as on or off on an individual bit basis. In modes 4 to 6, if a pin is in the input state in accordance with the settings of PFCR, the LCD driver LPCR, and DDR, setting PBPCR to 1 turns on MOS input pull-up.
Page 298: Port C
9.10.1 Overview Port C is an 8-bit I/O port. Port C also functions as LCD driver output pins (H8S/2646, H8S/2646R, H8S/2645: SEG8 to SEG1, H8S/2648, H8S/2648R, H8S/2647: SEG24 to SEG17) and as address bus outputs. The pin functions are determined by the operating mode.
Page 299: Register Configuration
9.10.2 Register Configuration Table 9-19 shows the port C register configuration. Table 9-19 Port C Registers Name Abbreviation Initial Value Address* Port C data direction register PCDDR H'00 H'FE3B Port C data register PCDR H'00 H'FF0B Port C register PORTC Undefined H'FFBB Port C MOS pull-up control register...
Page 300 Port C Register (PORTC) Initial value : —* —* —* —* —* —* —* —* Note: * Determined by state of pins PC7 to PC0. PORTC is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port C pins (PC7 to PC0) must always be performed on PCDR.
Page 301: Pin Functions
9.10.3 Pin Functions Port C can function as LCD segment output pins (H8S/2646, H8S/2646R, H8S/2645: SEG8 to SEG1, H8S/2648, H8S/2648R, H8S/2647: SEG24 to SEG17) and as address bus outputs. The pin functions differ in modes 4, 5, 6, and 7. The port C pin functions are listed in table 9-20.
Page 302: Mos Input Pull-Up Function
9.10.4 MOS Input Pull-Up Function Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis.
Page 303: Port D
9.11 Port D 9.11.1 Overview Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. In the H8S/2648, H8S/2648R, H8S/2647, port D pins also function as LCD driver output pins (SEG16 to SEG9). Port D has a built-in MOS input pull-up function that can be controlled by software.
Page 304: Register Configuration
9.11.2 Register Configuration Table 9-22 shows the port D register configuration. Table 9-22 Port D Registers Name Abbreviation Initial Value Address* Port D data direction register PDDDR H'00 H'FE3C Port D data register PDDR H'00 H'FF0C Port D register PORTD Undefined H'FFBC Port D MOS pull-up control register...
Page 305 Port D Register (PORTD) Initial value : —* —* —* —* —* —* —* —* Note: * Determined by state of pins PD7 to PD0. PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port D pins (PD7 to PD0) must always be performed on PDDR.
Page 306: Pin Functions
The function of pins on port D are as listed in tables 9-23 (1) and 9-23 (2). Table 9-23 (1) Port D Pin Functions (H8S/2646, H8S/2646R, H8S/2645) Pins Method of Selection and Pin Function...
Page 307: Mos Input Pull-Up Function
9.11.4 MOS Input Pull-Up Function Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit basis.
Page 308: Port E
9.12 Port E 9.12.1 Overview Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. In the H8S/2648, H8S/2648R, and H8S/2647, port E pins also function as LCD driver output pins (SEG8 to SEG1).
Page 309: Register Configuration
9.12.2 Register Configuration Table 9-25 shows the port E register configuration. Table 9-25 Port E Registers Address * Name Abbreviation Initial Value Port E data direction register PEDDR H'00 H'FE3D Port E data register PEDR H'00 H'FF0D Port E register PORTE Undefined H'FFBD...
Page 310 Port E Register (PORTE) Initial value : —* —* —* —* —* —* —* —* Note: * Determined by state of pins PE7 to PE0. PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port E pins (PE7 to PE0) must always be performed on PEDR.
Page 311: Pin Functions
9.12.3 Pin Functions The port E pin functions are listed in tables 9-26 (1) and 9-26 (2). Table 9-26 (1) Port E Pin Functions (H8S/2646, H8S/2646R, H8S/2645) Operating mode Modes 4 to 6 Mode 7 Bus width setting 16-bit mode 8-bit mode —...
Page 312 Table 9-27 MOS Input Pull-Up States (Port E) Hardware Software In Other Modes Reset Standby Mode Standby Mode Operations ON/OFF ON/OFF 4 to 6 8-bit bus 16-bit bus Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PEDDR = 0, PEPCR = 1, and the pin is not used as a segment driver; otherwise off.
Page 313: Port F
9.13 Port F 9.13.1 Overview Port F is a 7-bit I/O port. Port F also functions as LCD driver output pins (SEG20 to SEG17), external interrupt input pins (IRQ2, IRQ3), the A/D trigger input pin (ADTRG), bus control signal I/O pins (AS, RD, HWR, LWR, WAIT), and as the system clock output pin (φ). Figure 9-12 shows the port F pin configuration.
Page 314: Register Configuration
9.13.2 Register Configuration Table 9-28 shows the port F register configuration. Table 9-28 Port F Registers Name Abbreviation R/W Initial Value Address Port F data direction register PFDDR H'80/H'00 H'FE3E Port F data register PFDR H'00 H'FF0E Port F register PORTF Undefined H'FFBE...
Page 315 Port F Data Register (PFDR) — PF6DR PF5DR PF4DR PF3DR PF2DR — PF0DR Initial value : undefined — PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF6 to PF2, PF0). PFDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.
Page 316: Pin Functions
Switches as follows according to bit PF7DDR. PF7DDR Pin function PF7 input ø output PF6/AS/SEG20 Switches as follows according to the operating mode and the setting of SGS3 (H8S/2646, to SGS0 and bit PF6DDR. H8S/2646R, H8S/2645) PF6/AS/SEG36 (H8S/2648, Operating Mode...
Page 317 H8S/2648, SEG35 SEG35 H8S/2648R, output output H8S/2647 PF4/HWR/SEG1 Switches as follows according to the operating mode and the setting of SGS3 8 (H8S/2646, to SGS0 and bit PF4DDR. H8S/2646R, H8S/2645) PF4/HWR/SEG34 (H8S/2648, Operating Mode Modes 4 to 6 Mode 7...
Page 318 *2 When used as an external interrupt input pin, do not use it as an I/O pin for other functions. PF2/WAIT/SEG1 Switches as follows according to the operating mode, and the setting of bits 7 (H8S/2646, SGS3 to SGS0, the WAITE bit, and bit PF2DDR. H8S/2646R, H8S/2645)
Page 319: Port H
9.14 Port H 9.14.1 Overview Port H is an 8-bit I/O port. Port H pins also function as motor control PWM timer output pins (PWM1A to PWM1H). Figure 9-13 shows the port H pin configuration. Port H pin PH7 (I/O) / PWM1H (output) PH6 (I/O) / PWM1G (output) PH5 (I/O) / PWM1F (output) PH4 (I/O) / PWM1E (output)
Page 320 Port H Data Direction Register (PHDDR) PH7DDR PH6DDR PH5DDR PH4DDR PH3DDR PH2DDR PH1DDR PH0DDR Initial value : PHDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port H. PHDDR cannot be read. If it is, an undefined value will be read. PHDDR is initialized to H'00 by a reset and in hardware standby mode.
Page 321: Pin Functions
9.14.3 Pin Functions As shown in Table 9-31, the port H pin functions can be switched, bit by bit, by changing the values of OE1A to OE1H of motor control PWM timer PWOCR1 and PHDDR. Table 9-31 Port H Pin Functions OE1A to OE1H PHDDR —...
Page 322: Register Configuration
9.15.2 Register Configuration Table 9-32 shows the port J register configuration. Table 9-32 Port J Registers Name Abbreviation Initial Value Address* Port J data direction register PJDDR H'00 H'FC21 Port J data register PJDR H'00 H'FC25 Port J register PORTJ Undefined H'FC29 Note: * Lower 16 bits of the address...
Page 323: Pin Functions
Port J Register (PORTJ) Initial value : —* —* —* —* —* —* —* —* Note: * Determined by the state of PJ7 to PJ0. PORTJ is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port J pins (PJ7 to PJ0) must always be performed on PJDR.
Page 324: Port K
9.16 Port K 9.16.1 Overview Port K is a 2-bit I/O port. Figure 9-15 shows the pin functions for port K. Port K pins PK7 (I/O) PK6 (I/O) Port K Figure 9-15 Port K Pin Functions 9.16.2 Register Configuration Table 9-34 shows the port A register configuration. Table 9-34 Port K Registers Name Abbreviation...
Page 325 Port K Data Direction Register (PKDDR) PK7DDR PK6DDR — — — — — — Initial value : Undefined Undefined Undefined Undefined Undefined Undefined — — — — — — PKDDR is an 8-bit write-only register that specifies whether individual bits are input or output for each of the pins in port K.
Page 326: Pin Functions
PKDDR and PKDR are initialized if a reset occurs and in the hardware standby mode, so the content of PORTK is determined by the pin states. The previous states are retained in the software standby mode. 9.16.3 Pin Functions The function of the port K pins changes with the operating mode, in accordance with the value of PKDDR, as shown in table 9-35.
Page 327: Section 10 16-Bit Timer Pulse Unit (Tpu)
Section 10 16-Bit Timer Pulse Unit (TPU) 10.1 Overview The H8S/2646 Series has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. 10.1.1 Features • Maximum 16-pulse input/output  A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3,...
Page 328 • Fast access via internal 16-bit bus  Fast access is possible via a 16-bit bus interface • 26 interrupt sources  For channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently ...
Page 329 Table 10-1 TPU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Count clock ø/1 ø/1 ø/1 ø/1 ø/1 ø/1 ø/4 ø/4 ø/4 ø/4 ø/4 ø/4 ø/16 ø/16 ø/16 ø/16 ø/16 ø/16 ø/64 ø/64 ø/64 ø/64 ø/64 ø/64...
Page 330 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 activation compare compare compare compare compare compare match or match or match or match or match or match or input capture input capture input capture input capture input capture input capture TGR0A...
Page 331: Block Diagram
10.1.2 Block Diagram Figure 10-1 shows a block diagram of the TPU. Interrupt request signals Channel 3: TGI3A Input/output pins TGI3B Channel 3: TIOCA3 TGI3C TIOCB3 TGI3D TIOCC3 TCI3V TIOCD3 Channel 4: TGI4A Channel 4: TIOCA4 TGI4B TIOCB4 TCI4V Channel 5: TIOCA5 TCI4U TIOCB5...
Page 332: Pin Configuration
10.1.3 Pin Configuration Table 10-2 summarizes the TPU pins. Table 10-2 TPU Pins Channel Name Symbol Function Clock input A TCLKA Input External clock A input pin (Channel 1 and 5 phase counting mode A phase input) Clock input B TCLKB Input External clock B input pin...
Page 333 Channel Name Symbol Function Input capture/out TIOCA3 TGR3A input capture input/output compare compare match A3 output/PWM output pin Input capture/out TIOCB3 TGR3B input capture input/output compare compare match B3 output/PWM output pin Input capture/out TIOCC3 TGR3C input capture input/output compare compare match C3 output/PWM output pin Input capture/out...
Page 334: Register Configuration
10.1.4 Register Configuration Table 10-3 summarizes the TPU registers. Table 10-3 TPU Registers Channel Name Abbreviation Initial Value Address Timer control register 0 TCR0 H'00 H'FF10 Timer mode register 0 TMDR0 H'C0 H'FF11 Timer I/O control register 0H TIOR0H H'00 H'FF12 Timer I/O control register 0L TIOR0L...
Page 335 Channel Name Abbreviation Initial Value Address Timer control register 3 TCR3 H'00 H'FE80 Timer mode register 3 TMDR3 H'C0 H'FE81 Timer I/O control register 3H TIOR3H H'00 H'FE82 Timer I/O control register 3L TIOR3L H'00 H'FE83 Timer interrupt enable register 3 TIER3 H'40 H'FE84 Timer status register 3...
Page 336: Register Descriptions
10.2 Register Descriptions 10.2.1 Timer Control Register (TCR) Channel 0: TCR0 Channel 3: TCR3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value : Channel 1: TCR1 Channel 2: TCR2 Channel 4: TCR4 Channel 5: TCR5 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2...
Page 337 Bits 7 to 5—Counter Clear 2 to 0 (CCLR2 to CCLR0): These bits select the TCNT counter clearing source. Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description 0, 3 TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture...
Page 338 Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. ø/4 both edges = ø/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority.
Page 339 Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on ø/1 (Initial value) Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input...
Page 340 Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on ø/1 (Initial value) Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input Internal clock: counts on ø/1024 Internal clock: counts on ø/256 Internal clock: counts on ø/4096...
Page 341: Timer Mode Register (Tmdr)
10.2.2 Timer Mode Register (TMDR) Channel 0: TMDR0 Channel 3: TMDR3 — — Initial value : — — Channel 1: TMDR1 Channel 2: TMDR2 Channel 4: TMDR4 Channel 5: TMDR5 — — — — Initial value : — — — —...
Page 342 Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved.
Page 343: Timer I/O Control Register (Tior)
10.2.3 Timer I/O Control Register (TIOR) Channel 0: TIOR0H Channel 1: TIOR1 Channel 2: TIOR2 Channel 3: TIOR3H Channel 4: TIOR4 Channel 5: TIOR5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : Channel 0: TIOR0L Channel 3: TIOR3L IOD3 IOD2 IOD1...
Page 344 Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD. Bit 7 Bit 6 Bit 5 Bit 4...
Page 345 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOD3 IOD2 IOD1 IOD0 Description TGR0D is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output register 1 output at compare match Toggle output at compare match Output disabled Initial output is 1...
Page 346 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR1B is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 347 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR3B is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 348 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOD3 IOD2 IOD1 IOD0 Description TGR3D is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output register 1 output at compare match Toggle output at compare match Output disabled Initial output is 1...
Page 349 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR4B is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 350 Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC. Bit 3 Bit 2 Bit 1 Bit 0 Channel...
Page 351 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOC3 IOC2 IOC1 IOC0 Description TGR0C is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output register 1 output at compare match Toggle output at compare match Output disabled Initial output is 1...
Page 352 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR1A is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 353 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR3A is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 354 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOC3 IOC2 IOC1 IOC0 Description TGR3C is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output register 1 output at compare match Toggle output at compare match Output disabled Initial output is 1...
Page 355 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR4A is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 356: Timer Interrupt Enable Register (Tier)
10.2.4 Timer Interrupt Enable Register (TIER) Channel 0: TIER0 Channel 3: TIER3 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value : — — Channel 1: TIER1 Channel 2: TIER2 Channel 4: TIER4 Channel 5: TIER5 TTGE — TCIEU TCIEV —...
Page 357 Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. Bit 7 TTGE Description A/D conversion start request generation disabled (Initial value) A/D conversion start request generation enabled Bit 6—Reserved: It is always read as 1 and cannot be modified. Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5.
Page 358 Bit 2—TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2 TGIEC Description...
Page 359: Timer Status Register (Tsr)
10.2.5 Timer Status Register (TSR) Channel 0: TSR0 Channel 3: TSR3 — — — TCFV TGFD TGFC TGFB TGFA Initial value : — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Can only be written with 0 for flag clearing. Channel 1: TSR1 Channel 2: TSR2 Channel 4: TSR4...
Page 360 Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. Bit 7 TCFD Description...
Page 361 Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGFD Description...
Page 362 Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match. Bit 1 TGFB Description [Clearing conditions] (Initial value) • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 •...
Page 363: Timer Counter (Tcnt)
10.2.6 Timer Counter (TCNT) Channel 0: TCNT0 (up-counter) Channel 1: TCNT1 (up/down-counter*) Channel 2: TCNT2 (up/down-counter*) Channel 3: TCNT3 (up-counter) Channel 4: TCNT4 (up/down-counter*) Channel 5: TCNT5 (up/down-counter*) Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel.
Page 364: Timer General Register (Tgr)
10.2.7 Timer General Register (TGR) Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The TGR registers are 16-bit registers with a dual function as output compare and input capture registers.
Page 365: Timer Start Register (Tstr)
10.2.8 Timer Start Register (TSTR) — — CST5 CST4 CST3 CST2 CST1 CST0 Initial value : — — TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.
Page 366: Timer Synchro Register (Tsyr)
10.2.9 Timer Synchro Register (TSYR) — — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value : — — TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Page 367: Module Stop Control Register A (Mstpcra)
10.2.10 Module Stop Control Register A (MSTPCRA) MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : MSTPCRA is an 8-bit readable/writable register that performs module stop mode control. When the MSTPA5 bit in MSTPCRA is set to 1, TPU operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 368: Interface To Bus Master
10.3 Interface to Bus Master 10.3.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 10-2.
Page 369 Examples of 8-bit register access operation are shown in figures 10-3, 10-4, and 10-5. Internal data bus Module Bus interface master data bus Figure 10-3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)] Internal data bus Module master Bus interface data bus...
Page 370: Operation
10.4 Operation 10.4.1 Overview Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Synchronous Operation: When synchronous operation is designated for a channel, TCNT for that channel performs synchronous presetting.
Page 371: Basic Functions
10.4.2 Basic Functions Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. • Example of count operation setting procedure Figure 10-6 shows an example of the count operation setting procedure.
Page 372 • Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up- count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1.
Page 373 Figure 10-8 illustrates periodic counter operation. Counter cleared by TGR TCNT value compare match H'0000 Time CST bit Flag cleared by software or DTC activation Figure 10-8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match.
Page 374 • Examples of waveform output operation Figure 10-10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
Page 375 Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel’s counter input clock or compare match signal as the input capture source.
Page 376 • Example of input capture operation Figure 10-13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Page 377: Synchronous Operation
10.4.3 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation.
Page 378 Example of Synchronous Operation: Figure 10-15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Page 379: Buffer Operation
10.4.4 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 10-5 shows the register combinations used in buffer operation.
Page 380 • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 10-17. Input capture signal Timer general...
Page 381 Examples of Buffer Operation • When TGR is an output compare register Figure 10-19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Page 382 • When TGR is an input capture register Figure 10-20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Page 383: Cascaded Operation
10.4.5 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Page 384 Examples of Cascaded Operation: Figure 10-22 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated as input capture registers, and TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.
Page 385: Pwm Modes
10.4.6 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register.
Page 386 Table 10-7 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGR0A TIOCA0 TIOCA0 TGR0B TIOCB0 TGR0C TIOCC0 TIOCC0 TGR0D TIOCD0 TGR1A TIOCA1 TIOCA1 TGR1B TIOCB1 TGR2A TIOCA2 TIOCA2 TGR2B TIOCB2 TGR3A TIOCA3 TIOCA3 TGR3B TIOCB3...
Page 387 Example of PWM Mode Setting Procedure: Figure 10-24 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to PWM mode TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
Page 388 TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 10-25 Example of PWM Mode Operation (1) Figure 10-26 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM waveform.
Page 389 Figure 10-27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten...
Page 390: Phase Counting Mode
10.4.7 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Page 391 Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. • Phase counting mode 1 Figure 10-29 shows an example of phase counting mode 1 operation, and table 10-9 summarizes the TCNT up/down-count conditions.
Page 392 • Phase counting mode 2 Figure 10-30 shows an example of phase counting mode 2 operation, and table 10-10 summarizes the TCNT up/down-count conditions. TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCNT value Up-count Down-count...
Page 393 • Phase counting mode 3 Figure 10-31 shows an example of phase counting mode 3 operation, and table 10-11 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count...
Page 394 • Phase counting mode 4 Figure 10-32 shows an example of phase counting mode 4 operation, and table 10-12 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count...
Page 395 Phase Counting Mode Application Example: Figure 10-33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB.
Page 396 Channel 1 TCLKA Edge TCNT1 detection circuit TCLKB TGR1A (speed period capture) TGR1B (position period capture) TCNT0 TGR0A (speed control period) – TGR0C – (position control period) TGR0B (pulse width capture) TGR0D (buffer operation) Channel 0 Figure 10-33 Phase Counting Mode Application Example...
Page 397: Interrupts
10.5 Interrupts 10.5.1 Interrupt Sources and Priorities There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
Page 398 Table 10-13 TPU Interrupts Channel Interrupt Source Description DTC Activation Priority TGI0A TGR0A input capture/compare match Possible High TGI0B TGR0B input capture/compare match Possible TGI0C TGR0C input capture/compare match Possible TGI0D TGR0D input capture/compare match Possible TCI0V TCNT0 overflow Not possible TGI1A TGR1A input capture/compare match Possible TGI1B...
Page 399: Dtc Activation
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
Page 400: Operation Timing
10.6 Operation Timing 10.6.1 Input/Output Timing TCNT Count Timing: Figure 10-34 shows TCNT count timing in internal clock operation, and figure 10-35 shows TCNT count timing in external clock operation. ø Falling edge Rising edge Internal clock TCNT input clock TCNT N–1 Figure 10-34 Count Timing in Internal Clock Operation...
Page 401 Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin.
Page 402 Timing for Counter Clearing by Compare Match/Input Capture: Figure 10-38 shows the timing when counter clearing by compare match occurrence is specified, and figure 10-39 shows the timing when counter clearing by input capture occurrence is specified. ø Compare match signal Counter clear signal H'0000...
Page 403 Buffer Operation Timing: Figures 10-40 and 10-41 show the timing in buffer operation. ø TCNT Compare match signal TGRA, TGRB TGRC, TGRD Figure 10-40 Buffer Operation Timing (Compare Match) ø Input capture signal TCNT TGRA, TGRB TGRC, TGRD Figure 10-41 Buffer Operation Timing (Input Capture)
Page 404: Interrupt Signal Timing
10.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 10-42 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. ø TCNT input clock TCNT Compare match signal...
Page 405 TGF Flag Setting Timing in Case of Input Capture: Figure 10-43 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. ø Input capture signal TCNT TGF flag TGI interrupt Figure 10-43 TGI Interrupt Timing (Input Capture)
Page 406 TCFV Flag/TCFU Flag Setting Timing: Figure 10-44 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 10-45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing.
Page 407 Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10-46 shows the timing for status flag clearing by the CPU, and figure 10-47 shows the timing for status flag clearing by the DTC.
Page 408: Usage Notes
10.7 Usage Notes Note that the kinds of operation and contention described below occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width.
Page 409 Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10-49 shows the timing in this case. TCNT write cycle ø...
Page 410 Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10-50 shows the timing in this case. TCNT write cycle ø...
Page 411 Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 10-51 shows the timing in this case.
Page 412 Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 10-52 shows the timing in this case. TGR write cycle ø...
Page 413 Contention between TGR Read and Input Capture: If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 10-53 shows the timing in this case. TGR read cycle ø...
Page 414 Contention between TGR Write and Input Capture: If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10-54 shows the timing in this case. TGR write cycle ø...
Page 415 Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10-55 shows the timing in this case. Buffer register write cycle ø...
Page 416 Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10-56 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
Page 417 Figure 10-57 Contention between TCNT Write and Overflow Multiplexing of I/O Pins: In the H8S/2646 Series, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin.
Page 419: Section 11 Programmable Pulse Generator (Ppg)
11.1 Overview The H8S/2646 Series has a built-in programmable pulse generator (PPG) that provides pulse outputs by using the 16-bit timer-pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (group 3 and group 2) that can operate both simultaneously and independently.
Page 420: Block Diagram
11.1.2 Block Diagram Figure 11-1 shows a block diagram of the PPG. Compare match signals NDERH NDERL Control logic PO15 Pulse output PO14 PO13 pins, group 3 Internal PO12 PODRH NDRH PO11 data bus PO10 Pulse output pins, group 2 Pulse output pins, group 1 PODRL...
Page 421: Pin Configuration
11.1.3 Pin Configuration Table 11-1 summarizes the PPG pins. Table 11-1 PPG Pins Name Symbol Function Pulse output 8 Output Group 2 pulse output Pulse output 9 Output Pulse output 10 PO10 Output Pulse output 11 PO11 Output Pulse output 12 PO12 Output Group 3 pulse output...
Page 422: Registers
PCR setting, the NDRL address is H'FE2D. When the output triggers are different, the NDRL address is H'FE2F for group 0 and H'FE2D for group 1. *4 The H8S/2646 Series has no pins corresponding to pulse output groups 0 and 1.
Page 423: Register Descriptions
11.2 Register Descriptions 11.2.1 Next Data Enable Registers H and L (NDERH, NDERL) NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value : NDERL NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial value : NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a bit-by-bit basis.
Page 424: Output Data Registers H And L (Podrh, Podrl)
Note: * A bit that has been set for pulse output by NDER is read-only. PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse output. However, the H8S/2646 Series has no pins corresponding to PODRL.
Page 425: Next Data Registers H And L (Ndrh, Ndrl)
H'FE2D. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FE2F consists entirely of reserved bits that cannot be modified and are always read as 1. However, the H8S/2646 Series has no output pins corresponding to pulse output groups 0 and 1.
Page 426 H'FE2F. Bits 3 to 0 of address H'FE2D and bits 7 to 4 of address H'FE2F are reserved bits that cannot be modified and are always read as 1. However, the H8S/2646 Series has no output pins corresponding to pulse output groups 0 and 1.
Page 427: Ppg Output Control Register (Pcr)
Address H'FE2D NDR7 NDR6 NDR5 NDR4 — — — — Initial value : — — — — Address H'FE2F — — — — NDR3 NDR2 NDR1 NDR0 Initial value : — — — — 11.2.5 PPG Output Control Register (PCR) G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : PCR is an 8-bit readable/writable register that selects output trigger signals for PPG outputs on a...
Page 428 Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match that triggers pulse output group 1 (pins PO7 to PO4). However, the H8S/2646 Series has no output pins corresponding to pulse output group 1. Description...
Page 429: Ppg Output Mode Register (Pmr)
11.2.6 PPG Output Mode Register (PMR) G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV Initial value : PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping operation for each group. The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB and the non-overlap margin is set in TGRA.
Page 430 Bit 5—Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output group 1 (pins PO7 to PO4). However, the H8S/2646 Series has no pins corresponding to pulse output group 1. Bit 5 G1INV Description Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL)
Page 431 Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse output group 1 (pins PO7 to PO4). However, the H8S/2646 Series has no pins corresponding to pulse output group 1. Bit 1 G1NOV Description Normal operation in pulse output group 1 (output values updated at compare match A...
Page 432: Port 1 Data Direction Register (P1Ddr)
11.2.7 Port 1 Data Direction Register (P1DDR) P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. Port 1 is multiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG output must be set to 1.
Page 433: Operation
11.3 Operation 11.3.1 Overview PPG pulse output is enabled when the corresponding bits in P1DDR and NDER are set to 1. In this state the corresponding PODR contents are output. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values.
Page 434: Output Timing
11.3.2 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 11-3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. ø...
Page 435: Normal Pulse Output
11.3.3 Normal Pulse Output Sample Setup Procedure for Normal Pulse Output: Figure 11-4 shows a sample procedure for setting up normal pulse output. [1] Set TIOR to make TGRA an output Normal PPG output compare register (with output disabled) Select TGR functions [2] Set the PPG output trigger period Set TGRA value [3] Select the counter clock source...
Page 436 Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 11-5 shows an example in which pulse output is used for cyclic five-phase pulse output. Compare match TCNT value TCNT TGRA H'0000 Time NDRH PODRH PO15 PO14 PO13 PO12 PO11 Figure 11-5 Normal Pulse Output Example (Five-Phase Pulse Output) [1] Set up the TPU channel to be used as the output trigger channel so that TGRA is an output...
Page 437: Non-Overlapping Pulse Output
11.3.4 Non-Overlapping Pulse Output Sample Setup Procedure for Non-Overlapping Pulse Output: Figure 11-6 shows a sample procedure for setting up non-overlapping pulse output. [1] Set TIOR to make TGRA and Non-overlapping PPG output TGRB an output compare registers (with output disabled) Select TGR functions [2] Set the pulse output trigger period in TGRB and the non-overlap...
Page 438 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non- Overlapping Output): Figure 11-7 shows an example in which pulse output is used for four- phase complementary non-overlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 Time NDRH PODRH Non-overlap margin PO15 PO14 PO13...
Page 439 [1] Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt.
Page 440: Inverted Pulse Output
11.3.5 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 11-8 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 11-7.
Page 441: Pulse Output Triggered By Input Capture
11.3.6 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal.
Page 442: Usage Notes
11.4 Usage Notes Operation of Pulse Output Pins: Pins PO8 to PO15 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins.
Page 443 Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC.
Page 445: Section 12 Watchdog Timer
The H8S/2646 Series has an on-chip watchdog timer with two channels (WDT0, WDT1). The WDT can also generate an internal reset signal for the H8S/2646 Series if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow.
Page 446: Block Diagram
12.1.2 Block Diagram Figures 12-1 (a) and 12-1 (b) show a block diagram of the WDT. Overflow ø/2 Interrupt ø/64 WOVI0 control ø/128 (interrupt request ø/512 signal) Clock Clock select ø/2048 ø/8192 ø/32768 Reset ø/131072 Internal reset signal * control Internal clock sources RSTCSR...
Page 447 ø/2 øSUB/2 ø/64 WOVI1 øSUB/4 ø/128 Interrupt (Interrupt request signal) øSUB/8 ø/512 control Clock Overflow øSUB/16 Clock Internal NMI select ø/2048 øSUB/32 Interrupt request signal ø/8192 Reset øSUB/64 ø/32768 control øSUB/128 ø/131072 Internal reset signal* øSUB/256 Internal clock TCNT TCSR interface Module bus Legend:...
Page 448: Pin Configuration
12.1.3 Pin Configuration There are no pins related to the WDT. 12.1.4 Register Configuration The WDT has five registers, as summarized in table 12-1. These registers control clock selection, WDT mode switching, and the reset signal. Table 12-1 WDT Registers Address Channel Name Abbreviation R/W...
Page 449: Register Descriptions
12.2 Register Descriptions 12.2.1 Timer Counter (TCNT) Initial value : TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), an internal reset, a NMI interrupt (only WDT1), or an interval timer interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR.
Page 450 TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCSR0 (TCSR1) is initialized to H'18 (H'00) by a reset and in hardware standby mode. It is not initialized in software standby mode.
Page 451 WDT0 Mode Select TCSR0 WT/IT Description Interval timer mode: WDT0 requests an interval timer interrupt (WOVI) from the CPU when the TCNT overflows. (Initial value) Watchdog timer mode: A reset is issued when the TCNT overflows if the RSTE bit of RSTCSR is set to 1.* Note: * For details see section 12.2.3, Reset Control/Status Register (RSTCSR).
Page 452 WDT0 TCSR Bit 3—Reserved Bit: It is always read as 1 and cannot be modified. WDT1 TCSR Bit 3—Reset or NMI (RST/NMI): This bit is used to choose between an internal reset request and an NMI request when the TCNT overflows during the watchdog timer mode. Bit 3 RTS/NMI Description...
Page 453 WDT1 Input Clock Select Description Bit 4 Bit 2 Bit 1 Bit 0 Overflow Period* (where ø = 20 MHz) CKS2 CKS1 CKS0 Clock (where ø SUB = 32.768 kHz) ø/2 (initial value) 25.6 µs ø/64 819.2 µs ø/128 1.6 ms ø/512 6.6 ms ø/2048...
Page 454: Reset Control/Status Register (Rstcsr)
(Initial value) Reset signal is generated if TCNT overflows Note: * The modules within the H8S/2646 Series are not reset, but TCNT and TCSR within the WDT are reset. Bit 5—Reserved: Always read as 0. Can only be written with 0.
Page 455: Notes On Register Access
12.2.4 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction. They cannot be written to with byte instructions.
Page 456 Writing to RSTCSR: RSTCSR must be written to by word transfer instruction to address H'FF76. It cannot be written to with byte instructions. Figure 12-3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF bit differs from that for writing to the RSTE bits.
Page 457: Operation
12.3 Operation 12.3.1 Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before overflow occurs.
Page 458 TCNT value Overflow H'FF Time H'00 WT/IT= 1 WOVF= 1* Write H'00' WT/IT= 1 Write H'00' TME= 1 to TCNT TME= 1 to TCNT internal reset is generated Internal reset signal 515/516 states Legend : Timer mode select bit WT/IT : Timer enable bit Note: * The WOVF bit is set to 1 and then cleared to 0 by an internal reset.
Page 459: Interval Timer Operation
12.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 12-5.
Page 460: Timing Of Setting Of Watchdog Timer Overflow Flag (Wovf)
In the WDT0, the WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire H8S/2646 Series chip. Figure 12-7 shows the timing in this case. ø...
Page 461: Interrupts
12.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. If an NMI request has been chosen in the watchdog timer mode, an NMI request is generated when a TCNT overflow occurs.
Page 462: Changing Value Of Pss And Cks2 To Cks0
Internal Reset in Watchdog Timer Mode In watchdog timer mode, the H8S/2646 Series will not be reset internally if TCNT overflows while the RSTE bit is cleared to 0. When this module is used as a watchdog timer, the RSTE bit must be set to 1 beforehand.
Page 463: Section 13 Serial Communication Interface (Sci)
Section 13 Serial Communication Interface (SCI) 13.1 Overview The H8S/2646 Series is equipped with 2 or 3 independent serial communication interface (SCI) channels*. The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function).
Page 464  Receive error detection : Overrun errors detected • Full-duplex communication capability  The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously  Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data •...
Page 465: Block Diagram
13.1.2 Block Diagram Figure 13-1 shows a block diagram of the SCI. Internal Module data bus data bus SCMR ø ø/4 Baud rate generator ø/16 Transmission/ ø/64 reception control Parity generation Clock Parity check External clock Legend : Receive shift register : Receive data register : Transmit shift register : Transmit data register...
Page 466: Pin Configuration
13.1.3 Pin Configuration Table 13-1 shows the serial pins for each SCI channel. Table 13-1 SCI Pins Channel Pin Name Symbol Function Serial clock pin 0 SCK0 SCI0 clock input/output Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output...
Page 467: Register Configuration
13.1.4 Register Configuration The SCI has the internal registers shown in table 13-2. These registers are used to specify asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control transmitter/receiver. Table 13-2 SCI Registers Channel Name Abbreviation...
Page 468: Register Descriptions
13.2 Register Descriptions 13.2.1 Receive Shift Register (RSR) — — — — — — — — RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data.
Page 469: Transmit Shift Register (Tsr)
13.2.3 Transmit Shift Register (TSR) — — — — — — — — TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically.
Page 470: Serial Mode Register (Smr)
13.2.5 Serial Mode Register (SMR) STOP CKS1 CKS0 Initial value SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset and in hardware standby mode.
Page 471 Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In clocked synchronous mode with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting.
Page 472 Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP Description...
Page 473: Serial Control Register (Scr)
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from ø, ø/4, ø/16, and ø/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 13.2.8, Bit Rate Register (BRR).
Page 474 Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI) request and receive error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 Description Receive data full interrupt (RXI) request and receive error interrupt (ERI) request...
Page 475 Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE Description...
Page 476 Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin.
Page 477: Serial Status Register (Ssr)
13.2.7 Serial Status Register (SSR) TDRE RDRF ORER TEND MPBT Initial value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits.
Page 478 Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR. Bit 6 RDRF Description [Clearing conditions] (Initial value) • When 0 is written to RDRF after reading RDRF = 1 • When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Note: RDR and the RDRF flag are not affected and retain their previous values when an error is...
Page 479 Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 Description [Clearing condition] (Initial value) When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 Notes: *1 The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
Page 480 Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2 TEND Description [Clearing conditions] •...
Page 481: Bit Rate Register (Brr)
13.2.8 Bit Rate Register (BRR) Initial value BRR is an 8-bit register that sets the serial transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset and in standby mode.
Page 482 ø = 6.144 MHz ø = 7.3728 MHz ø = 8 MHz ø = 9.8304 MHz Bit Rate Error Error Error Error (bit/s) 0.08 –0.07 2 0.03 –0.26 0.00 0.00 0.16 0.00 0.00 0.00 0.16 0.00 0.00 0.00 0.16 0.00 1200 0.00 0.00...
Page 483 ø = 14.7456 MHz ø = 16 MHz ø = 17.2032 MHz ø = 18 MHz Bit Rate Error Error Error Error (bit/s) 0.70 0.03 0.48 –0.12 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 1200 0.00 0.16 0.00...
Page 484 Table 13-4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ø = 4 MHz ø = 8 MHz ø = 10 MHz ø = 16 MHz ø = 20 MHz Bit Rate (bit/s) — — — — — — —...
Page 485 The BRR setting is found from the following formulas. Asynchronous mode: ø × 10 – 1 64 × 2 × B 2n–1 Clocked synchronous mode: ø × 10 – 1 8 × 2 × B 2n–1 Where B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 ≤...
Page 486 Table 13-5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 13-6 and 13-7 show the maximum bit rates with external clock input. Table 13-5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ø (MHz) Maximum Bit Rate (bit/s) 125000 4.9152 153600...
Page 487 Table 13-6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 1.0000 62500 4.9152 1.2288 76800 1.2500 78125 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 2.0000 125000 9.8304 2.4576 153600 2.5000 156250...
Page 488: Smart Card Mode Register (Scmr)
13.2.9 Smart Card Mode Register (SCMR) — — — — SDIR SINV — SMIF Initial value — — — — — SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous mode 7-bit data, LSB-first or MSB-first can be selected regardless of the serial communication mode.
Page 489: Module Stop Control Register B (Mstpcrb)
Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/E bit in SMR. Bit 2 SINV Description TDR contents are transmitted without modification (Initial value)
Page 490 Bit 7—Module Stop (MSTPB7): Specifies the SCI0 module stop mode. Bit 7 MSTPB7 Description SCI0 module stop mode is cleared SCI0 module stop mode is set (Initial value) Bit 6—Module Stop (MSTPB6): Specifies the SCI1 module stop mode. Bit 6 MSTPB6 Description SCI1 module stop mode is cleared...
Page 491: Operation
13.3 Operation 13.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or clocked synchronous mode and the transmission format is made using SMR as shown in table 13-8.
Page 492 Table 13-8 SMR Settings and Serial Transfer Format Selection SMR Settings SCI Transfer Format Multi Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data Parity Stop Bit Processor STOP Mode Length Length Asynchronous 8-bit data 1 bit mode 2 bits 1 bit 2 bits...
Page 493: Operation In Asynchronous Mode
13.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication.
Page 494 Data Transfer Format: Table 13-10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. Table 13-10 Serial Transfer Formats (Asynchronous Mode) SMR Settings Serial Transfer Format and Frame Length STOP 8-bit data STOP...
Page 495 Clock: Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 13-9.
Page 496 Figure 13-4 shows a sample SCI initialization flowchart. [1] Set the clock selection in SCR. Start initialization Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Clear TE and RE bits in SCR to 0 When the clock is selected in asynchronous mode, it is output Set CKE1 and CKE0 bits in SCR...
Page 497 • Serial data transmission (asynchronous mode) Figure 13-5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start transmission output pin.
Page 498 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Page 499 Figure 13-6 shows an example of the operation for transmission in asynchronous mode. Start Data Parity Stop Start Data Parity Stop Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt TEI interrupt request generated TDRE flag cleared to 0 in request generated request generated...
Page 500 • Serial data reception (asynchronous mode) Figure 13-7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start reception input pin.
Page 501 Error processing ORER= 1 Overrun error processing FER= 1 Break? Framing error processing Clear RE bit in SCR to 0 PER= 1 Parity error processing Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 13-7 Sample Serial Reception Data Flowchart (cont)
Page 502 In serial reception, the SCI operates as described below. [1] The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received.
Page 503 Table 13-11 Receive Errors and Conditions for Occurrence Receive Error Abbreviation Occurrence Condition Data Transfer Overrun error ORER When the next data reception is Receive data is not completed while the RDRF flag transferred from RSR to in SSR is set to 1 RDR.
Page 504: Multiprocessor Communication Function
13.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines.
Page 505 Transmitting station Serial transmission line Receiving Receiving Receiving Receiving station A station B station C station D (ID= 01) (ID= 02) (ID= 03) (ID= 04) Serial H'01 H'AA data (MPB= 1) (MPB= 0) ID transmission cycle= Data transmission cycle= receiving station Data transmission to specification receiving station specified by ID...
Page 506 SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start transmission output pin. After the TE bit is set to 1, a frame of 1s is output, and Read TDRE flag in SSR transmission is enabled. SCI status check and transmit TDRE= 1 data write:...
Page 507 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Page 508 Figure 13-11 shows an example of SCI operation for transmission using the multiprocessor format. Multi- Multi- proce- Start Data Stop Start Data Stop ssor proces- sor bit Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR TXI interrupt TEI interrupt request generated and TDRE flag cleared to...
Page 509 SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start reception input pin. ID reception cycle: Set MPIE bit in SCR to 1 Set the MPIE bit in SCR to 1. Read ORER and FER flags in SSR SCI status check, ID reception and comparison: Read SSR and check that the...
Page 510 Error processing ORER= 1 Overrun error processing FER= 1 Break? Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 13-12 Sample Multiprocessor Serial Reception Flowchart (cont)
Page 511 Figure 13-13 shows an example of SCI operation for multiprocessor format reception. Start Data (ID1) Stop Start Data (Data1) Stop Idle state (mark state) MPIE RDRF value MPIE = 0 RXI interrupt RDR data read If not this station’s ID, RXI interrupt request is request and RDRF flag...
Page 512: Operation In Clocked Synchronous Mode
13.3.4 Operation in Clocked Synchronous Mode In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer.
Page 513 Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. If you want to perform receive operations in units of one character, you should select an external clock as the clock source.
Page 514 • Serial data transmission (clocked synchronous mode) Figure 13-16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data output Start transmission pin.
Page 515 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Page 516 • Serial data reception (clocked synchronous mode) Figure 13-18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to clocked synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible.
Page 517 SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start reception input pin. [2] [3] Receive error processing: Read ORER flag in SSR If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error processing, clear the ORER flag ORER= 1...
Page 518 In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR.
Page 519 SCI initialization: Initialization The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the Start transmission/reception receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR SCI status check and transmit data write: Read SSR and check that the TDRE= 1...
Page 520: Sci Interrupts
13.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 13-12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of interrupt request is sent to the interrupt controller independently.
Page 521: Usage Notes
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt may have priority for acceptance, with the result that the TDRE and TEND flags are cleared.
Page 522 Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set.
Page 523 16 clocks 8 clocks 15 0 15 0 Internal basic clock Receive data Start bit (RxD) Synchronization sampling timing Data sampling timing Figure 13-21 Receive Data Sampling Timing in Asynchronous Mode Thus the reception margin in asynchronous mode is given by formula (1) below. | D –...
Page 524 Restrictions on Use of DTC • When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 ø clock cycles after TDR is updated by the DTC. Misoperation may occur if the transmit clock is input within 4 ø...
Page 525 • Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. RSR, RDR, and SSR are reset. If a transition is made without stopping operation, the data being received will be invalid.
Page 526 Transition Exit from End of to software software standby standby Start of transmission transmission TE bit Port input/output SCK output pin TxD output pin Port input/output High output Start Stop Port input/output High output SCI TxD Port Port SCI TxD output output Figure 13-24 Asynchronous Transmission Using Internal Clock Transition...
Page 527 <Reception> Read RDRF flag in SSR [1] Receive data being received RDRF = 1 becomes invalid. Read receive data in RDR RE = 0 Transition to software [2] Includes module stop mode. standby mode, etc. Exit from software standby mode, etc. Change operating mode? Initialization...
Page 528 Switching from SCK Pin Function to Port Pin Function: • Problem in Operation: When switching the SCK pin function to the output port function (high- level output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle.
Page 529 • Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown.
Page 531: Section 14 Smart Card Interface
Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 14.1.1 Features Features of the Smart Card interface supported by the H8S/2646 Series are as follows. • Asynchronous mode  Data length: 8 bits  Parity bit generation and checking ...
Page 532: Block Diagram
14.1.2 Block Diagram Figure 14-1 shows a block diagram of the Smart Card interface. Internal Module data bus data bus SCMR ø ø/4 Baud rate generator ø/16 Transmission/ ø/64 reception control Parity generation Clock Parity check Legend : Smart Card mode register SCMR : Receive shift register : Receive data register...
Page 533: Pin Configuration
14.1.3 Pin Configuration Table 14-1 shows the Smart Card interface pin configuration. Table 14-1 Smart Card Interface Pins Channel Pin Name Symbol Function Serial clock pin 0 SCK0 SCI0 clock input/output Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output...
Page 534: Register Configuration
14.1.4 Register Configuration Table 14-2 shows the registers used by the Smart Card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 13, Serial Communication Interface (SCI). Table 14-2 Smart Card Interface Registers Channel Name...
Page 535: Register Descriptions
14.2 Register Descriptions Registers added with the Smart Card interface and bits for which the function changes are described here. 14.2.1 Smart Card Mode Register (SCMR) — — — — SDIR SINV — SMIF Initial value : — — — —...
Page 536 Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 14.3.4, Register Settings.
Page 537: Serial Status Register (Ssr)
14.2.2 Serial Status Register (SSR) TDRE RDRF ORER TEND MPBT Initial value : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear these flags. Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different.
Page 538 Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below. Bit 2 TEND Description Transmission is in progress [Clearing conditions] (Initial value) •...
Page 539: Serial Mode Register (Smr)
14.2.3 Serial Mode Register (SMR) BCP1 BCP0 CKS1 CKS0 Initial value : Note: When the smart card interface is used, be sure to make the 1 setting shown for bit 5. The function of bits 7, 6, 3, and 2 of SMR changes in Smart Card interface mode. Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode.
Page 540 Bit 6—Block Transfer Mode (BLK): Selects block transfer mode. Bit 6 Description Normal Smart Card interface mode operation • Error signal transmission/detection and automatic data retransmission performed • TXI interrupt generated by TEND flag • TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode) Block transfer mode operation •...
Page 541: Serial Control Register (Scr)
14.2.4 Serial Control Register (SCR) MPIE TEIE CKE1 CKE0 Initial value : In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2—Operate in the same way as for the normal SCI.
Page 542: Operation
14.3 Operation 14.3.1 Overview The main functions of the Smart Card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame.
Page 543 Data line Clock line Rx (port) Reset line H8S/2646 Series IC card Connected equipment Figure 14-2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed...
Page 544: Data Format
14.3.3 Data Format Normal Transfer Mode: Figure 14-3 shows the normal Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted.
Page 545 If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor.
Page 546: Register Settings
14.3.4 Register Settings Table 14-3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 14-3 Smart Card Interface Register Settings Register Bit 7 Bit 6...
Page 547 The parity bit is 0, corresponding to state Z, since even parity is stipulated for the Smart Card. With the H8S/2646 Series, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR is set to odd parity mode (the same applies...
Page 548: Clock
14.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1, CKS0, BCP1 and BCP0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 14-5 shows some sample bit rates.
Page 549 The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the smaller error is specified.
Page 550: Data Transfer Operations
14.3.6 Data Transfer Operations Initialization: Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0.
Page 551 Serial Data Transmission: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 14-4 shows a flowchart for transmitting, and figure 14-5 shows the relation between a transmit operation and the internal registers.
Page 552 Start Initialization Start transmission ERS=0? Error processing TEND=1? Write data to TDR, and clear TDRE flag in SSR to 0 All data transmitted? ERS=0? Error processing TEND=1? Clear TE bit to 0 Figure 14-4 Example of Transmission Processing Flow...
Page 553 (shift register) (1) Data write Data 1 (2) Transfer from Data 1 Data 1 ; Data remains in TDR TDR to TSR Data 1 I/O signal line output (3) Serial data output Data 1 In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set...
Page 554 Serial Data Reception (Except Block Transfer Mode): Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 14-7 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0.
Page 555 With the above processing, interrupt servicing or data transfer by the DTC is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI) request will be generated.
Page 556 requests, and receive data full interrupt (RXI) requests. The transmit end interrupt (TEI) request is not used in this mode. When the TEND flag in SSR is set to 1, a TXI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated.
Page 557: Operation In Gsm Mode
flag is set but the RDRF flag is not. Consequently, the DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. Note: For block transfer mode, see section 13.4, SCI Interrupts. 14.3.7 Operation in GSM Mode Switching the Mode: When switching between smart card interface mode and software standby...
Page 558: Operation In Block Transfer Mode
Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to smart card mode operation.
Page 559: Usage Notes
14.4 Usage Notes The following points should be noted when using the SCI as a Smart Card interface. Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode: In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (as determined by bits BCP1 and BCP0).
Page 560 Thus the reception margin in asynchronous mode is given by the following formula. Formula for reception margin in smart card interface mode  D – 0.5 (1 + F) × 100% M = (0.5 – ) – (L – 0.5) F – Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, and 256) D: Clock duty (D = 0 to 1.0)
Page 561 Transfer nth transfer frame Retransferred frame frame n+1 (DE) D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 RDRF Figure 14-11 Retransfer Operation in SCI Receive Mode •...
Page 563: Section 15 Hitachi Controller Area Network (Hcan)
Overview The HCAN is a module for controlling a controller area network (CAN) for realtime communication in vehicular and industrial equipment systems, etc. The H8S/2646 Series has a single-channel on-chip HCAN module. Reference: BOSCH CAN Specification Version 2.0 1991, Robert Bosch GmbH 15.1.1...
Page 564: Block Diagram
 HCAN configuration mode  HCAN sleep mode  HCAN halt mode • Other features: DTC can be activated by message reception mailbox (HCAN mailbox 0 only) 15.1.2 Block Diagram Figure 15-1 shows a block diagram of the HCAN. HCAN (CDLC) Message buffer Mailboxes...
Page 565: Pin Configuration
15.1.3 Pin Configuration Table 15-1 shows the HCAN’s pins. When using HCAN pins, settings must be made in the HCAN configuration mode (during initialization: MCR0 = 1 and GSR3 = 1). Table 15-1 HCAN Pins Name Abbreviation Input/Output Function HCAN transmit data pin HTxD Output CAN bus transmission pin...
Page 566 Name Abbreviation R/W Initial Value Address* Access Size Local acceptance filter mask L LAFML H'0000 H'F81C 8/16 bits Local acceptance filter mask H LAFMH H'0000 H'F81E 8/16 bits Message control 0 [1:8] MC0 [1:8] Undefined H'F820 8/16 bits Message control 1 [1:8] MC1 [1:8] Undefined H'F828...
Page 567: Register Descriptions
15.2 Register Descriptions 15.2.1 Master Control Register (MCR) The master control register (MCR) is an 8-bit readable/writable register that controls the CAN interface. Bit: MCR7 — MCR5 — — MCR2 MCR1 MCR0 Initial value: R/W: Bit 7—HCAN Sleep Mode Release (MCR7): Enables or disables HCAN sleep mode release by bus operation.
Page 568: General Status Register (Gsr)
Bit 1—Halt Request (MCR1): Controls halting of the HCAN module. Bit 1: MCR1 Description HCAN normal operating mode (Initial value) HCAN halt mode transition request Bit 0—Reset Request (MCR0): Controls resetting of the HCAN module. Bit 0: MCR0 Description Normal operating mode (MCR0 = 0 and GSR3 = 0) [Setting condition] When 0 is written after an HCAN reset HCAN reset mode transition request...
Page 569 Bit 3—Reset Status Bit (GSR3): Indicates whether the HCAN module is in the normal operating state or the reset state. This bit cannot be written to. Bit 3: GSR3 Description Normal operating state [Setting condition] After an HCAN internal reset Configuration mode [Reset condition] MCR0 reset mode and sleep mode...
Page 570: Bit Configuration Register (Bcr)
15.2.3 Bit Configuration Register (BCR) The bit configuration register (BCR) is a 16-bit readable/writable register that is used to set CAN bit timing parameters and the baud rate prescaler. Bit: BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0 Initial value: R/W: Bit: BCR15...
Page 571 Bit 7—Bit Sample Point (BSP): Sets the point at which data is sampled. Bit 7: BCR15 Description Bit sampling at one point (end of time segment 1 (TSEG1)) (Initial value) Bit sampling at three points (end of TSEG1 and preceding and following time quantum) Bits 6 to 4—Time Segment 2 (TSEG2): These bits are used to set the segment for correcting 1- bit time error.
Page 572: Mailbox Configuration Register (Mbcr)
15.2.4 Mailbox Configuration Register (MBCR) The mailbox configuration register (MBCR) is a 16-bit readable/writable register that is used to set mailbox (buffer) transmission/reception. MBCR Bit: — MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 Initial value: R/W: — Bit: MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8 Initial value:...
Page 573: Transmit Wait Register (Txpr)
15.2.5 Transmit Wait Register (TXPR) The transmit wait register (TXPR) is a 16-bit readable/writable register that is used to set a transmit wait after a transmit message is stored in a mailbox (buffer) (CAN bus arbitration wait). TXPR Bit: TXPR7 TXPR6 TXPR5 TXPR4...
Page 574: Transmit Wait Cancel Register (Txcr)
15.2.6 Transmit Wait Cancel Register (TXCR) The transmit wait cancel register (TXCR) is a 16-bit readable/writable register that controls cancellation of transmit wait messages in mailboxes (buffers). TXCR Bit: TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 — Initial value: R/W: —...
Page 575: Transmit Acknowledge Register (Txack)
15.2.7 Transmit Acknowledge Register (TXACK) The transmit acknowledge register (TXACK) is a 16-bit readable/writable register containing status flags that indicate normal transmission of mailbox (buffer) transmit messages. TXACK Bit: — TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 Initial value: R/W: R/(W)* R/(W)* R/(W)*...
Page 576: Abort Acknowledge Register (Aback)
15.2.8 Abort Acknowledge Register (ABACK) The abort acknowledge register (ABACK) is a 16-bit readable/writable register containing status flags that indicate normal cancellation (aborting) of a mailbox (buffer) transmit messages. ABACK Bit: — ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 Initial value: R/W: R/(W)* R/(W)*...
Page 577: Receive Complete Register (Rxpr)
15.2.9 Receive Complete Register (RXPR) The receive complete register (RXPR) is a 16-bit readable/writable register containing status flags that indicate normal reception of messages (data frame or remote frame) in mailboxes (buffers). When receiving a remote frame, the corresponding remote-request register (REPR) is also set at the same time.
Page 578: Remote Request Register (Rfpr)
15.2.10 Remote Request Register (RFPR) The remote request register (RFPR) is a 16-bit readable/writable register containing status flags that indicate normal reception of remote frames in mailboxes (buffers). When this bit is set, the corresponding receive-completed bit is set the same time. RFPR Bit: RFPR7...
Page 579: Interrupt Register (Irr)
15.2.11 Interrupt Register (IRR) The interrupt register (IRR) is a 16-bit readable/writable register containing status flags for the various interrupt sources. Bit: IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 Initial value: R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Bit: —...
Page 580 Bit 13—Error Passive Interrupt Flag: Status flag indicating the error passive state caused by the transmit/receive error counter. Bit 13: IRR5 Description [Clearing condition] Writing 1 (Initial value) Error passive state caused by transmit/receive error [Setting condition] When TEC ≥ 128 or REC ≥ 128 Bit 12—Receive Overload Warning Interrupt Flag: Status flag indicating the error warning state caused by the receive error counter.
Page 581 Bit 9—Receive Message Interrupt Flag: Status flag indicating that a mailbox (buffer) receive message has been received normally. Bit 9: IRR1 Description [Clearing condition] Clearing of all bits in RXPR (receive complete register) of the mailbox, which enables the receive interrupt requests in the MBIMR (Initial value) Data frame or remote frame received and stored in mailbox [Setting conditions]...
Page 582 Bit 1—Unread Interrupt Flag: Status flag indicating that a receive message has been overwritten while still unread. Bit 1: IRR9 Description [Clearing condition] Clearing of all bits in UMSR (unread message status register) (Initial value) Unread message overwrite [Setting condition] When UMSR (unread message status register) is set Bit 0—Mailbox Empty Interrupt Flag: Status flag indicating that the next transmit message can be stored in the mailbox.
Page 583: Mailbox Interrupt Mask Register (Mbimr)
15.2.12 Mailbox Interrupt Mask Register (MBIMR) The mailbox interrupt mask register (MBIMR) is a 16-bit readable/writable register containing flags that enable or disable individual mailbox (buffer) interrupt requests. MBIMR Bit: MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 Initial value: R/W: Bit: MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8...
Page 584: Interrupt Mask Register (Imr)
15.2.13 Interrupt Mask Register (IMR) The interrupt mask register (IMR) is a 16-bit readable/writable register containing flags that enable or disable requests by individual interrupt sources. Bit: IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 — Initial value: R/W: — Bit: —...
Page 585 Bit 12—Receive Overload Warning Interrupt Mask: Enables or disables error warning interrupt requests caused by the receive error counter. Bit 12: IMR4 Description REC error warning interrupt request to CPU by IRR4 enabled REC error warning interrupt request to CPU by IRR4 disabled (Initial value) Bit 11—Transmit Overload Warning Interrupt Mask: Enables or disables error warning interrupt requests caused by the transmit error counter.
Page 586: Receive Error Counter (Rec)
Bit 1—Unread Interrupt Mask: Enables or disables unread receive message overwrite interrupt requests. Bit 1: IMR9 Description Unread message overwrite interrupt request to CPU by IRR9 enabled Unread message overwrite interrupt request to CPU by IRR9 disabled (Initial value) Bit 0—Mailbox Empty Interrupt Mask: Enables or disables mailbox empty interrupt requests. Bit 0: IMR8 Description Mailbox empty interrupt request to CPU by IRR8 enabled...
Page 587: Unread Message Status Register (Umsr)
15.2.16 Unread Message Status Register (UMSR) The unread message status register (UMSR) is a 16-bit readable/writable register containing status flags that indicate, for individual mailboxes (buffers), that a received message has been overwritten by a new receive message before being read. If a previously received message is overwritten by a newly received message, the old data will be lost.
Page 588: Local Acceptance Filter Masks (Lafml, Lafmh)
15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH) The local acceptance filter masks (LAFML, LAFMH) are 16-bit readable/writable registers that filter receive messages to be stored in the receive-only mailbox (RX0) according to the identifier. In these registers, consist of LAFMH15 (MSB) to LAFMH5 (LSB) are 11 standard/extended identifier bits, and LAFMH1 (MSB) to LAFML0 (LSB) are 18 extended identifier bits.
Page 589: Message Control (Mc0 To Mc15)
LAFMH Bits 12 to 10—Reserved: These bits always read 0. The write value should always be 0. LAFMH Bits 9 and 8, LAFML bits 15 to 0–18-Bit Identifier Filter (LAFMHx, LAFMLx): Filter mask bits for the 18 bits of the receive message identifier (extended). Bit x: LAFMHx LAFMLx Description...
Page 590 MCx [4] Bit: — — — — — — — — Initial value: R/W: MCx [5] Bit: — STD_ID2 STD_ID1 STD_ID0 EXD_ID17 EXD_ID16 Initial value: R/W: MCx [6] Bit: STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Initial value: R/W: MCx [7] Bit: EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0...
Page 591 MCx[1] Bits 3 to 0—Data Length Code (DLC): These bits indicate the required length of data frames and remote frames. Bit 3: Bit 2: Bit 1: Bit 0: DLC3 DLC2 DLC1 DLC0 Description Data length = 0 byte Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes...
Page 592 MCx[5] Bit 4—Remote Transmission Request (RTR): Used to distinguish between data frames and remote frames. Bit 4: RTR Description Data frame Remote frame MCx[5] Bit 3—Identifier Extension (IDE): Used to distinguish between the standard format and extended format of data frames and remote frames. Bit 3: IDE Description Standard format...
Page 593: Message Data (Md0 To Md15)
15.2.19 Message Data (MD0 to MD15) The message data register sets (MD0 to MD15) consist of eight 8-bit readable/writable registers (MDx[1] to MDx[8]). The HCAN has 16 sets of these registers (MD0 to MD15). The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1). MDx [1] MSG_DATA_1 (8 bits) MDx [2]...
Page 594: Operation
15.3 Operation This LSI device is equipped with 2-channel HCAN modules, which are controlled independently. Both modules have identical specifications, and they are controlled in the same manner. 15.3.1 Hardware and Software Resets The HCAN can be reset by a hardware reset or software reset. Hardware Reset (HCAN Module Stop, Reset*, Hardware*/Software Standby): Initialization is performed by automatic setting of the MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3) in GSR within the HCAN (hardware reset).
Page 595 Hardware reset MCR0 = 1 (automatic) IRR0 = 1 (automatic) GSR3 = 1 (automatic) Initialization of HCAN module Bit configuration mode Clear IRR0 Period in which BCR, MBCR, etc., BCR setting are initialized MBCR setting Mailbox (RAM) initialization Message transmission method initialization MCR0 = 0 GSR3 = 0? IMR setting (interrupt mask setting)
Page 596 MCR0 = 1 Bus idle? GSR3 = 1 (automatic) Initialization of REC and TEC only Correction BCR setting MBCR setting Mailbox (RAM) initialization Message transmission method initialization MCR0 = 0 GSR3 = 0? Correction IMR setting MBIMR setting MC[x] setting LAFM setting GSR3 = 0 &...
Page 597 Clearing the IRR0 bit of the Interrupt Register (IRR): The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby mode. A HCAN interrupt is immediately entered if interrupts are enabled, so the IRR0 must be cleared. Bit Rate and Bit Timing Settings: As bit rate settings, a baud rate setting and bit timing setting must be made each time a CAN node begins communication.
Page 598 Example: With a 1 Mb/s baud rate and a 20 MHz input clock: 20 MHz 1 Mb/s = 2 × (0 + 1) × (3 + 4 + 3) Set Values Actual Values = 20 MHz — System clock × 2 BRP = 0 (B'000000) TSEG1 = 4 (B'0100) TSEG2 = 3 (B'011)
Page 599 Table 15-4 Setting Range for TSEG1 and TSEG2 in BCR TSEG2 (BCR [14:12]) TSEG1 0011 (BCR [11:8]) 0100 Yes* 0101 Yes* 0110 Yes* 0111 Yes* 1000 Yes* 1001 Yes* 1010 Yes* 1011 Yes* 1100 Yes* 1101 Yes* 1110 Yes* 1111 Yes* Notes: The time quanta value for TSEG1 and TSEG2 is the TSEG value + 1.
Page 600 • Setting for reception Transmit/receive mailbox setting (mailboxes 1 to 15) Setting a bit to 1 in the mailbox configuration register (MBCR) designates the corresponding mailbox for reception use. When setting mailboxes for reception, to improve message transmission efficiency, high-priority messages should be set in low-to-high mailbox order (priority order: mailbox 1 >...
Page 601: Transmit Mode
Mailbox (Message Control/Data (MCx[x], MDx[x])) Initial Settings: After power is supplied, all registers and RAM (message control/data, control registers, status registers, etc.) are initialized. Message control/data (MCx[x], MDx[x]) only are in RAM, and so their values are undefined. Initial values must therefore be set in all the mailboxes (by writing 0s or 1s). Setting the Message Transmission Method: Either of the following message transmission methods can be selected with the message transmission method bit (MCR2) in the master control register (MCR):...
Page 602 Message transmission and interrupts a. Message transmission wait b. Message transmission completion and interrupt c. Message transmission abort d. Message retransmission Initialization (After Hardware Reset Only): These settings should be made while the HCAN is in bit configuration mode. • IRR0 clearing The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby mode.
Page 603 Initialization (after hardware reset only) IRR0 clearing BCR setting MBCR setting Mailbox initialization Message transmission method setting Interrupt settings Transmit data setting Arbitration field setting Control field setting Data field setting Message transmission wait TXPR setting Bus idle? Message transmission GSR2 = 0 (during transmission only) Transmission completed? TXACK = 1...
Page 604 Interrupt and Transmit Data Settings: When mailbox initialization is finished, CPU interrupt source settings and data settings must be made. Interrupt source settings are made in the mailbox interrupt register (MBIMR) and interrupt mask register (IMR), while transmit data settings are made by writing the necessary data from the arbitration field, control field, and data field, described below, in the corresponding message control (MCx[1]–MCx[8]) and message data (MDx[1]–MDx[8]).
Page 605 When b is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), the message with the highest priority set in the message identifier (MCx[5]–MCx[8]) is stored in the transmit buffer. CAN bus arbitration is then carried out for the message in the transmit buffer, and message transmission is performed when the transmission right is acquired.
Page 606 Message transmit wait TXPR setting Set TXCR bit corresponding to message to be canceled Cancellation possible? Message not sent Completion of message transmission Clear TXCR, TXPR TXACK = 1 ABACK = 1 Clear TXCR, TXPR IRR8 = 1 IRR8 = 1 IMR8 = 1? Interrupt to CPU Clear TXACK...
Page 607: Receive Mode
15.3.4 Receive Mode Message reception is performed using mailboxes 0 and 1 to 15. The reception procedure is described below, and a reception flowchart is shown in figure 15-9. Initialization (after hardware reset only) a. IRR0 bit in the interrupt register (IRR0) clearing b.
Page 608 • Mailbox (RAM) initialization As message control/data registers (MCx[x], MDx[x]) are configured in RAM, their initial values after powering on are undefined, and so bit initialization is necessary. Write 0s or 1s to the mailboxes. Refer to Mailbox (message control/data (MCx[x], MDx[x])) initial settings in section 15.3.2, Initialization after Hardware Reset, for details.
Page 609 : Settings by user Initialization BCR setting : Processing by hardware MBCR setting Mailbox (RAM) initialization Interrupt settings Receive data setting Arbitration field setting Local acceptance filter settings Message reception (Match of identifier in mailbox?) Same RXPR = 1? Unread message Data frame? RXPR RXPR, RFPR = 1...
Page 610 Interrupt and Receive Message Settings: When mailbox initialization is finished, CPU interrupt source settings and receive message specifications must be made. Interrupt source settings are made in the mailbox interrupt register (MBIMR) and interrupt mask register (IMR). To receive a message, the identifier must be set in advance in the message control (MCx[1]–MCx[8]) for the receiving mailbox.
Page 611 Message Reception and Interrupts: • Message reception CRC check When a message is received, a CRC check is performed automatically (by hardware). If the result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of whether or not the message can be received.
Page 612 value at this time, an interrupt can be sent to the CPU. Figure 15-10 shows a flowchart of unread message overwriting. Unread message overwrite UMSR = 1 IRR9 = 1 IMR9 = 1? Interrupt to CPU Clear IRR9 Message control/message data read : Settings by user : Processing by hardware Figure 15-10 Unread Message Overwrite Flowchart...
Page 613: Hcan Sleep Mode
15.3.5 HCAN Sleep Mode The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep state to reduce current dissipation. Figure 15-11 shows a flowchart of the HCAN sleep mode. MCR5 = 1 Bus idle? Initialize TEC and REC Bus operation? IRR12 = 1...
Page 614: Hcan Halt Mode
HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is delayed until the bus becomes idle. Either of the following methods of clearing HCAN sleep mode can be selected by making a setting in the MCR7 bit.
Page 615: Interrupt Interface
HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until the bus becomes idle. HCAN halt mode is cleared by clearing MCR1 to 0. 15.3.7 Interrupt Interface There are 12 HCAN interrupt sources, to which five independent interrupt vectors are assigned.
Page 616: Dtc Interface
15.3.8 DTC Interface The DTC can be activated by reception of a message in the HCAN’s mailbox 0. When DTC transfer ends after DTC activation has been set, the RXPR0 and RFPR0 flags are acknowledge signal automatically. An interrupt request due to a receive interrupt from the HCAN cannot be sent to the CPU in this case.
Page 617: Can Bus Interface
15.4 CAN Bus Interface A bus transceiver IC is necessary to connect the H8S/2646 Series chip to a CAN bus. A Philips PCA82C250 transceiver IC, or compatible device, is recommended. Figure 15-14 shows a sample connection diagram. 124 Ω H8S/2646 Series...
Page 618 set mailboxes. 4. Error counters In the case of error active and error passive, REC and TEC normally count up and down. In the bus off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96 during the count, IRR4 and GSR1 are set.
Page 619: Section 16 A/D Converter
Section 16 A/D Converter 16.1 Overview The H8S/2646 Series incorporates a successive approximation type 10-bit A/D converter that allows up to twelve analog input channels to be selected. 16.1.1 Features A/D converter features are listed below. • 10-bit resolution • Twelve input channels •...
Page 620: Block Diagram
16.1.2 Block Diagram Figure 16-1 shows a block diagram of the A/D converter. Module data bus Internal data bus 10-bit D/A ø/2 – ø/4 Comparator Control circuit ø/8 Sample-and- ø/16 hold circuit AN10 AN11 interrupt ADTRG Conversion start trigger from TPU ADCR : A/D control register ADCSR...
Page 621: Pin Configuration
16.1.3 Pin Configuration Table 16-1 summarizes the input pins used by the A/D converter. The AV and AV pins are the power supply pins for the analog block in the A/D converter. The pin is the A/D conversion reference voltage pin. The 12 analog input pins are divided into two channel sets and two groups, with analog input pins 0 to 7 (AN0 to AN7) comprising channel set 0, analog input pins 8 to 11 (AN8 to AN11) comprising channel set 1, analog input pins 0 to 3 and 8 to 11 (AN0 to AN3, AN8 to AN11)
Page 622: Register Configuration
16.1.4 Register Configuration Table 16-2 summarizes the registers of the A/D converter. Table 16-2 A/D Converter Registers Name Abbreviation Initial Value Address A/D data register AH ADDRAH H'00 H'FF90 A/D data register AL ADDRAL H'00 H'FF91 A/D data register BH ADDRBH H'00 H'FF92...
Page 623: Register Descriptions
16.2 Register Descriptions 16.2.1 A/D Data Registers A to D (ADDRA to ADDRD) — — — — — — Initial value There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there.
Page 624: A/D Control/Status Register (Adcsr)
16.2.2 A/D Control/Status Register (ADCSR) ADIE ADST SCAN Initial value R/(W)* Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations. ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode. Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.
Page 625 Bit 5—A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST Description...
Page 626 Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channels. Only set the input channel while conversion is stopped (ADST = 0). Channel Selection Description Single Mode Scan Mode (SCAN = 0) (SCAN = 1)
Page 627: A/D Control Register (Adcr)
16.2.3 A/D Control Register (ADCR) TRGS1 TRGS0 — — CKS1 CKS0 — — Initial value — — — — ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations and sets the A/D conversion time. ADCR is initialized to H'33 by a reset, and in standby mode or module stop mode.
Page 628: Module Stop Control Register A (Mstpcra)
16.2.4 Module Stop Control Register A (MSTPCRA) MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value MSTPCR is a 8-bit readable/writable register that performs module stop mode control. When the MSTPA1 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 629: Interface To Bus Master
16.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP).
Page 630: Operation
16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. 16.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1, according to the software or external trigger input.
Page 631 Set* ADIE Set* Set* conversion starts ADST Clear* Clear* State of channel 0 (AN0) Idle State of channel 1 (AN1) Idle Idle Idle A/D conversion A/D conversion State of channel 2 (AN2) Idle State of channel 3 (AN3) Idle ADDRA Read conversion result Read conversion result ADDRB...
Page 632: Scan Mode (Scan = 1)
16.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the first channel in the group (AN0).
Page 633 Continuous A/D conversion execution Clear ADST Clear A/D conversion time State of channel 0 (AN0) Idle Idle Idle A/D conversion 1 A/D conversion 4 State of channel 1 (AN1) Idle Idle Idle A/D conversion 2 A/D conversion 5 State of channel 2 (AN2) Idle Idle A/D conversion 3...
Page 634: Input Sampling And A/D Conversion Time
16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 16-5 shows the A/D conversion timing.
Page 635: External Trigger Input Timing
Table 16-4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS1 = 0 CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1 Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max A/D conversion start delay t —...
Page 636: Interrupts
16.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC can be activated by an ADI interrupt. Having the converted data read by the DTC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software.
Page 637 Also, digital circuitry must be isolated from the analog input signals (AN0 to AN11), analog reference power supply (V ), and analog power supply (AV ) by the analog ground (AV Also, the analog ground (AV ) should be connected at one point to a stable digital ground (V on the board.
Page 638 To A/D converter 20 pF Note: Values are reference values. Figure 16-8 Analog Input Pin Equivalent Circuit A/D Conversion Precision Definitions: H8S/2646 Series A/D conversion precision definitions are given below. • Resolution The number of A/D converter digital output codes •...
Page 639 Digital output Ideal A/D conversion characteristic Quantization error 1022 1023 1024 1024 1024 1024 Analog input voltage Figure 16-9 A/D Conversion Precision Definitions (1)
Page 640 Figure 16-10 A/D Conversion Precision Definitions (2) Permissible Signal Source Impedance: H8S/2646 Series analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 kΩ or less. This specification is provided to enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling time;...
Page 641 GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AV Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. H8S/2646 Series A/D converter equivalent circuit Sensor output impedance 10 kΩ...
Page 643: Section 17 Motor Control Pwm Timer
Section 17 Motor Control PWM Timer 17.1 Overview The H8S/2646 Series has an on-chip motor control PWM (pulse width modulator) with a maximum capability of 16 pulse outputs. 17.1.1 Features Features of the motor control PWM are given below. • Maximum of 16 pulse outputs ...
Page 644: Block Diagram
• Module stop mode  As the initial setting, PWM operation is halted. Register access is enabled by clearing module stop mode. 17.1.2 Block Diagram Figure 17-1 shows a block diagram of PWM channel 1. ø, ø/2, ø/4, ø/8, ø/16 Interrupt Port PWCR1...
Page 645 Figure 17-2 shows a block diagram of PWM channel 2. ø, ø/2, ø/4, ø/8, ø/16 Port Interrupt PWCR2 PWCNT2 PWOCR2 control request Compare match PWCYR2 PWPR2 12 9 PWDTR2A PWM2A PWBFR2A PWDTR2B PWM2B PWBFR2B Internal data bus PWM2C PWDTR2C PWBFR2C PWM2D PWDTR2D PWBFR2D...
Page 646: Pin Configuration
17.1.3 Pin Configuration Table 17-1 shows the PWM pin configuration. Table 17-1 PWM Pin Configuration Name Abbrev. Function PWM output pin 1A PWM1A Output Channel 1A PWM output PWM output pin 1B PWM1B Output Channel 1B PWM output PWM output pin 1C PWM1C Output Channel 1C PWM output...
Page 647: Register Configuration
17.1.4 Register Configuration Table 17-2 shows the register configuration of the PWM. Table 17-2 PWM Registers Channel Name Abbrev. Initial Value Address* PWM control register 1 PWCR1 H'C0 H'FC00 PWM output control register 1 PWOCR1 H'00 H'FC02 PWM polarity register 1 PWPR1 H'00 H'FC04...
Page 648: Register Descriptions
17.2 Register Descriptions 17.2.1 PWM Control Registers 1 and 2 (PWCR1, PWCR2) — — CKS2 CKS1 CKS0 Initial value Read/Write — — R/(W)* Note: * Only 0 can be written, to clear the flag. PWCR is an 8-bit read/write register that performs interrupt enabling, starting/stopping, and counter (PWCNT) clock selection.
Page 649: Pwm Output Control Registers 1 And 2 (Pwocr1, Pwocr2)
Bit 3—Counter Start (CST): Bit 3 selects starting or stopping of the PWCNT counter for the corresponding channel. Bit 3: CST Description PWCNT is stopped (Initial value) PWCNT is started Bits 2 to 0—Clock Select (CKS): Bits 2 to 0 select the clock for the PWCNT counter in the corresponding channel.
Page 650: Pwm Polarity Registers 1 And 2 (Pwpr1, Pwpr2)
Bits 7 to 0—Output Enable (OE): Each of these bits enables or disables the corresponding PWM output. Bits 7 to 0: Description PWM output is disabled (Initial value) PWM output is enabled 17.2.3 PWM Polarity Registers 1 and 2 (PWPR1, PWPR2) PWPR1 OPS1H OPS1G...
Page 651: Pwm Counters 1 And 2 (Pwcnt1, Pwcnt2)
17.2.4 PWM Counters 1 and 2 (PWCNT1, PWCNT2) — — — — — — Initial value Read/Write — — — — — — — — — — — — — — — — PWCNT is a 10-bit up-counter incremented by the input clock. The input clock is selected by clock select bits 2 to 0 (CKS2 to CKS0) in PWCR.
Page 652: Pwm Duty Registers 1A, 1C, 1E, 1G (Pwdtr1A, 1C, 1E, 1G)
17.2.6 PWM Duty Registers 1A, 1C, 1E, 1G (PWDTR1A, 1C, 1E, 1G) — — — OTS — — DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 Initial value Read/Write — — — — — — — — — —...
Page 653 is no high-level output period (no low-level output period when the corresponding bit in PWPR1 is set to 1). Compare match PWCNT1 M–2 M–1 N–1 (lower 10 bits) PWCYR1 (lower 10 bits) PWDTR1 (lower 10 bits) PWM output on selected pin PWM output on unselected pin Figure 17-4 Duty Register Compare Match (OPS = 0 in PWPR1)
Page 654: Pwm Buffer Registers 1A, 1C, 1E, 1G (Pwbfr1A, 1C, 1E, 1G)
17.2.7 PWM Buffer Registers 1A, 1C, 1E, 1G (PWBFR1A, 1C, 1E, 1G) — — — OTS — — DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 Initial value Read/Write — — — R/W — — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W There are four 16-bit read/write PWBFR1 registers (PWBFR1A, 1C, 1E, 1G).
Page 655 Bits 15 to 10—Reserved: These bits cannot be read from or written to. Bits 9 to 0—Duty (DT): Bits 9 to 0 set the PWM output duty according to the values in bits 9 to 0 in the buffer register that is transferred by a PWCYR2 compare match. A high level (or a low level when the corresponding bit in PWPR2 is set to 1) is output from the time PWCNT2 is cleared by a PWCYR2 compare match until a PWDTR2 compare match occurs.
Page 656: Pwm Buffer Registers 2A To 2D (Pwbfr2A To Pwbfr2D)
17.2.9 PWM Buffer Registers 2A to 2D (PWBFR2A to PWBFR2D) — — — TDS — — DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 Initial value Read/Write — — — R/W — — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W There are four 16-bit read/write PWBFR2 registers (PWBFR2A to PWBFR2D).
Page 657: Module Stop Control Register D (Mstpcrd)
17.2.10 Module Stop Control Register D (MSTPCRD) MSTPD7 MSTPD6 — — — — — — Initial value undefined undefined undefined undefined undefined undefined Read/Write — — — — — — MSTPCRD is an 8-bit read/write register that performs module stop mode control. When the MSTPD7 bit is set to 1, PWM timer operation is stopped at the end of the bus cycle, and module stop mode is entered.
Page 658: Bus Master Interface
17.3 Bus Master Interface 17.3.1 16-Bit Data Registers PWCYR1/2, PWBFR1A/C/E/G, and PWBFR2A/B/C/D are 16-bit registers. These registers are linked to the bus master by a 16-bit data bus, and can be read or written in 16-bit units. They cannot be read by 8-bit access; 16-bit access must always be used. Internal data bus Module master...
Page 659: Operation
17.4 Operation 17.4.1 PWM Channel 1 Operation PWM waveforms are output from pins PWM1A to PWM1H as shown in figure 17-10. Initial Settings: Set the PWM output polarity in PWPR1; enable the pins for PWM output with PWOCR1; select the clock to be input to PWCNT1 with bits CKS2 to CKS0 in PWCR1; set the PWM conversion cycle in PWCYR1;...
Page 660: Pwm Channel 2 Operation
Stopping: When the CST bit in PWCR1 is cleared to 0, PWCNT1 is reset and stops. All PWM outputs go low (or high if the corresponding bit in PWPR1 is set to 1). 17.4.2 PWM Channel 2 Operation PWM waveforms are output from pins PWM2A to PWM2H as shown in figure 17-11. Initial Settings: Set the PWM output polarity in PWPR2;...
Page 661: Usage Note
H'000. The CMF bit in PWCR2 is set, and if the IE bit in PWCR2 has been set, an interrupt can be requested or the DTC can be activated. Stopping: When the CST bit in PWCR2 is cleared to 0, PWCNT2 is reset and stops. PWDTR2A to PWDTR2H are reset.
Page 663: Section 18 Lcd Controller/Driver
Section 18 LCD Controller/Driver 18.1 Overview The H8S/2646 Series has an on-chip segment type LCD control circuit, LCD driver, and power supply circuit, enabling it to directly drive an LCD panel. 18.1.1 Features Features of the LCD controller/driver are given below.
Page 664: Block Diagram
SEG1 SEGn, DO Legend: LPCR: LCD port control register LCR: LCD control register LCR2: LCD control register 2 Notes: *1 In the H8S/2646, H8S/2646R, and H8S/2645. *2 In the H8S/2648, H8S/2648R, and H8S/2647. Figure 18-1 Block Diagram of LCD Controller/Driver...
Page 665: Pin Configuration
Table 18-1 shows the LCD controller/driver pin configuration. Table 18-1 Pin Configuration Name Abbreviation Function Segment output SEG24 to SEG1 Output LCD segment drive pins pins (H8S/2646, All pins are multiplexed as port pins (setting H8S/2646R, programmable) H8S/2645) SEG40 to SEG1 (H8S/2648, H8S/2648R, H8S/2647) Common output...
Page 666: Register Descriptions
18.2 Register Descriptions 18.2.1 LCD Port Control Register (LPCR) DTS1 DTS0 — SGS3 SGS2 SGS1 SGS0 Initial value Read/Write — LPCR is an 8-bit read/write register which selects the duty cycle, LCD driver, and pin functions. LPCR is initialized to H'00 upon reset and in standby mode. Bits 7 to 5—Duty Cycle Select 1 and 0 (DTS1, DTS0), Common Function Select (CMX): The combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty.
Page 667 Bits 3 to 0—Segment Driver Select 3 to 0 (SGS3 to SGS0): Bits 3 to 0 select the segment drivers to be used. • H8S/2646, H8S/2646R, H8S/2645 Function of Pins SEG24 to SEG1 Bit 3: Bit 2: Bit 1: Bit 0:...
Page 668 • H8S/2648, H8S/2648R, H8S/2647 Function of Pins SEG40 to SEG1 SEG40 SEG32 SEG28 SEG24 SEG20 SEG16 SEG12 SEG8 SEG4 Bit 3: Bit 2: Bit 1: Bit 0: SGS3 SGS2 SGS1 SGS0 SEG33 SEG29 SEG25 SEG21 SEG17 SEG13 SEG9 SEG5 SEG1 Notes Port Port Port...
Page 669: Lcd Control Register (Lcr)
18.2.2 LCD Control Register (LCR) — DISP CKS3 CKS2 CKS1 CKS0 Initial value Read/Write — LCR is an 8-bit read/write register which performs LCD power supply split-resistance connection control and display data control, and selects the frame frequency. LCR is initialized to H'80 upon reset and in standby mode. Bit 7—Reserved: This bit is always read as 1 and cannot be modified.
Page 670 Bits 3 to 0—Frame Frequency Select 3 to 0 (CKS3 to CKS0): Bits 3 to 0 select the operating clock and the frame frequency. In subactive mode, watch mode, and subsleep mode, the system clock (ø) is halted, and therefore display operations are not performed if one of the clocks from ø/8 to ø/1024 is selected.
Page 671: Lcd Control Register 2 (Lcr2)
18.2.3 LCD Control Register 2 (LCR2) LCDAB — — — — — — — Initial value Read/Write — — — — — — — LCR2 is an 8-bit read/write register which controls switching between the A waveform and B waveform. LCR2 is initialized to H'70 upon reset and in standby mode.
Page 672: Module Stop Control Register D (Mstpcrd)
18.2.4 Module Stop Control Register D (MSTPCRD) MSTPD7 MSTPD6 — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Read/Write — — — — — — MSTPCRD is an 8-bit read/write register that performs module stop mode control. When the MSTPD6 bit is set to 1, LCD controller/driver operation is stopped at the end of the bus cycle, and module stop mode is entered.
Page 673: Operation
COM3. • LCD drive power supply setting With the H8S/2646 Series, there are two ways of providing LCD power: by using the on-chip power supply circuit, or by using an external power supply circuit. When an external power supply circuit is used for the LCD drive power supply, connect the...
Page 674 Software Settings • Duty selection Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits DTS1 and DTS0. • Segment selection The segment drivers to be used can be selected with bits SGS3 to SGS0. •...
Page 675: Relationship Between Lcd Ram And Display
18.3.2 Relationship between LCD RAM and Display H8S/2646, H8S/2646R, H8S/2645 The relationship between the LCD RAM and the display segments differs according to the duty cycle. LCD RAM maps for the different duty cycles are shown in figures 18-3 to 18-6.
Page 676 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FC40 Space not used for display H'FC47 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 H'FC48 Display space H'FC53 SEG24 SEG24 SEG24 SEG23 SEG23 SEG23 COM3 COM2 COM1 COM3 COM2 COM1 Figure 18-4 LCD RAM Map (1/3 Duty)
Page 677 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Space not H'FC40 used for H'FC41 display H'FC42 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 Display H'FC44 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 space Space not used for display...
Page 678 H8S/2648, H8S/2648R, H8S/2647 The relationship between the LCD RAM and the display segments differs according to the duty cycle. LCD RAM maps for the different duty cycles are shown in figures 18-7 to 18-10. After setting the registers required for display, data is written to the part corresponding to the duty using the same kind of instruction as for ordinary RAM, and display is started automatically when turned on.
Page 679 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FC40 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 H'FC53 SEG40 SEG40 SEG40 SEG39 SEG39 SEG39 COM3 COM2 COM1 COM3 COM2 COM1 Space not used for display Figure 18-8 LCD RAM Map (1/3 Duty) Bit 7 Bit 6...
Page 680 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 H'FC40 Display space SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 H'FC44 Space not used for display H'FC53 COM1 COM1...
Page 681 1 frame 1 frame Data Data COM1 COM1 COM2 COM2 COM3 COM3 COM4 SEGn SEGn (a) Waveform with 1/4 duty (b) Waveform with 1/3 duty 1 frame 1 frame Data Data COM1 COM1 COM2 SEGn SEGn (d) Waveform with static output (c) Waveform with 1/2 duty Figure 18-11 Output Waveforms for Each Duty Cycle (A Waveform)
Page 682 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame Data Data COM1 COM1 COM2 COM2 COM3 COM3 COM4 SEGn SEGn (a) Waveform with 1/4 duty (b) Waveform with 1/3 duty 1 frame 1 frame 1 frame 1 frame 1 frame...
Page 683: Operation In Power-Down Modes
Segment output 18.3.3 Operation in Power-Down Modes In the H8S/2646 Series, the LCD controller/driver can be operated even in the power-down modes. The operating state of the LCD controller/driver in the power-down modes is summarized in table 18-4. In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and therefore, unless ø...
Page 684: Boosting The Lcd Drive Power Supply
0.1 to 0.3 µF to pins V1 to V3, or to connect a new split-resistance externally, as shown in figure 18-13. several kΩ to several MΩ H8S/2646 Series C = 0.1 to 0.3 µF Figure 18-13 Connection of External Split-Resistance...
Page 685: Section 19 Ram
19.1 Overview The H8S/2646, H8S/2646R, H8S/2648, and H8S/2648R have 4 kbytes and H8S/2645 and H8S/2647 have 2 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer.
Page 686: Register Configuration
19.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 19-1 shows the address and initial value of SYSCR. Table 19-1 RAM Register Name Abbreviation Initial Value Address* System control register SYSCR H'01 H'FDE5 Note: * Lower 16 bits of the address. 19.2 Register Descriptions 19.2.1...
Page 687: Operation
When the RAME bit is set to 1, accesses to addresses H'FFE000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2646, H8S/2646R, H8S/2648, and H8S/2648R to addresses H'FFE7C0 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2645 and H8S/2647, are directed to the on- chip RAM.
Page 689: Section 20 Rom
Section 20 ROM 20.1 Features The LSI (H8S/2646R, H8S/2648R) has 128 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode ...
Page 690: Overview
20.2 Overview 20.2.1 Block Diagram Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Operating FWE pin Bus interface/controller mode Mode pin EBR1 EBR2 RAMER FLPWCR Flash memory (128 kbytes) Legend FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR1: Erase block register 1 EBR2:...
Page 691: Mode Transitions
20.2.2 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the microcomputer enters an operating mode as shown in figure 20-2. In user mode, flash memory can be read but not programmed or erased. The boot, user program and programmer modes are provided as modes to write and erase the flash memory.
Page 692: On-Board Programming Modes
20.2.3 On-Board Programming Modes Boot Mode 1. Initial state 2. Programming control program transfer The old program version or data remains written When boot mode is entered, the boot program in in the flash memory. The user should prepare the the LSI (originally incorporated in the chip) is programming control program and new started and the programming control program in...
Page 693 User Program Mode 1. Initial state 2. Programming/erase control program transfer The FWE assessment program that confirms that When user program mode is entered, user user program mode has been entered, and the software confirms this fact, executes transfer program that will transfer the programming/erase program in the flash memory, and transfers the control program from flash memory to on-chip programming/erase control program to RAM.
Page 694: Flash Memory Emulation In Ram
20.2.4 Flash Memory Emulation in RAM Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. Flash memory Overlap RAM Emulation block...
Page 695: Differences Between Boot Mode And User Program Mode
Flash memory Overlap RAM Programming data (programming data) Programming control program execution state Application program Figure 20-4 Writing Overlap RAM Data in User Program Mode 20.2.5 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Total erase Block erase Programming control program* (1) (2) (3)
Page 696: Block Configuration
20.2.6 Block Configuration The flash memory is divided into two 32 kbytes blocks, one 28 kbytes block, one 16 kbytes block, two 8 kbytes blocks, and four 1 kbyte blocks. Address H'00000 × 1 kbyte 28 kbytes 16 kbytes 8 kbytes 128 kbytes 8 kbytes 32 kbytes...
Page 697: Pin Configuration
20.3 Pin Configuration The flash memory is controlled by means of the pins shown in table 20-1. Table 20-1 Pin Configuration Pin Name Abbreviation Function Reset Input Reset Flash write enable Input Flash program/erase protection by hardware Mode 2 Input Sets LSI operating mode Mode 1 Input...
Page 698: Register Configuration
20.4 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 20-2. Table 20-2 Register Configuration Register Name Abbreviation Initial Value Address Flash memory control register 1 FLMCR1 H'00 H'FFA8 Flash memory control register 2 FLMCR2 H'00 H'FFA9...
Page 699 Bit: Initial value: —* R/W: Note: * Determined by the state of the FWE pin. Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7: FWE Description When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Bit 6—Software Write Enable Bit (SWE): Enables or disables flash memory programming and erasing.
Page 700 Bit 4—Program Setup Bit (PSU): Prepares for a transition to program mode. Set this bit to 1 before setting the P bit in FLMCR1 to 1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time.
Page 701: Flash Memory Control Register 2 (Flmcr2)
Bit 0—Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Bit 0: P Description Program mode cleared (Initial value) Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 20.5.2 Flash Memory Control Register 2 (FLMCR2)
Page 702: Erase Block Register 1 (Ebr1)
20.5.3 Erase Block Register 1 (EBR1) EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set.
Page 703: Ram Emulation Register (Ramer)
Table 20-3 Flash Memory Erase Blocks Block (Size) Addresses EB0 (1 kbyte) H'000000–H'0003FF EB1 (1 kbyte) H'000400–H'0007FF EB2 (1 kbyte) H'000800–H'000BFF EB3 (1 kbyte) H'000C00–H'000FFF EB4 (28 kbytes) H'001000–H'007FFF EB5 (16 kbytes) H'008000–H'00BFFF EB6 (8 kbytes) H'00C000–H'00DFFF EB7 (8 kbytes) H'00E000–H'00FFFF EB8 (32 kbytes) H'010000–H'017FFF...
Page 704: Flash Memory Power Control Register (Flpwcr)
Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected. Bit 3: RAMS Description Emulation not selected (Initial value) Program/erase-protection of all flash memory blocks is disabled Emulation selected Program/erase-protection of all flash memory blocks is enabled Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together...
Page 705: On-Board Programming Modes
Bit 7: PDWND Description Transition to flash memory power-down mode enabled (Initial value) Transition to flash memory power-down mode disabled Bits 6 to 0—Reserved: These bits always read 0. 20.6 On-Board Programming Modes When pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory.
Page 706 Flash memory Host Write data reception RxD1 SCI1 On-chip RAM Verify data transmission TxD1 Figure 20-6 System Configuration in Boot Mode...
Page 707 Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Host transmits number LSI measures low period of programming control program of H'00 data transmitted by host bytes (N), upper byte followed by lower byte LSI calculates bit rate and sets value in bit rate register...
Page 708 Automatic SCI Bit Rate Adjustment Start Stop Low period (9 bits) measured (H'00 data) High period (1 or more bits) When boot mode is initiated, the LSI measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity.
Page 709 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the programming control program is transferred via the SCI, as shown in figure 20-8. The boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host.
Page 710: User Program Mode
The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program.
Page 711 Figure 20-9 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD2, MD1, MD0 = 110, 111 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area...
Page 712: Flash Memory Programming/Erasing
20.7 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the on- board programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes for addresses H'000000 to H'01FFFF are made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1.
Page 713 E = 1 Erase setup Erase mode state E = 0 ESU = 1 Normal mode ESU = 0 FWE = 1 FWE = 0 Erase-verify EV = 1 mode On-board SWE = 1 EV = 0 Software programming mode programming Software programming enable...
Page 714: Program Mode
20.7.1 Program Mode When writing data or programs to flash memory, the program/program-verify flowchart shown in figure 20-11 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability.
Page 715: Program-Verify Mode
4. The write pulse is applied and a flash memory write executed while the P bit in FLMCR1 is set. In the H8S/2646, write pulses should be applied as follows in the program/program-verify procedure to prevent voltage stress on the device and loss of write data reliability.
Page 716 When programming is completed at an early stage in the program/program-verify procedure: If programming is completed in the 1st to 6th reprogramming processing loop, additional programming should be performed on the relevant bits. Additional programming should only be performed on bits which first return 0 in a verify-read in certain reprogramming processing.
Page 717 Reprogram Data Computation Table Result of Verify-Read after Write Pulse Application (V) Result of Operation Comments Programming completed: reprogramming processing not to be executed Programming incomplete: reprogramming processing to be executed  Still in erased state: no action Legend (D): Source data of bits on which programming is executed (X): Source data of bits on which reprogramming is executed Additional-Programming Data Computation Table Result of Verify-Read...
Page 718 Start of programming Write pulse application subroutine Perform programming in the erased state. Sub-Routine Write Pulse START Do not perform additional programming on previously programmed addresses. Set SWE bit in FLMCR1 WDT enable ) µs Wait (t sswe Set PSU bit in FLMCR1 Store 128-byte program data in program ) µs data area and reprogram data area...
Page 719: Erase Mode
20.7.3 Erase Mode When erasing flash memory, the single-block erase flowchart shown in figure 20-12 should be followed. The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and the maximum number of erase operations (N) are shown in table 23-10 in section 23.7, Flash Memory Characteristics.
Page 720 Start Perform erasing in block units. Set SWE bit in FLMCR1 ) µs Wait (t sswe n = 1 Set EBR1 or EBR2 *3, *4 Enable WDT Set ESU bit in FLMCR1 ) µs Wait (t sesu Start of erase Set E bit in FLMCR1 Wait (t ) ms...
Page 721: Protection
20.8 Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 20.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2).
Page 722: Software Protection
20.8.2 Software Protection Software protection can be implemented by setting the SWE bit in FLMCR1, erase block register 1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P or E bit in flash memory control register 1 (FLMCR1), does not cause a transition to program mode or erase mode.
Page 723: Error Protection
20.8.3 Error Protection In error protection, an error is detected when H8S/2646 runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing.
Page 724 Figure 20-13 shows the flash memory state transition diagram. Reset or standby Program mode RES = 0 or HSTBY = 0 (hardware protection) Erase mode RD VF PR ER FLER = 0 RD VF PR ER FLER = 0 RES = 0 or Error occurrence HSTBY = 0 FLMCR1, FLMCR2,...
Page 725: Flash Memory Emulation In Ram
20.9 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time.
Page 726 This area can be accessed from both the RAM area and flash memory area H'000000 H'000400 H'000800 H'000C00 H'001000 Flash memory EB4 to EB9 H'FFE000 H'FFE3FF On-chip RAM H'FFEFBF H'01FFFF Figure 20-15 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB0 is Overlapped 1.
Page 727: Interrupt Handling When Programming/Erasing Flash Memory
20.10 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI interrupt is disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode , to give priority to the program or erase operation.
Page 728: 20.11.1 Socket Adapter Pin Correspondence Diagram
Table 20-9 Programmer Mode Pin Settings Pin Names Settings Mode pins: MD2, MD1, MD0 Low level input to MD2, MD1, and MD0. Mode setting pins: PF0, P16, P14 High level input to PF0, low level input to P16 and P14 FWE pin High level input (in auto-program and auto-erase modes)
Page 729 Socket Adapter H8S/2646F-ZTAT, H8S/2648F-ZTAT 40-Pin Socket on Writer (Conversion to Pin Name 40-Pin Pin No. Pin Name Pin No. FP-144 Arrangement) I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 1, 40 1, 21, 56, 66, 84, 85, 91, 92, 98, 119, , LPV cc , AV cc , 11, 30 126, 127...
Page 730: 20.11.2 Programmer Mode Operation
20.11.2 Programmer Mode Operation Table 20-10 shows how the different operating modes are set when using programmer mode, and table 20-11 lists the commands used in programmer mode. Details of each mode are given below. • Memory Read Mode Memory read mode supports byte reads. •...
Page 731: 20.11.3 Memory Read Mode
Table 20-11 Programmer Mode Commands 1st Cycle 2nd Cycle Number Command Name of Cycles Mode Address Data Mode Address Data Memory read mode 1 + n Write H'00 Read Dout Auto-program mode Write H'40 Write Auto-erase mode Write H'20 Write H'20 Status read mode Write...
Page 732 Command write Memory read mode Address stable A18–A0 nxtc I/O7–I/O0 Note: Data is latched on the rising edge of WE. Figure 20-18 Timing Waveforms for Memory Read after Memory Write Table 20-13 AC Characteristics in Transition from Memory Read Mode to Another Mode (Conditions: V = 5.0 V ±0.5 V, V = 0 V, T...
Page 733 Memory read mode Other mode command write Address stable A18–A0 nxtc I/O7–I/O0 Note: Do not enable WE and OE at the same time. Figure 20-19 Timing Waveforms in Transition from Memory Read Mode to Another Mode Table 20-14 AC Characteristics in Memory Read Mode (Conditions: V = 5.0 V ±0.5 V, = 0 V, T = 25°C ±5°C)
Page 734: 20.11.4 Auto-Program Mode
Address stable Address stable A18–A0 I/O7–I/O0 Figure 20-21 CE and OE Clock System Read Timing Waveforms 20.11.4 Auto-Program Mode 1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. 2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses.
Page 735 Table 20-15 AC Characteristics in Auto-Program Mode (Conditions: V = 5.0 V ±0.5 V, = 0 V, T = 25°C ±5°C) Item Symbol Unit Command write cycle — µs nxtc CE hold time — CE setup time — Data hold time —...
Page 736: 20.11.5 Auto-Erase Mode
20.11.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4.
Page 737 A18–A0 nxtc nxtc ests erase I/O7 Erase end decision signal I/O6 Erase normal decision signal I/O5–I/O0 H'20 H'20 H'00 Figure 20-23 Auto-Erase Mode Timing Waveforms...
Page 738: 20.11.6 Status Read Mode
20.11.6 Status Read Mode 1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. The return code is retained until a command write other than a status read mode command write is executed.
Page 739: 20.11.7 Status Polling
Table 20-18 Status Read Mode Return Commands Pin Name I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Attribute Normal Command Program- Erase — — Program- Effective error ming error error ming or address error decision erase count exceeded Initial value 0 Indications Normal Command Program-...
Page 740: 20.11.9 Notes On Memory Programming
Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi. For other chips for which the erasure history is unknown, it is recommended that auto- erasing be executed to check and supplement the initialization (erase) level.
Page 741: Flash Memory And Power-Down States
20.12 Flash Memory and Power-Down States In addition to its normal operating state, the flash memory has power-down states in which power consumption is reduced by halting part or all of the internal power supply circuitry. There are three flash memory operating states: (1) Normal operating mode: The flash memory can be read and written to.
Page 742: Flash Memory Programming And Erasing Precautions
1. Use the specified voltages and timing for programming and erasing. Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Hitachi microcomputer device type with 128-kbyte on-chip flash memory (FZTAT256V3A).
Page 743 4. Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc.
Page 744 Program- ming/ erasing Wait time: Wait time: 100 µs possible φ Min 0 µs OSC1 Min 0 µs MD2 to MD0 SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit) Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
Page 745 Program- ming/ erasing Wait time: Wait time: 100 µs possible φ Min 0 µs OSC1 MD2 to MD0 SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit) Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: *1 Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-...
Page 746 φ OSC1 Min 0µs MD2 to MD0 RESW SWE set cleared SWE bit Boot Mode Mode User User User program mode User program mode change change mode mode mode Period during which flash memory access is prohibited (x: Wait time after setting SWE bit) Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: *1 When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried...
Page 747: Section 21 Clock Pulse Generator
Section 21 Clock Pulse Generator 21.1 Overview The H8S/2646 Series has a built-in clock pulse generator (CPG) that generates the system clock (ø), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock oscillator, and waveform shaping circuit.
Page 748: Register Configuration
21.1.2 Register Configuration The clock pulse generator is controlled by SCKCR and LPWRCR. Table 21-1 shows the register configuration. Table 21-1 Clock Pulse Generator Register Name Abbreviation Initial Value Address* System clock control register SCKCR H'00 H'FDE6 Low-power control register LPWRCR H'00 H'FDEC...
Page 749: Low-Power Control Register (Lpwrcr)
Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation when the PLL circuit frequency multiplication factor is changed. Bit 3 STCS Description Specified multiplication factor is valid after recovery from software standby mode, watch mode, or subactive mode (Initial value) Specified multiplication factor is valid immediately after STC bits are rewritten Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master...
Page 750: Oscillator
Bits 1 and 0—Frequency Multiplication Factor (STC1, STC0): The STC bits specify the frequency multiplication factor of the PLL circuit. Bit 1 Bit 0 STC1 STC0 Description ×1 (Initial value) ×2 ×4 Setting prohibited Note: Make this setting so that the clock frequency both before and after multiplication is within the operating frequency range of the LSI.
Page 751 See figure 21-4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Avoid Signal A Signal B H8S/2646 Series XTAL EXTAL Figure 21-4 Example of Incorrect Board Design...
Page 752 External circuitry such as that shown below is recommended around the PLL. R1: 3 kΩ C1: 470 pF PLLCAP PLLV CB: 0.1 µF * (Values are preliminary recommended values.) Note: * CB is laminated ceramic capacitors. Figure 21-5 Points for Attention when Using PLL Oscillation Circuit Place oscillation stabilization capacitor C1 and resistor R1 close to the PLLCAP pin, and ensure that no other signal lines cross this line.
Page 753: Pll Circuit
21.4 PLL Circuit The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 1, 2, or 4. The multiplication factor is set with the STC bits in SCKCR. The phase of the rising edge of the internal clock is controlled so as to match that at the EXTAL pin.
Page 754: Subclock Oscillator
21.7 Subclock Oscillator Connecting 32.768kHz Quartz Oscillator: To supply a clock to the subclock divider, connect a 32.768kHz quartz oscillator, as shown in figure 21-6. See section 21.3.1, “Notes on Board Design” for notes on connecting quartz oscillators. OSC1 OSC2 =15pF (typ)* Note: * C and C...
Page 755: Subclock Waveform Generation Circuit
21.8 Subclock Waveform Generation Circuit To eliminate noise from the subclock input to OSCI, the subclock is sampled using the dividing clock ø. The sampling frequency is set using the NESEL bit of LPWRCR. For details, see section 22.2.3, Low-Power Control Register (LPWRCR). No sampling is performed in sub-active mode, sub-sleep mode, or watch mode.
Page 757: Section 22 Power-Down Modes
22.1 Overview In addition to the normal program execution state, the H8S/2646 Series has nine power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on.
Page 758 Table 22-1 LSI Internal States in Each Mode High- Medium- Module Sub- Software Hardware Function Speed Speed Sleep Stop Watch active Subsleep Standby Standby System clock pulse Function- Function- Function- Function- Halted Halted Halted Halted Halted generator Subclock pulse Function- Function- Function- Function-...
Page 759 Program-halted state STBY pin = Low Hardware Reset state standby mode STBY pin = High RES pin = Low RES pin = High Program execution state SSBY= 0, LSON= 0 Sleep mode SLEEP instruction (main clock) High-speed mode (main clock) Any interrupt * SSBY= 1, SLEEP...
Page 760 Table 22.2 Low Power Dissipation Mode Transition Conditions State After Transition Status of Control Bit at State After Transition Back from Low Power Transition Pre-Transition Invoked by SLEEP Mode Invoked by State SSBY PSS LSON DTON Instruction Interrupt High-speed/ Sleep High-speed/Medium-speed Medium-speed 0 —...
Page 761: Register Configuration
22.1.1 Register Configuration Power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, TCSR (WDT1), and MSTPCR registers. Table 22-3 summarizes these registers. Table 22-3 Power-Down Mode Registers Name Abbreviation Initial Value Address* Standby control register SBYCR H'58 H'FDE4 System clock control register SCKCR H'00 H'FDE6...
Page 762: Register Descriptions
22.2 Register Descriptions 22.2.1 Standby Control Register (SBYCR) SSBY STS2 STS1 STS0 — — — Initial value — — — SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'58 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Page 763 Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time for clock stabilization when shifting to high-speed mode or medium-speed mode by using a specific interrupt or command to cancel software standby mode, watch mode, or sub-active mode. With a quartz oscillator (table 22-5), select a wait time of 8ms (oscillation stabilization time) or more, depending on the operating frequency.
Page 764: System Clock Control Register (Sckcr)
22.2.2 System Clock Control Register (SCKCR) PSTOP — — — STCS SCK2 SCK1 SCK0 Initial value — — — SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium- speed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Page 765: Low-Power Control Register (Lpwrcr)
Bits 2 to 0—System clock select (SCK2 to SCK0): These bits select the bus master clock in high-speed mode, medium-speed mode, and sub-active mode. Set SCK2 to SCK0 all to 0 when shifting to operation in watch mode or sub-active mode. Bit 2 Bit 1 Bit 0...
Page 766 Bit 7 DTON Description • When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode*. • When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-sleep mode or watch mode.
Page 767 Bit 5—Noise Elimination Sampling Frequency Select (NESEL): This bit selects the sampling frequency of the subclock (øSUB) generated by the subclock oscillator is sampled by the clock (ø) generated by the system clock oscillator. Set this bit to 0 when ø=5MHz or more. This setting is disabled in sub-active mode, sub-sleep mode, and watch mode.
Page 768: Timer Control/Status Register (Tcsr)
22.2.4 Timer Control/Status Register (TCSR) WT/IT RST/NMI CKS2 CKS1 CKS0 Initial value R/(W)* Note: * Only write 0 to clear the flag. TCSR is an 8-bit read/write register that selects the clock input to WDT1 TCNT and the mode. Here, we describe bit 4. For details of the other bits in this register, see section 12.2.2, Timer Control/Status Register (TCSR).
Page 769: Module Stop Control Register (Mstpcr)
22.2.5 Module Stop Control Register (MSTPCR) MSTPCRA MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : MSTPCRB (H8S/2646, H8S/2646R, H8S/2645) MSTPB7 MSTPB6 — MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : — MSTPCRB (H8S/2648, H8S/2648R, H8S/2647) MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0...
Page 770: Medium-Speed Mode
MSTPB4 to MSTPB0 MSTPC7, and MSTPC5 to MSTPC0 MSTPD7 and MSTPD6 Description (H8S/2646, H8S/2646R, H8S/2645) Module stop mode is cleared (initial value of MSTPA7 and MSTPA6) Module stop mode is set (initial value of MSTPA5 to 0, MSTPB7 to 0,...
Page 771: Sleep Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and LSON bit in LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit = 1, LPWRCR LSON bit = 0, and TCSR (WDT1) PSS bit = 0, operation shifts to the software standby mode.
Page 772: Module Stop Mode
Exiting Sleep Mode by Interrupts: When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. Exiting Sleep Mode by RES pin: Setting the RES pin level Low selects the reset state. After the stipulated reset input duration, driving the RES pin High starts the CPU performing reset exception processing.
Page 773: Usage Notes
MSTPB5 Serial communication interface 2 (SCI2) (H8S/2648, H8S/2648R, H8S/2647) MSTPCRC MSTPC4 PC break controller (PBC) MSTPC3 Hitachi controller area network (HCAN) MSTPCRD MSTPD7 Motor control PWM (PWM) MSTPD6 LCD controller/driver Note: Unlisted bits of the registers are reserved. The write value must always be 1.
Page 774: Software Standby Mode
When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire H8S/2646 Series chip. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling.
Page 775: Setting Oscillation Stabilization Time After Clearing Software Standby Mode
22.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time).
Page 776: Usage Notes
Oscillator ø NMIEG SSBY NMI exception Software standby mode NMI exception Oscillation handling (power-down mode) handling stabilization NMIEG=1 time t SSBY=1 OSC2 SLEEP instruction Figure 22-3 Software Standby Mode Application Example 22.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained.
Page 777: Hardware Standby Mode
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while the H8S/2646 Series is in hardware standby mode.
Page 778: Hardware Standby Mode Timing
22.7.2 Hardware Standby Mode Timing Figure 22-4 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high.
Page 779: Exiting Watch Mode
22.8.2 Exiting Watch Mode Watch mode is exited by any interrupt (WOVI interrupt, NMI pin, or IRQ0 to IRQ5), or signals at the RES, or STBY pins. Exiting Watch Mode by Interrupts: When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or medium-speed mode when the LPWRCR LSON bit = 0 or to sub-active mode when the LSON bit = 1.
Page 780: Sub-Sleep Mode
22.9 Sub-Sleep Mode 22.9.1 Sub-Sleep Mode When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to sub-sleep mode. In sub-sleep mode, the CPU is stopped. Supporting modules other than WDT0, and WDT1 are also stopped.
Page 781: Sub-Active Mode
22.10 Sub-Active Mode 22.10.1 Sub-Active Mode When the SLEEP instruction is executed in high-speed mode with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1, LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to sub-active mode.
Page 782: Direct Transitions
22.11 Direct Transitions 22.11.1 Overview of Direct Transitions There are three modes, high-speed, medium-speed, and sub-active, in which the CPU executes programs. When a direct transition is made, there is no interruption of program execution when shifting between high-speed and sub-active modes. Direct transitions are enabled by setting the LPWRCR DTON bit to 1, then executing the SLEEP instruction.
Page 783: Usage Notes
22.13 Usage Notes 1. When making a transition to sub-active mode or watch mode, set the DTC to enter module stop mode (write 1 to the relevant bits in MSTPCR), and then read the relevant bits to confirm that they are set to 1 before mode transition. Do not clear module stop mode (write 0 to the relevant bits in MSTPCR) until a transition from sub-active mode to high-speed mode or medium-speed mode has been performed.
Page 785: Section 23 Electrical Characteristics
Section 23 Electrical Characteristics 23.1 Absolute Maximum Ratings Table 23-1 lists the absolute maximum ratings. Table 23-1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 PMWV Input voltage (OSC1, OSC2) –0.3 +3.5 lnput voltage (XTAL, EXTAL) –0.3 to A +0.3 Input voltage (ports 4 and 9)
Page 786: Power Supply Voltage And Operating Frequency Range
23.2 Power Supply Voltage and Operating Frequency Range Power supply voltage and operating frequency ranges (shaded areas) are shown in figure 23-1. Operating range in high-speed, medium-speed, and sleep modes Power supply voltage (V) Operating range in watch, sub-active, and sub-sleep modes 32.768 Power supply voltage (V) Figure 23-1 Power Supply Voltage and Operating Ranges...
Page 787: Dc Characteristics
23.3 DC Characteristics Table 23-2 lists the DC characteristics. Table 23-3 lists the permissible output currents. Table 23-2 DC Characteristics Conditions: V = PWMV = 4.5 V to 5.5 V, LPV = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = 4.5 V to AV = PWMV = PLLV...
Page 788 Item Symbol Unit Test Conditions Output high Ports 1 to 3, 5, – 0.5 — — = –200 µA voltage H, J, K Ports PF0, PF3, PF7, HTxD Ports A, B, C, – 0.5 — — = –200 µA D, E Ports PF2, PF4 to PF6 Ports 1 to 3, 5,...
Page 789 Item Symbol Min Unit Test Conditions µA MOS input Ports A to E –I — = 0 V pull-up current Input — — = 0 V capacitance f = 1 MHz — — = 25°C All input pins — — except RES and NMI Current...
Page 790 Notes: *1 If the A/D converter is not used, do not leave the AV , and AV pins open. Apply a voltage between 4.5 V and 5.5 V to the AV and V pins by connecting them to V ≤ AV for instance.
Page 791 Table 23-3 Permissible Output Currents Conditions: V = PWMV = 4.5 V to 5.5 V, LPV = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = 4.5 V to AV = PWMV = PLLV = AV = 0 V, T = –20°C to +75°C = –40°C to +85°C (wide-range specifications) *...
Page 792: Ac Characteristics
23.4 AC Characteristics Figure 23-2 show, the test conditions for the AC characteristics. LSI output pin C = 50 pF: Ports A to F (In case of expansion bus control signal output pin setting) C = 30 pF: All ports except ports A to F = 2.4 kΩ...
Page 793: Clock Timing
23.4.1 Clock Timing Table 23-4 lists the clock timing Table 23-4 Clock Timing Condition : = PWMV = 4.5 V to 5.5 V, LPV = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = 4.5 V to AV = PWMV = PLLV = AV...
Page 794 ø Figure 23-3 System Clock Timing STBY OSC1 OSC1 ø Figure 23-4 Oscillator Settling Timing...
Page 795: Control Signal Timing
23.4.2 Control Signal Timing Table 23-5 lists the control signal timing. Table 23-5 Control Signal Timing Condition : = PWMV = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, V = 4.5 V to AV = PWMV = PLLV = AV = 0 V, T...
Page 796 ø RESS RESS RESW Figure 23-5 Reset Input Timing ø NMIS NMIH NMIW IRQW IRQS IRQH Edge input IRQS Level input Figure 23-6 Interrupt Input Timing...
Page 797: Bus Timing
23.4.3 Bus Timing Table 23-6 lists the bus timing. Table 23-6 Bus Timing Condition : = PWMV = 4.5 V to 5.5 V, LPV = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = 4.5 V to AV = PWMV = PLLV = AV...
Page 798 ø A23 to A0 RSD2 RSD1 ACC2 (read) ACC3 D15 to D0 (read) WRD2 WRD2 HWR, LWR (write) WSW1 D15 to D0 (write) Figure 23-7 Basic Bus Timing (Two-State Access)
Page 799 ø A23 to A0 RSD1 RSD2 ACC4 (read) ACC5 D15 to D0 (read) WRD1 WRD2 HWR, LWR (write) WSW2 D15 to D0 (write) Figure 23-8 Basic Bus Timing (Three-State Access)
Page 800 ø A23 to A0 (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) WAIT Figure 23-9 Basic Bus Timing (Three-State Access with One Wait State)
Page 801 or T ø A23 to A0 RSD2 (read) ACC3 D15 to D0 (read) Figure 23-10 Burst ROM Access Timing (Two-State Access)
Page 802 or T ø A23 to A0 RSD2 (read) ACC1 D15 to D0 (read) Figure 23-11 Burst ROM Access Timing (One-State Access)
Page 803: Timing Of On-Chip Supporting Modules
23.4.4 Timing of On-Chip Supporting Modules Table 23-7 lists the timing of on-chip supporting modules. Table 23-7 Timing of On-Chip Supporting Modules Condition : = PWMV = 4.5 V to 5.5 V, LPV = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = 4.5 V to AV = PWMV...
Page 804 Condition Item Symbol Unit Test Conditions Input clock Asynchro- — Figure 23-17 Scyc cycle nous Synchronous — Input clock pulse width SCKW Scyc Input clock rise time — SCKr Input clock fall time — SCKf Transmit data delay time — Figure 23-18 Receive data setup time —...
Page 805 ø Port 1 to 5, 9, A to F, K (read) Port 1 to 3, 5, A to F, K (write) ø Port H, J (read) Port H, J (write) Figure 23-12 I/O Port Input/Output Timing ø PO15 to 8 Figure 23-13 PPG Output Timing...
Page 806 Figure 23-15 TPU Clock Input Timing ø MPWMOD PWM1A to PWM1H, PWM2A to PWM2H Figure 23-16 Motor Control PWM Output Timing SCKr SCKf SCKW H8S/2646, H8S/2646R, H8S/2645: SCK0, SCK1 H8S/2648, H8S/2648R, H8S/2647: SCK0 to SCK2 Scyc Figure 23-17 SCK Clock Input Timing...
Page 807 SCK0, SCK1 TxD0, TxD1 (transmit data) RxD0, RxD1 (receive data) Figure 23-18 SCI Input/Output Timing (Clock Synchronous Mode) ø TRGS ADTRG Figure 23-19 A/D Converter External Trigger Input Timing —Preliminary— HTXD HTxD (transmit data) HRXS HRXH HRxD (receive data) Figure 23-20 HCAN Input/Output Timing...
Page 808: A/D Conversion Characteristics
23.5 A/D Conversion Characteristics Table 23-8 lists the A/D conversion characteristics. Table 23-8 A/D Conversion Characteristics Condition : = PWMV = 4.5 V to 5.5 V, LPV = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = 4.5 V to AV = PWMV = PLLV...
Page 809: Lcd Characteristics
Test Item Symbol Conditions Min Max Unit Notes Segment driver SEG1 to SEG24 ID = 2 µA — — step-down voltage (H8S/2646, H8S/2646R, H8S/2645) SEG1 to SEG40 (H8S/2648, H8S/2648R, H8S/2647) Common driver COM1 to COM4 ID = 2 µA —...
Page 810: Flash Memory Characteristics
23.7 Flash Memory Characteristics Table 23-10 shows the flash memory characteristics. Table 23-10 Flash Memory Characteristics Conditions: V = PWMV = 4.5 V to 5.5 V, LPV = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = 4.5 V to AV PWMV = PLLV...
Page 811 Item Symbol Unit Test Condition Erase Wait time after H'FF dummy — µs sevr write Wait time after EV bit clear — µs Wait time after SWE bit clear — µs cswe * 1* 5 Maximum erase count — Times Notes: *1 Make each time setting in accordance with the program or erase algorithm.
Page 813: Appendix A Instruction Set
Appendix A Instruction Set Instruction List Operand Notation General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-and-accumulate register (32-bit register) (EAd) Destination operand (EAs) Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR...
Page 814 Condition Code Notation Symbol Changes according to the result of instruction Undetermined (no guaranteed value) Always cleared to 0 Always set to 1 — Not affected by execution of the instruction...
Page 837: Instruction Codes
Instruction Codes Table A-2 shows the instruction codes.
Page 852: Operation Code Map
Operation Code Map Table A-3 shows the operation code map.
Page 856: Number Of States Required For Instruction Execution
Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A-5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A-4 indicates the number of states required for each cycle.
Page 857 Table A-4 Number of States per Cycle Access Conditions External Device On-Chip Supporting Module 8-Bit Bus 16-Bit Bus On-Chip 8-Bit 16-Bit 2-State 3-State 2-State 3-State Cycle Memory Access Access Access Access Instruction fetch 6 + 2m 3 + m Branch address read S Stack operation Byte data access 3 + m...
Page 858 Table A-5 Number of Cycles in Instruction Execution Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDS #1/2/4,ERd ADDX ADDX #xx:8,Rd ADDX Rs,Rd...
Page 859 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16...
Page 860 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8...
Page 861 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16...
Page 862 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16...
Page 863 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic EEPMOV EEPMOV.B 2n+2 EEPMOV.W 2n+2 EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 JMP @@aa:8 JSR @ERn...
Page 864 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH LDMAC ERs,MACL MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd...
Page 865 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd)
Page 866 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd...
Page 867 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd...
Page 868 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) 3 STC.W EXR,@(d:16,ERd) 3 STC.W CCR,@(d:32,ERd) 5 STC.W EXR,@(d:32,ERd) 5 STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32...
Page 869 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR Notes: *1 An internal operation may require between 0 and 3 additional states, depending on the preceding instruction.
Page 870: Bus States During Instruction Execution
Bus States During Instruction Execution Table A-6 indicates the types of cycles that occur during instruction execution by the CPU. See table A-4 for the number of states per cycle. How to Read the Table: Order of execution Instruction Internal operation, JMP@aa:24 R:W 2nd R:W EA...
Page 871 Figure A-1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. ø Address bus HWR, LWR High level Internal R:W 2nd R:W EA...
Page 884: Condition Code Modification
Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. 31 for longword operands 15 for word operands 7 for byte operands The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result The specified bit in the destination operand...
Page 885 Table A-7 Condition Code Modification Instruction Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ..· R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm ·...
Page 886 Instruction Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ..· R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm ·...
Page 887 Instruction Definition — — N = Rm Z = Rm · Rm–1 · ..· R0 MOVFPE Can not be used in this LSI MOVTPE MULXS — — — N = R2m Z = R2m · R2m–1 · ..· R0 MULXU —...
Page 888 Instruction Definition ROTXL — N = Rm Z = Rm · Rm–1 · ..· R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTXR — N = Rm Z = Rm · Rm–1 · ..· R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) Stores the corresponding bits of the result.
Page 889 Instruction Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ..· R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm ·...
Page 890: Appendix B Internal I/O Register
Appendix B Internal I/O Register Address Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'EBC0 to MRA 8/16/32* H'EFBF CHNE DISEL — — — —...
Page 891 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'F814 MBIMR MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 HCAN 8/16 H'F815 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10...
Page 892 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'F838 MC3[1] — — — — DLC3 DLC2 DLC1 DLC0 HCAN 8/16 H'F839 MC3[2] — — —...
Page 893 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'F860 MC8[1] — — — — DLC3 DLC2 DLC1 DLC0 HCAN 8/16 H'F861 MC8[2] — — —...
Page 894 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'F888 MC13[1] — — — — DLC3 DLC2 DLC1 DLC0 HCAN 8/16 H'F889 MC13[2] — — —...
Page 895 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'F8C0 MD2[1] MSG_DATA_1 (8 bits) HCAN 8/16 H'F8C1 MD2[2] MSG_DATA_2 (8 bits) H'F8C2 MD2[3] MSG_DATA_3 (8 bits) H'F8C3 MD2[4] MSG_DATA_4 (8 bits)
Page 896 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'F8E8 MD7[1] MSG_DATA_1 (8 bits) HCAN 8/16 H'F8E9 MD7[2] MSG_DATA_2 (8 bits) H'F8EA MD7[3] MSG_DATA_3 (8 bits) H'F8EB MD7[4] MSG_DATA_4 (8 bits)
Page 897 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'F910 MD12[1] MSG_DATA_1 (8 bits) HCAN 8/16 H'F911 MD12[2] MSG_DATA_2 (8 bits) H'F912 MD12[3] MSG_DATA_3 (8 bits) H'F913 MD12[4] MSG_DATA_4 (8 bits)
Page 898 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FC00 PWCR1 — — CKS2 CKS1 CKS0 Motor control H'FC02 PWOCR1 OE1H OE1G OE1F OE1E OE1D OE1C OE1B OE1A...
Page 899 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FC2A PORTK — — — — — — PORT H'FC30 LPCR DTS1 DTS0 — SGS3 SGS2 SGS1 SGS0 LCDC...
Page 900 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FE16 DTCERA DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 H'FE17 DTCERB DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1...
Page 901 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FE80 TCR3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU3 8/16 H'FE81 TMDR3 — — H'FE82 TIOR3H IOB3...
Page 902 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FEC0 IPRA — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC1 IPRB — IPR6 IPR5 IPR4 —...
Page 903 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FF10 TCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU0 8/16 H'FF11 TMDR0 — — H'FF12 TIOR0H IOB3...
Page 904 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FF74 TCSR0 WT/IT — — CKS2 CKS1 CKS0 (read/write) H'FF75 TCNT0 (read) H'FF76 — — — —...
Page 905 Register Module Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FF88 SMR2 STOP CKS1 CKS0 SCI2/ smart card interface H'FF88 SMR2 BCP1 BCP0 CKS1 CKS0 (H8S/2648, H8S/2648R, H'FF89 BRR2...
Page 906: Functions
Functions Register Register Address to which the Name of acronym name register is mapped on-chip supporting module DACR—D/A Control Register H'FFFA D/A Converter numbers Initial bit DAOE1 DAOE0 — — — — — values Initial value Names of the bits. Dashes Read/Write —...
Page 907 MRA—DTC Mode Register A H'EBC0–H'EFBF Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write — — — — — — — — DTC Data Transfer Size 0 Byte-size transfer 1 Word-size transfer DTC Transfer Mode Select 0 Destination side is repeat area or block area 1 Source side is repeat area or block area...
Page 908 MRB—DTC Mode Register B H'EBC0–H'EFBF CHNE DISEL — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write — — — — — — — — DTC Interrupt Select 0 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 1 After a data transfer ends, the CPU interrupt is enabled...
Page 909 CRA—DTC Transfer Count Register A H'EBC0–H'EFBF Initial value Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined Read/Write —...
Page 910 MCR—Master Control Register H'F800 HCAN MCR7 — MCR5 — — MCR2 MCR1 MCR0 Initial value Read/Write — — — Reset Request Normal operating mode (MCR0 = 0 and GSR3 = 0) [Setting condition] When 0 is written after an HCAN reset HCAN reset mode transition request Halt Request...
Page 911 GSR—General Status Register H'F801 HCAN — — — — GSR3 GSR2 GSR1 GSR0 Initial value Read/Write — — — — Bus Off Flag 0 [Reset condition] Recovery from bus off state 1 When TEC ≥ 256 (bus off state) Transmit/Receive Warning Flag 0 [Reset condition] When TEC <...
Page 912 BCR—Bit Configuration Register H'F802 HCAN BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0 Initial value Read/Write Resynchronization Jump Width Baud Rate Prescale 2 × system clock Bit synchronization width = 1 time quantum 4 × system clock Bit synchronization width = 2 time quanta 6 ×...
Page 913 MBCR—Mailbox Configuration Register H'F804 HCAN MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 — Initial value Read/Write — MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8 Initial value Read/Write Mailbox Setting Register Corresponding mailbox is set for transmission Corresponding mailbox is set for reception TXPR—Transmit Wait Register H'F806 HCAN...
Page 914 TXCR—Transmit Wait Cancel Register H'F808 HCAN TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 — Initial value Read/Write — TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8 Initial value Read/Write Transmit Wait Cancel Register Transmit message cancellation idle state in corresponding mailbox [Clearing condition] Completion of TXPR clearing (when transmit message is canceled normally)
Page 915 ABACK—Abort Acknowledge Register H'F80C HCAN ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 — Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* — ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*...
Page 916 RFPR—Remote Request Register H'F810 HCAN RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8 Initial value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Read/Write...
Page 917 IRR—Interrupt Register H'F812 HCAN IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Reset Interrupt Flag [Clearing condition] Writing 1 Transition to hardware reset (HCAN module stop, software standby) [Setting condition] When reset processing is completed after hardware reset transition (HCAN module stop, software standby) Note: After canceling a reset or returning from hardware standby...
Page 918 — — — IRR12 — — IRR9 IRR8 Initial value Read/Write — — — R/(W)* — — R/(W)* R/(W)* Mailbox Empty Interrupt Flag 0 [Clearing condition] Writing 1 Transmit message has been transmitted or aborted, and new message can be stored [Setting condition] When TXPR (transmit wait register) is cleared by completion of transmission or completion of transmission abort...
Page 919 MBIMR—Mailbox Interrupt Mask Register H'F814 HCAN MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 Initial value Read/Write MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8 Initial value Read/Write Mailbox Interrupt Mask [Transmitting] Interrupt request to CPU due to TXPR clearing [Receiving] Interrupt request to CPU due to RXPR setting Interrupt requests to CPU disabled...
Page 920 IMR—Interrupt Mask Register H'F816 HCAN IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 — Initial value Read/Write — Receive Message Interrupt Mask Message reception interrupt request to CPU by IRR1 enabled Message reception interrupt request to CPU by IRR1 disabled Remote Frame Request Interrupt Mask Remote frame reception interrupt request to CPU by IRR2 enabled Remote frame reception interrupt request to CPU by IRR2 disabled Transmit Overload Warning Interrupt Mask...
Page 921 — — — IMR12 — — IMR9 IMR8 Initial value Read/Write — — — — — Mailbox Empty Interrupt Mask Mailbox empty interrupt request to CPU by IRR8 enabled Mailbox empty interrupt request to CPU by IRR8 disabled Unread Interrupt Mask Unread message overwrite interrupt request to CPU by IRR9 enabled Unread message overwrite interrupt request to CPU by IRR9 disabled Bus Operation Interrupt Mask...
Page 922 REC—Receive Error Counter H'F818 HCAN Initial value Read/Write TEC—Transmit Error Counter H'F819 HCAN Initial value Read/Write UMSR—Unread Message Status Register H'F81A HCAN UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* UMSR15 UMSR14...
Page 923 LAFML—Local Acceptance Filter Masks L H'F81C HCAN LAFMH—Local Acceptance Filter Masks H H'F81E HCAN LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0 Initial value Read/Write LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8 Initial value Read/Write LAFMH LAFMH7 LAFMH6 LAFMH5 —...
Page 924 MC01—Message Control 01 H'F820 HCAN MC02—Message Control 02 H'F821 HCAN MC03—Message Control 03 H'F822 HCAN MC04—Message Control 04 H'F823 HCAN MC05—Message Control 05 H'F824 HCAN MC06—Message Control 06 H'F825 HCAN MC07—Message Control 07 H'F826 HCAN MC08—Message Control 08 H'F827 HCAN MC01 —...
Page 925 MC04 — — — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write MC05 STD_ID2 STD_ID1 STD_ID0 — EXD_ID17 EXD_ID16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Identifier Extension...
Page 926 MC07 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC08 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value...
Page 927 MC11—Message Control 11 H'F828 HCAN MC12—Message Control 12 H'F829 HCAN MC13—Message Control 13 H'F82A HCAN MC14—Message Control 14 H'F82B HCAN MC15—Message Control 15 H'F82C HCAN MC16—Message Control 16 H'F82D HCAN MC17—Message Control 17 H'F82E HCAN MC18—Message Control 18 H'F82F HCAN MC11 —...
Page 928 MC14 — — — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write MC15 STD_ID2 STD_ID1 STD_ID0 — EXD_ID17 EXD_ID16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Identifier Extension...
Page 929 MC17 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC18 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value...
Page 930 MC21—Message Control 21 H'F830 HCAN MC22—Message Control 22 H'F831 HCAN MC23—Message Control 23 H'F832 HCAN MC24—Message Control 24 H'F833 HCAN MC25—Message Control 25 H'F834 HCAN MC26—Message Control 26 H'F835 HCAN MC27—Message Control 27 H'F836 HCAN MC28—Message Control 28 H'F837 HCAN MC21 —...
Page 931 MC24 — — — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write MC25 STD_ID2 STD_ID1 STD_ID0 — EXD_ID17 EXD_ID16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Identifier Extension...
Page 932 MC27 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC28 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value...
Page 933 MC31—Message Control 31 H'F838 HCAN MC32—Message Control 32 H'F839 HCAN MC33—Message Control 33 H'F83A HCAN MC34—Message Control 34 H'F83B HCAN MC35—Message Control 35 H'F83C HCAN MC36—Message Control 36 H'F83D HCAN MC37—Message Control 37 H'F83E HCAN MC38—Message Control 38 H'F83F HCAN MC31 —...
Page 934 MC34 — — — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write MC35 STD_ID2 STD_ID1 STD_ID0 — EXD_ID17 EXD_ID16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Identifier Extension...
Page 935 MC37 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC38 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value...
Page 936 MC41—Message Control 41 H'F840 HCAN MC42—Message Control 42 H'F841 HCAN MC43—Message Control 43 H'F842 HCAN MC44—Message Control 44 H'F843 HCAN MC45—Message Control 45 H'F844 HCAN MC46—Message Control 46 H'F845 HCAN MC47—Message Control 47 H'F846 HCAN MC48—Message Control 48 H'F847 HCAN MC41 —...
Page 937 MC44 — — — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write MC45 STD_ID2 STD_ID1 STD_ID0 — EXD_ID17 EXD_ID16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Identifier Extension...
Page 938 MC47 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC48 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value...
Page 939 MC51—Message Control 51 H'F848 HCAN MC52—Message Control 52 H'F849 HCAN MC53—Message Control 53 H'F84A HCAN MC54—Message Control 54 H'F84B HCAN MC55—Message Control 55 H'F84C HCAN MC56—Message Control 56 H'F84D HCAN MC57—Message Control 57 H'F84E HCAN MC58—Message Control 58 H'F84F HCAN MC51 —...
Page 940 MC54 — — — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write MC55 STD_ID2 STD_ID1 STD_ID0 — EXD_ID17 EXD_ID16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Identifier Extension...
Page 941 MC57 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC58 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value...
Page 942 MC61—Message Control 61 H'F850 HCAN MC62—Message Control 62 H'F851 HCAN MC63—Message Control 63 H'F852 HCAN MC64—Message Control 64 H'F853 HCAN MC65—Message Control 65 H'F854 HCAN MC66—Message Control 66 H'F855 HCAN MC67—Message Control 67 H'F856 HCAN MC68—Message Control 68 H'F857 HCAN MC61 —...
Page 943 MC64 — — — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write MC65 STD_ID2 STD_ID1 STD_ID0 — EXD_ID17 EXD_ID16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Identifier Extension...
Page 944 MC67 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC68 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value...
Page 945 MC71—Message Control 71 H'F858 HCAN MC72—Message Control 72 H'F859 HCAN MC73—Message Control 73 H'F85A HCAN MC74—Message Control 74 H'F85B HCAN MC75—Message Control 75 H'F85C HCAN MC76—Message Control 76 H'F85D HCAN MC77—Message Control 77 H'F85E HCAN MC78—Message Control 78 H'F85F HCAN MC71 —...
Page 946 MC74 — — — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write MC75 STD_ID2 STD_ID1 STD_ID0 — EXD_ID17 EXD_ID16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Identifier Extension...
Page 947 MC77 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC78 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value...
Page 948 MC81—Message Control 81 H'F860 HCAN MC82—Message Control 82 H'F861 HCAN MC83—Message Control 83 H'F862 HCAN MC84—Message Control 84 H'F863 HCAN MC85—Message Control 85 H'F864 HCAN MC86—Message Control 86 H'F865 HCAN MC87—Message Control 87 H'F866 HCAN MC88—Message Control 88 H'F867 HCAN MC81 —...
Page 949 MC84 — — — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write MC85 STD_ID2 STD_ID1 STD_ID0 — EXD_ID17 EXD_ID16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Identifier Extension...
Page 950 MC87 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC88 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value...
Page 951 MC91—Message Control 91 H'F868 HCAN MC92—Message Control 92 H'F869 HCAN MC93—Message Control 93 H'F86A HCAN MC94—Message Control 94 H'F86B HCAN MC95—Message Control 95 H'F86C HCAN MC96—Message Control 96 H'F86D HCAN MC97—Message Control 97 H'F86E HCAN MC98—Message Control 98 H'F86F HCAN MC91 —...
Page 952 MC94 — — — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write MC95 STD_ID2 STD_ID1 STD_ID0 — EXD_ID17 EXD_ID16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Identifier Extension...
Page 953 MC97 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC98 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value...
Page 954 MC101—Message Control 101 H'F870 HCAN MC102—Message Control 102 H'F871 HCAN MC103—Message Control 103 H'F872 HCAN MC104—Message Control 104 H'F873 HCAN MC105—Message Control 105 H'F874 HCAN MC106—Message Control 106 H'F875 HCAN MC107—Message Control 107 H'F876 HCAN MC108—Message Control 108 H'F877 HCAN MC101 —...
Page 955 MC104 — — — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write MC105 STD_ID2 STD_ID1 STD_ID0 — EXD_ID17 EXD_ID16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Identifier Extension...
Page 956 MC107 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC108 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value...
Page 957 MC111—Message Control 111 H'F878 HCAN MC112—Message Control 112 H'F879 HCAN MC113—Message Control 113 H'F87A HCAN MC114—Message Control 114 H'F87B HCAN MC115—Message Control 115 H'F87C HCAN MC116—Message Control 116 H'F87D HCAN MC117—Message Control 117 H'F87E HCAN MC118—Message Control 118 H'F87F HCAN MC111 —...
Page 958 MC114 — — — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write MC115 STD_ID2 STD_ID1 STD_ID0 — EXD_ID17 EXD_ID16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Identifier Extension...
Page 959 MC117 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC118 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value...
Page 960 MC121—Message Control 121 H'F880 HCAN MC122—Message Control 122 H'F881 HCAN MC123—Message Control 123 H'F882 HCAN MC124—Message Control 124 H'F883 HCAN MC125—Message Control 125 H'F884 HCAN MC126—Message Control 126 H'F885 HCAN MC127—Message Control 127 H'F886 HCAN MC128—Message Control 128 H'F887 HCAN MC121 —...
Page 961 MC124 — — — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write MC125 STD_ID2 STD_ID1 STD_ID0 — EXD_ID17 EXD_ID16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Identifier Extension...
Page 962 MC127 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC128 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value...
Page 963 MC131—Message Control 131 H'F888 HCAN MC132—Message Control 132 H'F889 HCAN MC133—Message Control 133 H'F88A HCAN MC134—Message Control 134 H'F88B HCAN MC135—Message Control 135 H'F88C HCAN MC136—Message Control 136 H'F88D HCAN MC137—Message Control 137 H'F88E HCAN MC138—Message Control 138 H'F88F HCAN MC131 —...
Page 964 MC134 — — — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write MC135 STD_ID2 STD_ID1 STD_ID0 — EXD_ID17 EXD_ID16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Identifier Extension...
Page 965 MC137 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC138 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value...
Page 966 MC141—Message Control 141 H'F890 HCAN MC142—Message Control 142 H'F891 HCAN MC143—Message Control 143 H'F892 HCAN MC144—Message Control 144 H'F893 HCAN MC145—Message Control 145 H'F894 HCAN MC146—Message Control 146 H'F895 HCAN MC147—Message Control 147 H'F896 HCAN MC148—Message Control 148 H'F897 HCAN MC141 —...
Page 967 MC144 — — — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write MC145 STD_ID2 STD_ID1 STD_ID0 — EXD_ID17 EXD_ID16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Identifier Extension...
Page 968 MC147 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC148 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value...
Page 969 MC151—Message Control 151 H'F898 HCAN MC152—Message Control 152 H'F899 HCAN MC153—Message Control 153 H'F89A HCAN MC154—Message Control 154 H'F89B HCAN MC155—Message Control 155 H'F89C HCAN MC156—Message Control 156 H'F89D HCAN MC157—Message Control 157 H'F89E HCAN MC158—Message Control 158 H'F89F HCAN MC151 —...
Page 970 MC154 — — — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write MC155 STD_ID2 STD_ID1 STD_ID0 — EXD_ID17 EXD_ID16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames Identifier Extension...
Page 971 MC157 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Extended Identifier Set the identifier (extended identifier) of data frames and remote frames MC158 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value...
Page 972 MD01—Message Data 01 H'F8B0 HCAN MD02—Message Data 02 H'F8B1 HCAN MD03—Message Data 03 H'F8B2 HCAN MD04—Message Data 04 H'F8B3 HCAN MD05—Message Data 05 H'F8B4 HCAN MD06—Message Data 06 H'F8B5 HCAN MD07—Message Data 07 H'F8B6 HCAN MD08—Message Data 08 H'F8B7 HCAN MD01 MSG_DATA_1 (8 bits) MD02...
Page 973 MD21—Message Data 21 H'F8C0 HCAN MD22—Message Data 22 H'F8C1 HCAN MD23—Message Data 23 H'F8C2 HCAN MD24—Message Data 24 H'F8C3 HCAN MD25—Message Data 25 H'F8C4 HCAN MD26—Message Data 26 H'F8C5 HCAN MD27—Message Data 27 H'F8C6 HCAN MD28—Message Data 28 H'F8C7 HCAN MD21 MSG_DATA_1 (8 bits) MD22...
Page 974 MD41—Message Data 41 H'F8D0 HCAN MD42—Message Data 42 H'F8D1 HCAN MD43—Message Data 43 H'F8D2 HCAN MD44—Message Data 44 H'F8D3 HCAN MD45—Message Data 45 H'F8D4 HCAN MD46—Message Data 46 H'F8D5 HCAN MD47—Message Data 47 H'F8D6 HCAN MD48—Message Data 48 H'F8D7 HCAN MD41 MSG_DATA_1 (8 bits) MD42...
Page 975 MD61—Message Data 61 H'F8E0 HCAN MD62—Message Data 62 H'F8E1 HCAN MD63—Message Data 63 H'F8E2 HCAN MD64—Message Data 64 H'F8E3 HCAN MD65—Message Data 65 H'F8E4 HCAN MD66—Message Data 66 H'F8E5 HCAN MD67—Message Data 67 H'F8E6 HCAN MD68—Message Data 68 H'F8E7 HCAN MD61 MSG_DATA_1 (8 bits) MD62...
Page 976 MD81—Message Data 81 H'F8F0 HCAN MD82—Message Data 82 H'F8F1 HCAN MD83—Message Data 83 H'F8F2 HCAN MD84—Message Data 84 H'F8F3 HCAN MD85—Message Data 85 H'F8F4 HCAN MD86—Message Data 86 H'F8F5 HCAN MD87—Message Data 87 H'F8F6 HCAN MD88—Message Data 88 H'F8F7 HCAN MD81 MSG_DATA_1 (8 bits) MD82...
Page 977 MD101—Message Data 101 H'F900 HCAN MD102—Message Data 102 H'F901 HCAN MD103—Message Data 103 H'F902 HCAN MD104—Message Data 104 H'F903 HCAN MD105—Message Data 105 H'F904 HCAN MD106—Message Data 106 H'F905 HCAN MD107—Message Data 107 H'F906 HCAN MD108—Message Data 108 H'F907 HCAN MD101 MSG_DATA_1 (8 bits) MD102...
Page 978 MD121—Message Data 121 H'F910 HCAN MD122—Message Data 122 H'F911 HCAN MD123—Message Data 123 H'F912 HCAN MD124—Message Data 124 H'F913 HCAN MD125—Message Data 125 H'F914 HCAN MD126—Message Data 126 H'F915 HCAN MD127—Message Data 127 H'F916 HCAN MD128—Message Data 128 H'F917 HCAN MD121 MSG_DATA_1 (8 bits) MD122...
Page 979 MD141—Message Data 141 H'F920 HCAN MD142—Message Data 142 H'F921 HCAN MD143—Message Data 143 H'F922 HCAN MD144—Message Data 144 H'F923 HCAN MD145—Message Data 145 H'F924 HCAN MD146—Message Data 146 H'F925 HCAN MD147—Message Data 147 H'F926 HCAN MD148—Message Data 148 H'F927 HCAN MD141 MSG_DATA_1 (8 bits) MD142...
Page 980 PWCR1—PWM Control Register 1 H'FC00 PWM1 — — CKS2 CKS1 CKS0 Initial value Read/Write — — R/(W)* Clock Select Internal clock: counts on ø/1 Internal clock: counts on ø/2 Internal clock: counts on ø/4 Internal clock: counts on ø/8 Internal clock: counts on ø/16 *: Don't care Counter Start PWCNT is stopped...
Page 981 PWOCR1—PWM Output Control Register 1 H'FC02 PWM1 OE1H OE1G OE1F OE1E OE1D OE1C OE1B OE1A Initial value Read/Write Output Enable PWM output is disabled PWM output is enabled PWPR1—PWM Polarity Register 1 H'FC04 PWM1 OPS1H OPS1G OPS1F OPS1E OPS1D OPS1C OPS1B OPS1A Initial value...
Page 982 PWBFR1A—PWM Buffer Register 1A H'FC08 PWM1 PWBFR1C—PWM Buffer Register 1C H'FC0A PWM1 PWBFR1E—PWM Buffer Register 1E H'FC0C PWM1 PWBFR1G—PWM Buffer Register 1G H'FC0E PWM1 — — — — — Initial value Read/Write — — — — — Duty The data transferred to bits 9 to 0 in PWDTR1 Output Terminal Select The data transferred to bit 12 of PWDTR1 Register...
Page 983 PWCR2—PWM Control Register 2 H'FC10 PWM2 — — CKS2 CKS1 CKS0 Initial value Read/Write — — R/(W)* Clock Select Internal clock: counts on ø/1 Internal clock: counts on ø/2 Internal clock: counts on ø/4 Internal clock: counts on ø/8 Internal clock: counts on ø/16 *: Don't care Counter Start PWCNT is stopped...
Page 984 PWOCR2—PWM Output Control Register 2 H'FC12 PWM2 OE2H OE2G OE2F OE2E OE2D OE2C OE2B OE2A Initial value Read/Write Output Enable PWM output is disabled PWM output is enabled PWPR2—PWM Polarity Register 2 H'FC14 PWM2 OPS2H OPS2G OPS2F OPS2E OPS2D OPS2C OPS2B OPS2A Initial value...
Page 985 PWBFR2A—PWM Buffer Register 2A H'FC18 PWM2 PWBFR2B—PWM Buffer Register 2B H'FC1A PWM2 PWBFR2C—PWM Buffer Register 2C H'FC1C PWM2 PWBFR2D—PWM Buffer Register 2D H'FC1E PWM2 — — — — — Initial value Read/Write — — — — — Duty Comprise the data transferred to bits 9 to 0 in PWDTR2 Transfer Destination Select Selects the PWDTR2 register to which data is to be transferred...
Page 986 PKDDR—Port K Data Direction Register H'FC22 Port PK7DDR PK6DDR — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Read/Write — — — — — — PHDR—Port H Data Register H'FC24 Port PH7DR PH6DR PH5DR PH4DR PH3DR PH2DR PH1DR...
Page 987 PORTJ—Port J Register H'FC29 Port Initial value —* —* —* —* —* —* —* —* Read/Write Note: * Determined by the state of PJ7 to PJ0. PORTK—Port K Register H'FC2A Port — — — — — — Initial value —* —* Undefined Undefined...
Page 988 DTS1 DTS0 — SGS3 SGS2 SGS1 SGS0 Initial value Read/Write — Segment Driver Select (H8S/2646, H8S/2646R, H8S/2645) Bit 3 Bit 2 Bit 1 Bit 0 Function of Pins SEG24 to SEG1 SEG24 to SEG16 to SEG12 to SEG8 to SEG4 to...
Page 989 LCR—LCD Control Register H'FC31 — DISP CKS3 CKS2 CKS1 CKS0 Initial value Read/Write — Frame Frequency Select Bit 3 Bit 2 Bit 1 Bit 0 Operating Clock Frame Frequency CKS3 CKS2 CKS1 CKS0 ø = 20 MHz ø 128 Hz ø...
Page 990 LCR2—LCD Control Register 2 H'FC32 LCDAB — — — — — — — Initial value Read/Write — — — — — — — A Waveform/B Waveform Switching Control 0 Drive using A waveform 1 Drive using B waveform LCD—LCD RAM H'FC40 to H'FC53 MSTPCRD—Module Stop Control Register D H'FC60...
Page 991 SBYCR—Standby Control Register H'FDE4 System SSBY STS2 STS1 STS0 — — — Initial value Read/Write — — — Output Port Enable In software standby mode, watch mode, and when making a direct transition, address bus and bus control signals are high-impedance In software standby mode, watch mode, and when making a direct transition, the output state of the address bus and bus control signals is retained...
Page 992 SYSCR—System Control Register H'FDE5 System MACS — INTM1 INTM0 NMIEG — — RAME Initial value Read/Write — — RAM Enable 0 On-chip RAM is disabled 1 On-chip RAM is enabled NMI Edge Select 0 An interrupt is requested at the falling edge of NMI input 1 An interrupt is requested at the rising edge of NMI input Interrupt Control Mode 1 and 0 INTM1 INTM0...
Page 993 SCKCR—System Clock Control Register H'FDE6 System PSTOP — — — STCS SCK2 SCK1 SCK0 Initial value Read/Write — — — System Clock Select Bus master in high-speed mode Medium-speed clock is ø/2 Medium-speed clock is ø/4 Medium-speed clock is ø/8 Medium-speed clock is ø/16 Medium-speed clock is ø/32 —...
Page 994 MDCR—Mode Control Register H'FDE7 System — — — — — MDS2 MDS1 MDS0 Initial value —* —* —* Read/Write — — — — — Mode Select 2 to 0 Indicate the input levels at pins MD2 to MD0 Note: * Determined by pins MD2 to MD0. MSTPCRA—Module Stop Control Register A H'FDE8 System...
Page 995 MSTPCRC—Module Stop Control Register C H'FDEA System MSTPC7 — MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value Read/Write — Module Stop Module stop mode is cleared Module stop mode is set PFCR—Pin Function Control Register H'FDEB System — — — —...
Page 996 LPWRCR—Low-Power Control Register H'FDEC System DTON LSON NESEL SUBSTP RFCUT — STC1 STC0 Initial value Read/Write Frequency Multiplication Factor ×1 ×2 ×4 Setting prohibited Note: The clock frequency after a multiplication must not exceed the maximum operating frequency of this LSI. Oscillation Circuit Feedback Resistance Control Bit When the main clock is oscillating, sets the feedback resistance ON.
Page 997 BARA—Break Address Register A H'FE00 BARB—Break Address Register B H'FE04 • • • • • • — — • • • • • • Initial value Unde- Unde- • • • • • • fined fined Read/Write — — • • • •...
Page 998 BCRA—Break Control Register A H'FE08 BCRB—Break Control Register B H'FE09 CMFA BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA Initial value Read/Write R/(W)* Break Interrupt Enable 0 PC break interrupts are disabled PC break interrupts are enabled Break Condition Select Instruction fetch is used as break condition Data read cycle is used as break condition Data write cycle is used as break condition Data read/write cycle is used as break condition...
Page 999 ISCRH—IRQ Sence Control Register H H'FE12 Interrupt Controller ISCRL—IRQ Sence Control Register L H'FE13 Interrupt Controller ISCRH — — — — IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value Read/Write ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value Read/Write IRQ5 to IRQ0 sense control A and B IRQ5SCB to IRQ5SCA to...
Page 1000 IER—IRQ Enable Register H'FE14 Interrupt Controller — — IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value Read/Write IRQ5 to IRQ0 Enable IRQn interrupts disabled IRQn interrupts enabled (n = 5 to 0) ISR—IRQ Status Register H'FE15 Interrupt Controller — — IRQ5F IRQ4F IRQ3F...
Page 1001 DTCER—DTC Enable Register A H'FE16 DTCER—DTC Enable Register B H'FE17 DTCER—DTC Enable Register C H'FE18 DTCER—DTC Enable Register D H'FE19 DTCER—DTC Enable Register E H'FE1A DTCER—DTC Enable Register F H'FE1B DTCER—DTC Enable Register G H'FE1C DTCER—DTC Enable Register I H'FE1E DTCE7 DTCE6 DTCE5...
Page 1002 DTVECR—DTC Vector Register H'FE1F SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value Read/Write R/(W) Specify a number for DTC software activation DTC Software Activation Enable DTC software activation is disabled [Clearing condition] • When the DISEL bit is 0 and the specified number of transfers have not ended •...
Page 1003 PCR—PPG Output Control Register H'FE26 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 0 Compare Match Select Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 Group 1 Compare Match Select Compare match in TPU channel 0 Compare match in TPU channel 1...
Page 1004 PMR—PPG Output Mode Register H'FE27 G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV Initial value Read/Write Group 0 Non-Overlap Normal operation in pulse output group 0 (output values updated at compare match A in the selected TPU channel) Non-overlapping operation in pulse output group 0 (independent 1 and 0 output at compare match A or B in the selected TPU channel) Group 1 Non-Overlap...
Page 1005 NDERH—Next Data Enable Register H H'FE28 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next Data Enable Pulse outputs PO15 to PO8 are disabled (NDR15 to NDR8 are not transferred to POD15 to POD8) Pulse outputs PO15 to PO8 are enabled (NDR15 to NDR8 are transferred to POD15 to POD8) NDERL—Next Data Enable Register L H'FE29...
Page 1006 PODRL—Output Data Register L H'FE2B POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * A bit that has been set for pulse output by NDER is read-only.
Page 1007 NDRH—Next Data Register H H'FE2C, H'FE2E Same Trigger for Pulse Output Groups Address H'FE2C NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value Read/Write Address H'FE2E — — — — — — — — Initial value Read/Write — — —...
Page 1008 NDRL—Next Data Register L H'FE2D, H'FE2F Same Trigger for Pulse Output Groups Address H'FE2D NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value Read/Write Address H'FE2F — — — — — — — — Initial value Read/Write — — —...
Page 1009 P1DDR—Port 1 Data Direction Register H'FE30 Port P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value Read/Write Specify input or output for each of the pins in port 1 P2DDR—Port 2 Data Direction Register H'FE31 Port P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR...
Page 1010 PADDR—Port A Data Direction Register H'FE39 Port PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial value Read/Write Specify input or output for each of the pins in port A PBDDR—Port B Data Direction Register H'FE3A Port PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR...
Page 1011 PEDDR—Port E Data Direction Register H'FE3D Port PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value Read/Write Specify input or output for each of the pins in port E PFDDR—Port F Data Direction Register H'FE3E Port PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR...
Page 1012 PCPCR—Port C MOS Pull-Up Control Register H'FE42 Port PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value Read/Write Control the MOS input pull-up function incorporated into port C PDPCR—Port D MOS Pull-Up Control Register H'FE43 Port PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR...
Page 1013 PAODR—Port A Open Drain Control Register H'FE47 Port PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial value Read/Write Control whether PMOS is on or off for each port A pin PBODR—Port B Open Drain Control Register H'FE48 Port PB7ODR PB6ODR PB5ODR PB4ODR...
Page 1014 TCR3—Timer Control Register 3 H'FE80 TPU3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write Time Prescaler Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input Internal clock: counts on ø/1024 Internal clock: counts on ø/256 Internal clock: counts on ø/4096...
Page 1015 TMDR3—Timer Mode Register 3 H'FE81 TPU3 — — Initial value Read/Write — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — *: Don't care Notes: 1.
Page 1016 TIOR3H—Timer I/O Control Register 3H H'FE82 TPU3 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR3A I/O Control TGR3A is Output disabled output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled...
Page 1017 TIOR3L—Timer I/O Control Register 3L H'FE83 TPU3 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value Read/Write TGR3C I/O Control TGR3C is Output disabled output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled...
Page 1018 TIER3—Timer Interrupt Enable Register 3 H'FE84 TPU3 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value Read/Write — — TGR Interrupt Enable A Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled TGR Interrupt Enable C...
Page 1019 TSR3—Timer Status Register 3 H'FE85 TPU3 — — — TCFV TGFD TGFC TGFB TGFA Initial value Read/Write — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 •...
Page 1020 TCNT3—Timer Counter 3 H'FE86 TPU3 Initial value Read/Write Up-counter TGR3A—Timer General Register 3A H'FE88 TPU3 TGR3B—Timer General Register 3B H'FE8A TPU3 TGR3C—Timer General Register 3C H'FE8C TPU3 TGR3D—Timer General Register 3D H'FE8E TPU3 Initial value Read/Write...
Page 1021 TCR4—Timer Control Register 4 H'FE90 TPU4 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Time Prescaler Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on ø/1024...
Page 1022 TMDR4—Timer Mode Register 4 H'FE91 TPU4 — — — — Initial value — Read/Write — — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 —...
Page 1023 TIOR4—Timer I/O Control Register 4 H'FE92 TPU4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR4A I/O Control TGR4A is Output disabled output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled...
Page 1024 TIER4—Timer Interrupt Enable Register 4 H'FE94 TPU4 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value Read/Write — — — TGR Interrupt Enable A Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable...
Page 1025 TSR4—Timer Status Register 4 H'FE95 TPU4 TCFD — TCFU TCFV — — TGFB TGFA Initial value Read/Write — R/(W)* R/(W)* — — R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 •...
Page 1026 TCNT4—Timer Counter 4 H'FE96 TPU4 Initial value Read/Write Up/down-counter* Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. In other cases they function as up-counters. TGR4A—Timer General Register 4A H'FE98 TPU4 TGR4B—Timer General Register 4B...
Page 1027 TCR5—Timer Control Register 5 H'FEA0 TPU5 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Time Prescaler Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on ø/256...
Page 1028 TMDR5—Timer Mode Register 5 H'FEA1 TPU5 — — — — Initial value — Read/Write — — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 —...
Page 1029 TIOR5—Timer I/O Control Register 5 H'FEA2 TPU5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR5A I/O Control TGR5A is Output disabled output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled...
Page 1030 TIER5—Timer Interrupt Enable Register 5 H'FEA4 TPU5 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value Read/Write — — — TGR Interrupt Enable A Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable...
Page 1031 TSR5—Timer Status Register 5 H'FEA5 TPU5 TCFD — TCFU TCFV — — TGFB TGFA Initial value Read/Write — R/(W)* R/(W)* — — R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 •...
Page 1032 TCNT5—Timer Counter 5 H'FEA6 TPU5 Initial value Read/Write Up/down-counter* Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. In other cases they function as up-counters. TGR5A—Timer General Register 5A H'FEA8 TPU5 TGR5B—Timer General Register 5B...
Page 1033 TSYR—Timer Synchro Register H'FEB1 — — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value Read/Write — — Timer Synchro TCNTn operates independently (TCNT presetting/ clearing is unrelated to other channels) TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible (n = 5 to 0) Notes: 1.
Page 1034 IPRA—Interrupt Priority Register A H'FEC0 IPRB—Interrupt Priority Register B H'FEC1 IPRC—Interrupt Priority Register C H'FEC2 IPRD—Interrupt Priority Register D H'FEC3 IPRE—Interrupt Priority Register E H'FEC4 IPRF—Interrupt Priority Register F H'FEC5 IPRG—Interrupt Priority Register G H'FEC6 IPRH—Interrupt Priority Register H H'FEC7 IPRJ—Interrupt Priority Register J H'FEC9 IPRK—Interrupt Priority Register K...
Page 1035 ABWCR—Bus Width Control Register H'FED0 Bus Controller ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes 5 to 7 Initial value Read/Write Mode 4 Initial value Read/Write Area 7 to 0 Bus Width Control Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) ASTCR—Access State Control Register...
Page 1036 WCRH—Wait Control Register H H'FED2 Bus Controller Initial value Read/Write Area 4 Wait Control 1 and 0 Program wait not inserted when external space area 4 is accessed 1 program wait state inserted when external space area 4 is accessed 2 program wait states inserted when external space area 4 is accessed 3 program wait states inserted when external...
Page 1037 WCRL—Wait Control Register L H'FED3 Bus Controller Initial value Read/Write Area 0 Wait Control 1 and 0 Program wait not inserted when external space area 0 is accessed 1 program wait state inserted when external space area 0 is accessed 2 program wait states inserted when external space area 0 is accessed 3 program wait states inserted when external...
Page 1038 BCRH—Bus Control Register H H'FED4 Bus Controller ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 — — — Initial value Read/Write Burst Cycle Select 0 Max. 4 words in burst access Max. 8 words in burst access Burst Cycle Select 1 Burst cycle comprises 1 state Burst cycle comprises 2 states Burst ROM Enable Area 0 is basic bus interface...
Page 1039 BCRL—Bus Control Register L H'FED5 Bus Controller — — — — — — WDBE WAITE Initial value Read/Write — Wait Enable Wait input by WAIT pin disabled. WAIT pin can be used as I/O port. Wait input by WAIT pin enabled Write Data Buffer Enable Write data buffer function not used Write data buffer function used...
Page 1040 P1DR—Port 1 Data Register H'FF00 Port P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial value Read/Write P2DR—Port 2 Data Register H'FF01 Port P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR Initial value Read/Write P3DR—Port 3 Data Register H'FF02 Port P37DR P36DR P35DR...
Page 1041 PBDR—Port B Data Register H'FF0A Port PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial value Read/Write PCDR—Port C Data Register H'FF0B Port PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR Initial value Read/Write PDDR—Port D Data Register H'FF0C Port PD7DR PD6DR PD5DR...
Page 1042 TCR0—Timer Control Register 0 H'FF10 TPU0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write Time Prescaler Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input...
Page 1043 TMDR0—Timer Mode Register 0 H'FF11 TPU0 — — Initial value Read/Write — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — *: Don't care Notes: 1.
Page 1044 TIOR0H—Timer I/O Control Register 0H H'FF12 TPU0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR0A I/O Control TGR0A is Output disabled output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled...
Page 1045 TIOR0L—Timer I/O Control Register 0L H'FF13 TPU0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value Read/Write TGR0C I/O Control TGR0C is Output disabled output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled...
Page 1046 TIER0—Timer Interrupt Enable Register 0 H'FF14 TPU0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value Read/Write — — TGR Interrupt Enable A Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled TGR Interrupt Enable C...
Page 1047 TSR0—Timer Status Register 0 H'FF15 TPU0 — — — TCFV TGFD TGFC TGFB TGFA Initial value Read/Write — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 •...
Page 1048 TCNT0—Timer Counter 0 H'FF16 TPU0 Initial value Read/Write Up-counter TGR0A—Timer General Register 0A H'FF18 TPU0 TGR0B—Timer General Register 0B H'FF1A TPU0 TGR0C—Timer General Register 0C H'FF1C TPU0 TGR0D—Timer General Register 0D H'FF1E TPU0 Initial value Read/Write 1016...
Page 1049 TCR1—Timer Control Register 1 H'FF20 TPU1 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Time Prescaler Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on ø/256...
Page 1050 TMDR1—Timer Mode Register 1 H'FF21 TPU1 — — — — Initial value — Read/Write — — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 —...
Page 1051 TIOR1—Timer I/O Control Register 1 H'FF22 TPU1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR1A I/O Control TGR1A is Output disabled output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled...
Page 1052 TIER1—Timer Interrupt Enable Register 1 H'FF24 TPU1 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value Read/Write — — — TGR Interrupt Enable A Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable...
Page 1053 TSR1—Timer Status Register 1 H'FF25 TPU1 TCFD — TCFU TCFV — — TGFB TGFA Initial value Read/Write — R/(W)* R/(W)* — — R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 •...
Page 1054 TCNT1—Timer Counter 1 H'FF26 TPU1 Initial value Read/Write Up/down-counter* Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. In other cases they function as up-counters. TGR1A—Timer General Register 1A H'FF28 TPU1 TGR1B—Timer General Register 1B...
Page 1055 TCR2—Timer Control Register 2 H'FF30 TPU2 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Time Prescaler Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input...
Page 1056 TMDR2—Timer Mode Register 2 H'FF31 TPU2 — — — — Initial value — Read/Write — — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 —...
Page 1057 TIOR2—Timer I/O Control Register 2 H'FF32 TPU2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR2A I/O Control TGR2A is Output disabled output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled...
Page 1058 TIER2—Timer Interrupt Enable Register 2 H'FF34 TPU2 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value Read/Write — — — TGR Interrupt Enable A Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable...
Page 1059 TSR2—Timer Status Register 2 H'FF35 TPU2 TCFD — TCFU TCFV — — TGFB TGFA Initial value Read/Write — R/(W)* R/(W)* — — R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 •...
Page 1060 TCNT2—Timer Counter 2 H'FF36 TPU2 Initial value Read/Write Up/down-counter* Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. In other cases they function as up-counters. TGR2A—Timer General Register 2A H'FF38 TPU2 TGR2B—Timer General Register 2B...
Page 1061 TCSR0—Timer Control/Status Register 0 H'FF74(W), H'FF74(R) WDT0 WT/IT — — CKS2 CKS1 CKS0 Initial value Read/Write R/(W)* — — Clock Select 2 to 0 CKS2 CKS1 CKS0 Clock Overflow Period* (where ø = 20 MHz) 25.6 µs ø/2 819.2 µs ø/64 ø/128 1.6 ms...
Page 1062 Reset Enable Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows Note: * The modules within the H8S/2646 are not reset, but TCNT and TCSR within the WDT are reset. Watchdog Overflow Flag [Clearing condition]...
Page 1063 SMR0—Serial Mode Register 0 H'FF78 SCI0 STOP CKS1 CKS0 Initial value Read/Write Clock Select 1 and 0 ø clock ø/4 clock ø/16 clock ø/64 clock Multiprocessor Mode Multiprocessor function disabled Multiprocessor format selected Stop Bit Length 1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent.
Page 1064 Notes: *1 When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first transfer. *2 When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission.
Page 1065 SMR0—Serial Mode Register 0 H'FF78 SCI0, Smart Card Interface 0 BCP1 BCP0 CKS1 CKS0 Initial value Read/Write Clock Select 1 and 0 ø clock ø/4 clock ø/16 clock ø/64 clock Basic Clock Pulse 32 clock periods 64 clock periods 372 clock periods 256 clock periods Parity Mode Even parity...
Page 1066 Notes: When the smart card interface is used, be sure to make the 1 setting shown for bit 5. *1 When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission.
Page 1067 SCR0—Serial Control Register 0 H'FF7A SCI0 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock Enable 1 and 0 Asynchronous Internal clock/SCK pin mode functions as I/O port Clocked Internal clock/SCK pin synchronous mode functions as serial clock output Asynchronous Internal clock/SCK pin mode functions as clock output Clocked...
Page 1068 Notes: *1 TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. *2 RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0.
Page 1069 SCR0—Serial Control Register 0 H'FF7A SCI0, Smart Card Interface 0 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock Enable 1 and 0 SCMR SCR Setting SCK Pin Function SMIF C/A, GM CKE1 CKE0 See the SCI Operates as port I/O pin Outputs clock as SCK output pin Operates as SCK output...
Page 1070 SSR0—Serial Status Register 0 H'FF7C SCI0 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor Bit Transfer 0 Data with a 0 multi-processor bit is transmitted 1 Data with a 1 multi-processor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor...
Page 1071 Notes: *1 The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. *2 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost.
Page 1072 SSR0—Serial Status Register 0 H'FF7C SCI0, Smart Card Interface 0 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Operate in the same way as for the normal SCI. Error Signal Status 0 Normal reception, with no error signal [Clearing condition] •...

This manual is also suitable for:

H8s/2647 H8s/2648 H8s/2646r f-ztat H8s/2648r f-ztat H8s/2645

Hitachi H8S/2646 Hardware Manual

Section 1 Overview

Cpu

MCU Operating Modes

Exception Handling

Interrupt Controller

PC Break Controller (PBC)

Bus Controller

Data Transfer Controller (DTC)

I/O Ports

Section 10 16-Bit Timer Pulse Unit (TPU)

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Summary of Contents for Hitachi H8S/2646