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Manuals and User Guides for Sony SS-HQ1. We have
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Sony SS-HQ1 manual available for free PDF download: Application Notes
Sony SS-HQ1 Application Notes (258 pages)
Brand:
Sony
| Category:
Speakers
| Size: 1.79 MB
Table of Contents
Table of Contents
2
1 System Concept
7
Comparison of SS-HQ1 and SS-1M System Specifications
7
New Functions in SS-HQ1 System
8
2 System Configuration
9
IC Configuration
9
Clock Configuration
11
Clock / Digital Encoder System Configuration
11
Clock / ECK Master - MCK PLL System Configuration
11
Output Configuration
12
Analog Composite (YCMIX) Output System Configuration
12
Digital Output System Configuration (REC656, REC601)
12
3 Peripheral Circuits
13
Initially Occupied Terminals
13
If no Valid Data in EEPROM
13
Processing of Empty Pins
14
Processing of Empty Pins in each Mode
14
Processing of Empty Pins in Case DAC Is Not Used
15
Processing of Empty Pins in Case Internal EVR Is Not Used
15
Processing of the Power Supply Pins for Analog Cells
15
Oscillator Circuit Periphery
16
Clock Oscillator Circuit for 1 Clock/Digital Encoder System
16
Clock Oscillator Circuit for 2 Clock/Eck Master MCK PLL
17
Reset Circuit
20
Outline
20
Example Circuit and Timing Chart
20
Ics Requiring Reset after Power-On
21
EVR Connection
22
Integrated EVR and Reserved Channels (AGC Control)
22
Communication Control with an External EVR
24
Noise Countermeasures
26
Introduction
26
Countermeasures for Areas Around Individual Devices
27
If Noise Occurs
30
External LPF
31
Outline
31
High Resolution and LPF
31
Example Characteristics and Circuit for External BPF
31
BPF Circuit Example
31
Example BPF Characteristics
32
DAC Mode and YC-MIX External Analog Circuit
33
DAC Mode
33
Circuit Configuration for Component Output
34
Circuit Configuration for Composite Output
35
Optical Filters
36
Outline
36
4 Parameter Configuration
37
Communication Parameter Concept
37
Communication Category Concept
37
Communication Category Details
37
Parameter Control by Built-In CPU
38
Processing by CPU
38
CPU Main Processing and Firmware Applications
38
Parameter Changes through Communication
39
Saving Parameters to EEPROM
40
EEPROM Write Command and Address Map
40
EEPROM ALL WRITE" Command
41
5 Power-On Sequence
42
DSP (CXD3172AR) Initialization Sequence
42
Parameters Exclusively for Initialization
44
6 CCD Type Selection
45
Supported CCD Type
45
List of Clock Configurations for each CCD Type
46
Important Information on Wiring
47
Drive Circuit Changes
47
Clock System Changes
50
Frequency Response Changes
50
Clock System Selection
51
Wiring Changes When EEPROM Is Not Written
52
CCD Primary Color Separation Matrix
53
The Sequence of Parameter Changes
53
Recommended Parameter's Value
53
7 Power Supply
55
Supply Voltage
55
Supply Voltage Accuracy
55
Power Consumption
56
Power-On Sequence
56
8 Level Diagram
57
SS-HQ1 Level Diagram
57
Signal Standard Level Diagram of Analog Output
57
The Standard Level Diagram of Digital Outputs
61
9 RS-232C Communication and Communication with Peripheral Ics
63
RS-232C Communication
63
Interface
63
Communication Procedure
64
Communication Timing
65
Communication Format
66
Serial Communication Prohibited Period
68
Important Note Regarding Communication
68
When Communication Is Not Used
68
Communication with Peripheral Ics
69
Connection of Communication Bus between DSP (CXD3172AR) and Peripheral Ics
69
Pin Connections for Serial Communication with Individual Ics
69
Serial Communication Speed and Timing
70
Clock for Communication with Peripheral Ics
73
10 Description of Operation of each Function
77
Port Driver Function
77
Port Driver Function Description
77
Port Driver Setting Method
78
Parameter Setting Instructions
82
Field Processing for each Port Driver
85
Port Driver Initial Settings, Depending on Presence of EEPROM
85
Precautions for Port Driver Configuration
86
Port Driver Setting Example
87
Conditions for Disabling the Port Drivers
88
Y Signal Processing
89
Y (Luminance Signal) Processing Flow
89
Pre-Block Signal Processing
89
Y Signal Main Process
92
High Resolution Mode
95
Aperture Compensation Function
97
Chroma Signal Processing
99
Block Diagram
99
Complementary Color Pixel Clipping
100
Highlight Edge Color Compensation Function
101
Using Four-Quadrant Independent Control
102
False Color Suppress Function
104
Variable Gamma Function
105
Gamma Curve Types
105
Y Variable Gamma
107
Y Gamma off
108
Y Gamma Curve Compression in Low Luminance Areas (S Gamma)
109
Chroma Variable Gamma
110
Chroma Gamma off
112
Chroma Knee High Region Correction
112
Chroma Signal Knee Clipping Process
113
OPD Window Setting and Display
114
Detection Window Setting Method
114
Detection Window Screen Display
116
AE Operation
117
Sequence of Operation
117
Mode
118
Backlight Compensation
122
Flickerless Function
123
AE Hysteresis Function
124
AE Mechanical Iris Mode
126
ME Shutter Speed and AGC Gain Setting
128
Detailed Description (Relationship of Modes and Parameters)
129
WB Operation
132
Sequence of Operation
132
WB Operation
133
ATW Operation Range
137
ATW Related Parameters
138
Anti Color-Rolling Mode
145
Suppress
149
Chroma Suppress
149
Aperture Correction Suppress
151
Mirror Function
153
Mask Function
154
Setting Procedure
154
Important
156
11 Functions for Adjustment
157
Adjustment Operation Mode
157
The Kind of Modes
157
CCD Blemish Detection and Compensation
162
CCD Blemish Detection Method Types
162
Blemish Detection and Compensation Parameters
163
Static Detection and Compensation Function
164
Dynamic Detection and Compensation Function
171
False Blemish Generating Function
179
Adjustment of TG Phase
180
Adjustment Method of Phase and Drive Ability
180
12 Supporting Functions for Applications
185
Using Digital Output
185
Operation Modes with Digital Output
185
Digital Output Format
185
Digital Output Gain Setting
185
Ways to Use Digital Output
186
Parameter Settings for each Output Type
188
Itu-Rec656
189
Using External Synchronization
194
Synchronization for the SS-HQ1 System
194
Parameters Used to Set External Synchronization
195
Internal Mode (INT)
198
Line Lock Mode (LL)
201
Combined Use of INT and LL Modes in a Single System
205
VS Lock Mode (VSL)
216
Using the Internal SYNCSEP
218
VS Lock Mode (VSL-S)
219
VS Lock Mode (VSL-D)
221
VBS Lock Mode (VBSLHP)
223
VBS Lock Mode (VBSLHR)
226
Reset H Reset Mode (VRHR)
228
I/O Pin Initial Settings and Preventive Measures
230
Phase Adjustment Using the Shifter
231
Key Operations (Shifter)
233
AWB MODE and SFTUP/SFTDWN Assignments
233
Key Operations
233
External Synchronization Phase Adjustment through Key Operations
235
WB Gain Adjustment through Key Operations
236
When Using the External Microcomputer
237
External Microcomputer-SS-HQ1 System Interface
237
Communication Protocol with External Microcomputers
238
Pattern Generator (PG)
245
Pattern Generator (PG) Usage Method
245
Pattern Settings
246
Sync Signal Output Setting Method
250
ADJUST Output
252
ADJUST Function
252
13 Appendix
254
External Synchronization Evaluation Results
254
Operation Mode Control During Digital Output
254
Tables: the Parameters Controlled by FW
255
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