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JVC GR-DVA10 Technical Manual
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JVC GR-DVA10 Technical Manual

JVC GR-DVA10 Technical Manual

2000 basic dvc models
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VIDEO TECHNICAL GUIDE
DIGITAL VIDEO CAMERA
2000 Basic DVC Models
No. 86056
September 2000
COPYRIGHT © 2000 VICTOR COMPANY OF JAPAN, LTD.

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Summary of Contents for JVC GR-DVA10

  • Page 1 VIDEO TECHNICAL GUIDE DIGITAL VIDEO CAMERA 2000 Basic DVC Models No. 86056 September 2000 COPYRIGHT © 2000 VICTOR COMPANY OF JAPAN, LTD.

  • Page 2: Table Of Contents

    INDEX SECTION 1 OUTLINE OF THE PROCUCTS 1.1 COMPARSION TABLE OF DV MODELS SPECIFICATION BY PRODUCTS YEAR.....1-1 1.1.1 Comparison table of DV models specification by products year ........1-1 1.1.2 Specification of the DVC models..................1-3 SECTION 2 EXPLANATION OF ELECTRICAL CIRCUIT 2.1 CIRCUIT OUTLINE ......................2-1 2.1.1 Basic block diagram.......................2-1 2.2 CCD (ICX220AK/ICX221BK)....................2-2...
  • Page 3 SECTION 3 HEAD CLOG WARNING 3.1 HEAD CLOG WARNING OF DVC..................3-1 3.1.1 Structure of Sync Blocks and Error correction..............3-1 3.1.2 Error Rate of DVC......................3-3 3.1.3 Previous method of head clog detection ................3-4 3.1.4 New method of head clog detection ................3-5 SECTION 4 DOCTOR SYSTEM 4.1 WHAT IS DOCTOR PROGRAM? ..................4-1 4.1.1 Matching of Doctor Program with Microcomputer Program ..........4-1...

  • Page 4: Section 1 Outline Of The Procucts

    SECTION 1 OUTLINE OF THE PROCUCTS 1.1 COMPARSION TABLE OF DV MODELS SPECIFICATION BY PRODUCTS YEAR 1.1.1 Comparison table of DV models specification by products year (1/2) Model 1998 Fusion DV Model 1999 Fusion DV Model 2000 Fusion DV Model Function Battery BN-V11 Ni-Cd...
  • Page 5 • • • • Comparison table of DV models specification by products year (2/2) Model 1998 Fusion DV Model 1999 Fusion DV Model 2000 Fusion DV Model Function Slow motion Yes (Frame Advance) Yes (Frame Advance) RM-V712U RM-V711U (optional: GR-DVF11U) RM-V716U Video auto light Yes ( /No)

  • Page 6: Specification Of The Dvc Models

    SIGNAL DIGITAL MODEL STILL FORMAT MONI TERMINAL ZOOM OUTPUT GR-DVF10 NTSC 1/4" 680K 3.0 INCH IN/OUT 250 X GR-DVA10 NTSC 1/4" 680K COLOR 3.0 INCH IN/OUT 100 X GR-DVA11/K NTSC 1/4" 680K COLOR 3.0 INCH IN/OUT 100 X GR-DVL100U NTSC 1/4"...

  • Page 7: Circuit Outline

    SECTION 2 EXPLANATION OF ELECTRICAL CIRCUIT 2.1 CIRCUIT OUTLINE 2.1.1 Basic block diagram C C D M A I N M O N I T O R I C 4 3 0 2 I C 7 6 0 1 F I E L D M E M O R Y L C D M O N I...

  • Page 8: Ccd (Icx220Ak/Icx221Bk)

    2.2 CCD (ICX220AK/ICX221BK) This IC functions as an interline CCD (Charge Coupled Device = one of solid-state pickup devices). Since this CCD conforms to the SD mode of the DV standard, it has an optimum number of vertical pixels for the MPEG2 main level and it realizes a horizontal resolution of 450 TV lines.

  • Page 9: Ccd Image Sensor

    2.2.2 CCD Image Sensor Main difference in CCD adopted with DVC and VHS-C. 960H-type 1/4" C C D (w/ EIS area) for DVC ( G R - D V X 7 , G R - D V F 3 1 / D V L 4 0 , G R - D V L 3 0 0 e t c . ) N T S C : effective 630,000 (I m a g e 3 4 0,000) pixels PAL: effective 740,000 (Im a g e 4 0 0,000) pixels 33% EIS Area...
  • Page 10 1. Feature of CCD for this model This CCD adopts the drive frequency and the number of pixels conforming to the DVC format. The horizontal drive frequency is 18MHz based on 13.5MHz that is Y signal sampling frequency of the DVC format.
  • Page 11 2) Construction of internal lens Since the internal lens is constructed between the color filter and gobo, the light condensation efficiency is improved even for inclined incident light. On-chip On-chip microlens microlens Color filter Color filter Internal lens G o b o G o b o Poly Si Poly Si...

  • Page 12: Numbers Of Pixel For Main Models

    630,000 approx. 340,000 998H ˜ 677V 962H ˜ 654V 711H ˜ 485V GR-DVM70U /50U GR-DVA1 /F1 GR-DVF11 /21 /31U GR-DVA10 /F10 /A11 GR-DVL100 /200 /300U GR-DVL700 1/3” approx. 680,000 approx. 630,000 approx. 340,000 1002H ˜ 662V 962H ˜ 654V 720H ˜...

  • Page 13: Explanation Of Camera Circuit

    2.3 EXPLANATION OF CAMERA CIRCUIT 2.3.1 Present AW / AE control system The signal-processing block of the present camera system is composed as shown below (Fig. 2-3-1) L P F G C A A G C C C D G C A ∗3 ∗4 ∗5...
  • Page 14 1. AE (Auto Exposure) control The luminance level of camera output picture is controlled to always be proper exposure regardless of the brightness and illumination of the object. 1) AE input information • Average of luminance level divided a frame picture into 48 blocks passed through the LPF. •...
  • Page 15 3) AE control and output luminance signal level Gain-up mode: AUTO (OFF and AGC modes are the same as the VHS-C camcorder) L U M I N A N C E 100 IRE 50 IRE 0 IRE 5000 lux 300 lux 40-50 lux 10 lux B R I G H T...
  • Page 16 (1) When the intensity of illumination is high and iris aperture is stopped down, the iris is opened for compensating drop of the signal level by changing the shutter speed to high (1/250 sec). (2) Since raising the AGC gain deteriorates the S/N ratio, the E-E level is slightly lowered in the exposure compensation by controlling the AGC as compared with the iris control mode.
  • Page 17 2. AW (Auto White balance) control AW control compensates the Red component gain and Blue component gain shown in the camera block diagram to keep the white balance in the camera picture under every kind of light source. Basic input data for AW control are three of the following. (1) R, G, B levels of sections divided a picture into 48 sections.
  • Page 18 2) AWB control algorithm A W B c o n t r o l The upper and lower limits of each gain are set according to Light source judgment the ratio between R and B components and judgment of the (Gain limiter setting) light source by the infrared sensor.

  • Page 19: Af (Auto Focus) Control

    2.3.2 AF (Auto Focus) control 1. Auto Focus operation during slow shutter mode Though the basic Auto Focus operation is the same as usual, the interval of Auto Focus operation varies conforming to the timing of the picture data renewal when the camera is in the slow shutter mode. For example, in case the Gain-up mode is set to Auto, the shutter speed is changed to 1/30(2V) according to the illumination of the object.

  • Page 20: Eis (Electric Image Stabilizer) Control

    2.3.3 EIS (Electric Image Stabilizer) control The accurate compensation without picture quality deterioration is possible by using CCD with expansion area and correcting it two times. V R A M CDS / AGC / C C D I W D F M C A D C 1 8 M H z...

  • Page 21: Camera Dsp (Ic4301: Jcy0120) Function

    2.4 CAMERA SYSTEM IC'S FUNCTION 2.4.1 Camera DSP (IC4301: JCY0120) function 1. Camera DSP (IC4301: JCY0120) internal block diagram M C L K R A D F M W R W A D R A E 1 W A E 1 F L D D S C R A E 2 W A E 2 C L K D S C...
  • Page 22 2. Camera DSP (IC4301: JCY0120) pin functions (1/6) Pin No. Label In/Out Description VDMDA Vertical reference signal output for MDA PWM output CLK45 4.5MHz output Ground for Digital VDDE Power supply for Digital (I/O) CSYNCI HDANA VDANA ANACNT AY00 AY01 AY02 Not used AY03...
  • Page 23 • • • • Camera DSP (IC4301: JCY0120) pin functions (2/6) Pin No. Label In/Out Description DSYI3 DSYI4 DSYI5 Digital luminance signal input for DSC DSYI6 DSYI7 DSCI0 DSCI1 Digital color difference signal input for DSC DSCI2 DSCI3 DSCI4 DSCI5 Not used DSCI6 DSCI7...
  • Page 24 • • • • Camera DSP (IC4301: JCY0120) pin functions (3/6) Pin No. Label In/Out Description AVDDV1 Power supply for Analog video Not used AVSSE3 Ground for EVR VREFL3 Reference voltage input for bottom side VREFH3 Power supply for EVR AVDDE3 Power supply for EVR DVDDM...
  • Page 25 • • • • Camera DSP (IC4301: JCY0120) pin functions (4/6) Pin No. Label In/Out Description CSYNC Internal composite sync. Signal output ADDVSS Ground for add Digital DYO0 DYO1 Digital luminance signal output for DVC DYO2 DYO3 Ground for Digital VDDI Power supply for Digital (I/O, internal) DCO0...
  • Page 26 • • • • Camera DSP (IC4301: JCY0120) pin functions (5/6) Pin No. Label In/Out Description TMY4 TMY5 Digital luminance signal output for field memory TMY6 TMY7 TMC0 TMC1 Digital colon difference signal output for field memory TMC2 TMC3 ADDVDDE Power supply for add Digital (I/O) ADDVSS Ground for add Digital...
  • Page 27 • • • • Camera DSP (IC4301: JCY0120) pin functions (6/6) Pin No. Label In/Out Description ADDVDDE Power supply for add Digital (I/O) Read enable High address write enable Low address write enable Address latch enable BUS15 BUS14 BUS13 BUS12 BUS11 BUS10 BUS9...

  • Page 28: Explanation Of Deck Circuit

    2.5 EXPLANATION OF DECK CIRCUIT 2.5.1 Deck system overall structure The DVC deck system has such the IC construction as shown in Fig. 2-5-1. The DV-MAIN IC (IC3001) serves as the center IC of the deck system IC construction, and this system has been incorporated in the models of the GR-DVX7 and after.

  • Page 29: Pb Equalizer And Atf

    2.5.2 PB equalizer and ATF IC3201 D V _ E Q IC3301 D V _ A N A M A I N P B _ D A T A P B _ E N V A U T O A I N A D 1 P B O 1 + D V I T E R B I...

  • Page 30: Pll Operation

    2.5.3 PLL operation IC5501 X 5 5 0 1 V . D R V 5 4 M H z 8 1 M H z X 3 3 0 1 M A I N _ V C O IC3001 D V D S P A D J F R P 2 7 M H z...

  • Page 31: Basic Principle Of Viterbi Detection

    2.5.4 Basic principle of Viterbi detection Recording signal point A "1" Threshold level "0" signal Threshold level "-1" Usual detection "1" "0" "0" "1" "0" (Hard decision) E R R O R ! ! Viterbi decoder A / D converter -0.4 Select the most reliable line...

  • Page 32: Audio Recording Mode

    2.5.5 Audio recording mode There are four basic modes in the DVC audio mode as shown in Table 2-5-1, and it is recommended that the DVC can cover all of the four basic modes by the specifications. Mode Channel Sampling frequency Quantiazation 48K mode 48kHz...

  • Page 33: Audio Signal Processing

    The audio recording system of this model is as follows. In the 2-channel mode, quantiazation is linearly processed in a data unit of 16-bits and the sampling frequency is 48kHz. In regard to the recording pattern, the first 5 tracks (6 tracks in PAL) of 10 tracks (12 tracks in PAL) in a frame is used for CH1 recording and the second 5 tracks in a frame is used for CH2 recording.

  • Page 34: Clock System For Audio Data

    2.5.7 Clock system for audio data DOMCK (Master Clock) Sampling frequency DOMCK 48kHz 256fs: 12.288MHz 32kHz 384fs: 12.288MHz 48kHz 256fs: 12.288MHz PLAY 44.1kHz 256fs: 11.2896MHz 32kHz 256fs: 8.192MHz A. Dubbing 32kHz 256fs: 8.192MHz DOBCK (Serial Clock) Sampling frequency DOBCK 48kHz 36fs: 1.536MHz 32kHz 36fs: 1.024MHz...

  • Page 35: Deck Dsp Ic Function

    2.5.8 Deck DSP IC function 1. Deck DSP (IC3001: JCY0106-2) pin functions (1/6) Pin No. Label In/Out Description Power supply Ground PWMAUDO Audio PLL control signal, (To DVANA: IC3301) VDDS Power supply VCOAUDI PB audio b PLL input, (From DVANA: IC3301) VCOAUDO PB audio b PLL adjustment voltage output Ground...
  • Page 36 • • • • Deck DSP (IC3001: JCY0106-2) pin functions (2/6) Pin No. Label In/Out Description Not used YSO [0] YSO [1] DVC playback digital luminance signal output, (To CAMERA_DSP: IC4301) YSO [2] YSO [3] BRSO [0] BRSO [1] DVC playback digital color difference signal output, (To CAMERA_DSP: IC4301) BRSO [2] BRSO [3] Not used...
  • Page 37 • • • • Deck DSP (IC3001: JCY0106-2) pin functions (3/6) Pin No. Label In/Out Description Not used Power supply RAMWE Write enable output, (To 16M_DRAM: IC3002) RAMRAS Lower address strobe, (To 16M_DRAM: IC3002) RAMCAS [0] Address strobe (Lower bit), (To 16M_DRAM: IC3002) RAMCAS [1] Address strobe (Upper bit), (To 16M_DRAM: IC3002) RAMOE...
  • Page 38 • • • • Deck DSP (IC3001: JCY0106-2) pin functions (4/6) Pin No. Label In/Out Description CPUAD [5] CPUAD [6] In/Out Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401) CPUAD [7] Ground Not used CPUAD [8] CPUAD [9] In/Out Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401) CPUAD [10] CPUAD [11] VDDS...
  • Page 39 • • • • Deck DSP (IC3001: JCY0106-2) pin functions (5/6) Pin No. Label In/Out Description TESTIO [22] Open (Not used) TESTIO [23] Power supply Not used SCANENABLE L: Fixed (Not used) SCANMODE TRST Reset signal input for boundary scan H: Fixed (Not used) L: Fixed (Not used) H: Fixed (Not used)
  • Page 40 • • • • Deck DSP (IC3001: JCY0106-2) pin functions (6/6) Pin No. Label In/Out Description PWM405O 40.5MHz (PLL control output) 1/2 frequency of VCO405I, (To DVANA: IC3301) VDDS Power supply VCO405I 81MHz VCO reference clock input, (From DVANA: IC3301) VCO405O Open (Not used) Ground...

  • Page 41: Audio Amp Ic Function

    2.5.9 Audio AMP IC function 1. Audio AMP (IC2201: AK4560VQ) pin locations and block diagram H P F E Q _ N _ R Control O F F Clock Register Divider I N T P R E _ O _ R D A T A E X T P R E _ N _ R...
  • Page 42 2. Audio AMP (IC2201: AK4560VQ) pin functions (1/2) Pin No. Label In/Out Description EQ_P_L L-ch EQ-Amp positive input EQ_O_L L-ch EQ-Amp output HPF_P_L L-ch HPF-Amp positive input HPF_O_L L-ch HPF output MIC_IN_L L-ch MIC input VCOM (1.5V) Common voltage output, (1/2VA) VREF (1.5V) ADC, DAC reference level, (1/2VA) GND (VA)
  • Page 43 • • • • Audio AMP (IC2201: AK4560VQ) pin functions (2/2) Pin No. Label In/Out Description CCLK Control clock input BCLK Audio serial data clock LRCK Input/Output channel clock MCLK Master clock input Power down & reset, (L: Power- down & reset, H: Normal operation) SPK+ Speaker Amp positive output Noise decrease (L: Disable, H: Enable)

  • Page 44: Syscon Cpu

    2.6 SYSCON CPU 2.6.1 Contents of SYSCON CPU processing 1) User I/F control • Recognition of Operation Keys and Menu • Holding the User Configurations 2) Camera signal process control • TG/CDS IC • Camera DSP IC (Y/C Process, Special Effect, Encoder, OSD Mix, EVR etc.) 3) Camera Auto system control •...

  • Page 45: System Composition

    2.6.3 System composition SYSCON CPU adopted with this model has five data communication systems and communicates with each peripheral device using those ports. There are three synchronous serial communication systems; one of these is used only for the model having DSC function. The communication with the Camera DSP is required a high-speed performance for transferring the information and command of camera auto processing.

  • Page 46: Syscon Cpu Block Diagram

    2.6.4 SYSCON CPU block diagram I C 1 0 0 1 S Y S C O N C P U I C 7 6 0 1 I C 7 6 0 3 EDIT_CTL 118 L C D E E P J L I P JLIP_L 93 D R V...

  • Page 47: Syscon Cpu (Ic1001: Mn1021617Hl) Pin Functions

    2.6.5 SYSCON CPU (IC1001: MN1021617HL) pin functions (1/3) Pin No. Label In/Out Description EL_CTL Strobe emission control (To EL driver: IC756) LAMP_ON Video light ON/OFF BUS0 BUS1 In/Out Address/Data MPX BUS 16bits (From/To CAMERA_DSP: IC4301) BUS2 BUS3 Power supply BUS4 BUS5 BUS6 In/Out...
  • Page 48 • • • • SYSCON CPU (IC1001: MN1021617HL) pin functions (2/3) Pin No. Label In/Out Description RTC_INT Clock 1 sec. Interrupt AV_DET AV plug connection detect signal input VF_MONI VF/MONI select signal LCD_LOAD LCD data load pulse VF_CTL VF_REG4.8V ON/OFF control EEPROM_CS Chip select signal (To EEPROM: IC1003) Power supply...
  • Page 49 • • • • SYSCON CPU (IC1001: MN1021617HL) pin functions (3/3) Pin No. Label In/Out Description AVDD Power supply DSC_PCTL Power control (To DSC_IF: IC8001) SRV_RST Reset signal (To DECK_CPU: IC1401) OEM_REG5_CTL Not used MENU_SET_SW Menu set switch input RTC_CS Chip select signal (To RTC: IC1004) JLIP_L PC connection terminal switch (L: JLIP terminal, H: PC terminal)

  • Page 50: Deck Cpu

    2.7 DECK CPU 2.7.1 Contents of DECK CPU processing 1) Mechanism control • Loading motor control • Drum motor control • Capstan motor control 2) Deck LSI control • DV DSP IC control • PRE / REC IC control 3) OSD control •...

  • Page 51: Tracking Error Information

    2.7.3 Tracking Error information Flame Pulse Track Pulse (Track reference ( 9 ) ( 0 ) ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 9 ) ( 0 ) ( 1 )

  • Page 52: 1394 Interface Control

    2.7.4 1394 interface control The DECK CPU has the function of the host microcomputer of the 1394 interface. It mainly controls the LINK IC, PHY IC and 1394 bus besides AV/C command processing. The AV/C command is classified into the VCR control commands such as for PLAY, STOP, FF, REW, REC operations and for status information such as time code, mode status, etc.

  • Page 53: Deck Cpu Block Diagram

    2.7.6 DECK CPU block diagram I C 1 4 0 1 D E C K C P U I C 5 5 0 1 I C 3 1 0 1 PHY_RST 61 72 OSCI PHY_PD 3 1 3 9 4 V .

  • Page 54: Deck Cpu (Ic1401: Mn103004Krh) Pin Functions

    2.7.7 Deck CPU (IC1401: MN103004KRH) pin functions (1/5) Description Pin No. Label In/Out CAP_BRK Capstan motor brake control LD_ON Loading motor ON/OFF control ANA_CS Chip select signal (To DV_ANA: IC3301) OSD_CS Chip select signal (To OSD: IC1002) MIC_CTL Power supply control to MIC PHY_PD Power down control (To PHY: IC3101) PHY_RST...
  • Page 55 • • • • Deck CPU (IC1401: MN103004KRH) pin functions (2/5) Description Pin No. Label In/Out VDDB Power supply (REG_3V) DK(L) Servo CPU ready signal (Low: Deck mode) RE(L) Read enable signal WE1(L) Test terminal (TL1401) WE0(L) Write enable signal PVDD Power supply (REG_3V) PVSS...
  • Page 56 • • • • Deck CPU (IC1401: MN103004KRH) pin functions (3/5) Description Pin No. Label In/Out Not used BCID3 Cassette tape ID board information BCID2 BCID1 DEW_SENS Dew sensor detect E_SENS End sensor detect S_SENS Start sensor detect VREFH Reference voltage AVDD Power supply (REG_3V) ADTRG(L)
  • Page 57 • • • • Deck CPU (IC1401: MN103004KRH) pin functions (4/5) Description Pin No. Label In/Out Not used VDDH Power supply (REG_3V) Head switch pulse output Not used Not used DRUM_REF Drum offset voltage output (To MDA: IC1601) CAP_REF Capstan offset voltage output (To MDA: IC1601) Not used HID reference (Drum 150Hz reference) Frame pulse (From DECK_DSP: IC3001)
  • Page 58 • • • • Deck CPU (IC1401: MN103004KRH) pin functions (5/5) Description Pin No. Label In/Out Not used VDDH Power supply (REG_3V) Not used Power supply (REG_3V) BR(L) H: fixed ANA_CLK Serial clock (To DV_ANA: IC3301) ANA_IN Serial data bus output (To DV_ANA: IC3301) ANA_OUT Serial data bus input (From DV_ANA: IC3301) MDA_CLK...

  • Page 59: Head Clog Warning Of Dvc

    SECTION 3 HEAD CLOG WARNING 3.1 HEAD CLOG WARNING OF DVC The method and criterion of DVC head clog detection have been changed from this DVC series. Differently from the previous models which detect head clog in the recording mode only, the new system incorporated in this series detects head clog in both the recording and playback modes based on the new detection criterion that is much more strict with possible error as compared with the previous system.
  • Page 60 Sync Block length : 90 Byte Sync block Byte-position number n u m b e r 0 1 2 3 4 5 Pre-sync block (2) VIDEO AUX (VAUX) VIDEO DATA Data-sync block Inner (149) Code Parity VIDEO AUX (VAUX) 1 5 6 1 5 7 Outer Parity 1 6 7...

  • Page 61: Error Rate Of Dvc

    3.1.2 Error Rate of DVC The error rate of the DVC is shown by the average number of error corrections by the inner parity in the AUDIO/VIDEO sector (A/V inner errors) per 1 second (300 tracks). Error correction is carried out by the ECC inside the DV-DSP IC, and the ECC outputs Error Flag SBE (Sync Block Error).

  • Page 62: Previous Method Of Head Clog Detection

    3.1.3 Previous method of head clog detection The previous head clog detection system (for the models of GR-DVL9800 and before) is based on the count of sync blocks as the criterion. The count of sync blocks that a head plays back per frame is: NTSC: ( Audio 17 + Video 152 ) ×...

  • Page 63: New Method Of Head Clog Detection

    3.1.4 New method of head clog detection The new head clog detection system (for this DVC series and after) performs detection in the normal (usual) playback mode besides the short-playback mode just after resuming of recording as well as the previous system.
  • Page 64 New method Previous method (GR-DVL300 series) (GR-DVL9800 and before) During Normal PB and Short PB During Short PB Detection period at recording start at recording start The number of Sink block counts The value of A/V inner error par 1 frame Judgment element par 1 frame Normal PB...

  • Page 65: What Is Doctor Program?

    SECTION 4 DOCTOR SYSTEM 4.1 WHAT IS DOCTOR PROGRAM? The function and performance of a product (an electric/electronic appliance in this case) generally depends on the program of the internal microcomputer. If there is some fault in the electrical function and performance of a product, the program of its microcomputer should be changed (upgraded) at the expenses of the manufacturer.

  • Page 66: Use Of Doctor Program For Camcorder

    4.1.2 Use of Doctor Program for Camcorder Doctor Programs have been widely used for stationary video decks, however, the function of the Doctor Program is an obstacle to repair of the product, namely, it occasionally brings about secondary troubles if the program data stored in the EEPROM mismatches the microcomputer program as mentioned previously.

  • Page 67: Procedure To Rewrite Doctor Program

    1. Specification of Doctor Program area If there is a Doctor Program area in the EEPROM data, the area is specified by coloring (gray) the cell on the EEPROM utility map. 2. Deletion of Data Editing Function in Doctor Program Area To avoid trouble caused by data editing in the Doctor Program area, data editing is disabled for the colored cell (Doctor Program area).
  • Page 68 2. Data Deletion from Doctor Program Area Only If the microcomputer is replaced, it occasionally needs to delete the Doctor Program stored in the EEPROM. Although the service support system software has no data deletion function like the emergency utility, the Doctor Program can be deleted by the "Doctor Load" function. 1.

  • Page 69: Doctor Program System In The Present Circumstances

    4.2 DOCTOR PROGRAM SYSTEM IN THE PRESENT CIRCUMSTANCES Though it explained about the outline of the Doctor Program and the doctor complying with of the service support system software in the preceding clause, it explains here about the present circumstances of the Doctor Program system.
  • Page 70 As mentioning above, it is unacceptable by using the service support system software to edit the doctor area directly at the time of the repair. However, when writing of the initial data or the backup data is done, the doctor area is also rewritten at the same time. Also, it is possible to turn off or renew the Doctor Program by using the "Doctor Load"...

  • Page 71: Writing Function Of Eeprom Data

    4.2.2 Writing function of EEPROM data The writing function of the previous service support system software (before complying with the doctor system) was the method which data are written in one after another as the turn of the address. If the ON/OFF address is younger than the Program address, the data renewal process becomes the following.
  • Page 72 1C6h VMD2/VMD3 1C7h GR-DVL700 6F0h GR-DVL9800U GR-DVL9800EG/DVL9800EK 6F1h GR-DVL9700EG/DVL9700EK 600h to 61Bh VMD10/VMD20 6F2h 6F3h GR-DVA10/DVF10 series 1ACh GR-DVL300U/DVL300UM series GR-DVL300KR/DVL805KR series 1ADh GR-DVL300EG/DVL300EK series DAh to DFh GR-DVL300A/DVL300A-S series 2A4h to 2D6h 1AEh GR-DVL300EA/DVL300ED series CC9370 1AFh Table 4-2-3 Address list of the doctor program area...
  • Page 73 VICTOR COMPANY OF JAPAN, LIMITED Printed in Japan 2000-09 (TM1)

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