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CDJ-500G, CDJ-500
1.8 TROUBLESHOOTING
@ How to Check Operation
of the DSP IC
(1C302:,.PD6383GF)
(1) Checking the system clock frequency
Make sure that the clock frequency is 24.576 MHz
(+5%) at XO (pin No.40).
(2
~~
Checking data transfer of DSP internal initialization
In order to operate the DSP, the initialize data (DSP in-
ternal registers and operation program) must be trans-
ferred from the system control microcomputer (IC701
'PD4543A).
After turning the power on, make sure that RST (pin
No.9) becomes High (5V), and that the clock pulse and
data are input for about 150 ms to SCK (pin No.3) and SI
(pin No.4).
1:
2: SCK
5V/div, 50m sec/div
3: SI
5V/div, 50m sec/div
3
~~
Checking the DSP operation control terminal
Make sure that a High signal (5V) is being input to RQ]
(pin No.86) and RQ2 (pin No.87) during operation of the
player.
(4
~~
Checking the digital audio I/O terminal
Make sure that the bit clock, data and LR clock are being
input to BCLKI (pin No.17), DI1 (pin No.20) and
LRCKI (pin No.18) during operation of the player.
Likewise, make sure that the bit clock, data and LR clock
are being output to BCLKO
(pin No.26), DOI (pin
No.23) and LRCKO (pin No.27).
1-34
1: BCLKI
5V/div, 20, sec/div
2: Dil
5V/div, 20 sec/div
3: LRCKI
5V/div, 20u sec/div
eee
eee
1: BCLKO
5V/div, 20u sec/div
2: DOI
5V/div, 20u sec/div
3: LRCKO
5V/div, 20u sec/div
(5) DSP peripheral circuit block diagram
1C303, 304
DRAM
MS514256A
OZC
X302
24.576MHz
1C301
U
DECORDER
DSP
DIGITAL FILTER
cxD25008Q.
~FRA———)_
uPDesa3GF
SM5841CP
Digital Audio
Digital Audio
signal
signal
Transfer of initial DSP data
iC701
|and operation control
CPU
PD4543A
@ Disengaging The Control Panel
1.
Turn on the power and press the Eject button to open the
door (note 1),
2.
Unplug
the power cord.
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