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Asus AAEON VPC-5600S User Manual
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Asus AAEON VPC-5600S User Manual

Asus AAEON VPC-5600S User Manual

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VPC-5600S
Mobile NVR
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User's Manual 11
Ed
Last Updated: August 15, 2023

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Summary of Contents for Asus AAEON VPC-5600S

  • Page 1 VPC-5600S Mobile NVR User’s Manual 11 Last Updated: August 15, 2023...
  • Page 2 Copyright Notice This document is copyrighted, 2023. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of the original manufacturer.
  • Page 3 Acknowledgements All other products’ name or trademarks are properties of their respective owners. Microsoft Windows® is a registered trademark of Microsoft Corp. ⚫ Intel® is a registered trademark of Intel Corporation ⚫ Intel® Core™ is a trademark of Intel Corporation ⚫...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity VPC-5600S ⚫ Wall Mount Bracket ⚫ SATA Cable ⚫ SATA Power Cable ⚫ If any of these items are missing or damaged, please contact your distributor or sales representative immediately.
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document.
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. All cables and adapters supplied by AAEON are certified and in accordance with the material safety laws and regulations of the country of sale.
  • Page 7 As most electronic components are sensitive to static electrical charge, be sure to ground yourself to prevent static charge when installing the internal components. Use a grounding wrist strap and contain all electronic components in any static-shielded containers. If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii.
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON System QO4-381 Rev.A0 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 × ○ ○ ○ ○ ○ 及其电子组件 外部信号 × ○ ○ ○ ○ ○ 连接器及线材 外壳 ○...
  • Page 10 China RoHS Requirement (EN) Hazardous and Toxic Materials List AAEON System QO4-381 Rev.A0 Hazardous or Toxic Materials or Elements Component Name PCB and Components Wires & Connectors for Ext.Connections Chassis CPU & RAM HDD Drive LCD Module Optical Drive Touch Control Module Battery This form is prepared in compliance with the provisions of SJ/T 11364.

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Chapter 2 – Hardware Information ..................4 Dimensions ....................... 5 Jumpers and Connectors ..................9 List of Jumpers ......................11 2.3.1 Clear CMOS (CN10) ..................11 2.3.2 ATX/AT Selection (CN14) ................11 2.3.3 COM 1 Ring/+5V/+12V Selection (CN15) ..........
  • Page 12 AMI BIOS Setup ..................... 33 Setup Submenu: Main ..................34 Setup Submenu: Advanced ................. 35 3.4.1 CPU Configuration ..................36 3.4.2 PCH-FW Configuration ................37 3.4.3 SATA Configuration ................... 38 3.4.4 Trusted Computing ..................39 3.4.5 Hardware Monitor ..................40 3.4.6 SIO Configuration ..................41 3.4.6.1...
  • Page 13 Appendix B - I/O Information ....................66 I/O Address Map ....................67 IRQ Mapping Chart ....................68 Appendix C – Digital I/O Ports ..................... 69 Digital I/O Programming ..................70 Digital I/O Register ....................71 Digital I/O Sample Program ................72 Preface XIII...

  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 15: Specifications

    Specifications System Form Factor In-Vehicle NVR Processor 7th Generation Intel® Core™ i3-7100U Processor Chipset — Main Memory 260-pin DDR4 SODIMM, up to 32GB Display HDMI x 1 DP x 1 Ethernet LAN x 2 + PoE x 4 (RTL8111E 10/100/1000 Base) PoE Ethernet Port PoE x 4 sharing 60W Power Budget RAID support...
  • Page 16 System Rear I/O Panel (Cont.) RS-232/422/485 x 2 HDMI x 1 CanBus Connector x 1 Audio Line-out x 1, Mic-In x 1 SIM Slot x 2 Storage HDD Tray 2.5” SATA SSD x 2 CF/CFast/mSATA Slot mSATA Slot x 1 (Optional: if mSATA slot is in use, only 1 SATA slot is available) Envrionmental Operating Temperature...

  • Page 17: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 18: Dimensions

    Dimensions Chassis Chapter 2 – Hardware Information...
  • Page 19 Chapter 2 – Hardware Information...
  • Page 20 Board Component side 164.4 163.12 162.14 146.19 160.6 153.75 106.9 98.85 74.25 65.85 41.25 18.7 11.87 6.01 10.8 7.16 Chapter 2 – Hardware Information...
  • Page 21 Solder side 140.5 140.5 132.5 132.5 107.58 106.9 77.58 74.65 41.65 47.58 37.5 37.5 29.5 29.5 Chapter 2 – Hardware Information...

  • Page 22: Jumpers And Connectors

    Jumpers and Connectors Component side SATA1 SATA2 CN10 SLOT1 DIM M 1 SLOT2 CN11 CN16 CN18 Chapter 2 – Hardware Information...
  • Page 23 Solder side M SATA1 DIM M 2 SLOT3 CN23 Chapter 2 – Hardware Information...

  • Page 24: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Label Function CN10 Clear CMOS CN14 ATX/AT Selection CN15 COM 1 Ring/+5V/+12V Selection CN16 CANBus UART/USB Selection CN18 CANBus Program Firmware 2.3.1 Clear CMOS (CN10)

  • Page 25: Com 1 Ring/+5V/+12V Selection (Cn15)

    2.3.3 COM 1 Ring/+5V/+12V Selection (CN15) Function Pin Selection Ring (Default) +12V 2.3.4 CANBus UART/USB Selection (CN16) Function Pin Selection UART USB (Default) 2.3.5 CANBus Program Firmware (CN18) Function Pin Selection Protected (Default) Program Chapter 2 – Hardware Information...

  • Page 26: List Of Connectors

    List of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function AUDIO1 Audio Connector USB 3.2 Gen 1 (3 ~ 4) + LAN 2 USB 3.2 Gen 1 (1 ~ 2) + LAN 1 Board to Board Connector LAN 3 ~ LAN 6 (With PoE Function) Front Panel Connector...
  • Page 27 Label Function LED4 SATA LED MSATA1 mSATA Connector (Optional) SATA1 Primary SATA Connector SATA2 Secondary SATA Connector SLOT1 Half Size Mini Card Connector (USB only) SLOT2 Full Size Mini Card Connector (PCIe + USB) SLOT3 Full Size Mini Card Connector (USB only) Power Button Software Reset Power On/Off Delay Select...

  • Page 28: Board To Board Connector (Cn3)

    2.4.1 Board to Board Connector (CN3) Signal Signal PCH_I2C1SCL PSE1_AOUT PCH_I2C1SDA PSE1_INT +3.3VDUAL +3.3VDUAL +V3P3S +V5S ASM3_TN PLTRST#_BUF ASM3_TP LPC_SERIRQ Chapter 2 – Hardware Information...

  • Page 29: Front Panel Connector (Cn5)

    Signal Signal ASM3_RN LPC_AD3 ASM3_RP LPC_AD2 LPC_AD1 ASM3_REFCLKN LPC_AD0 ASM3_REFCLKP LPC_FRAME# SIO_CLKIN 2.4.2 Front Panel Connector (CN5) Signal Signal PWR_SW# FPANSWH# HWRST# FPANSWH# 2.4.3 Power In & Remote Button (CN19) Signal Signal PWR_IN GND_PRI REMOTE_SW PS_ON# Chapter 2 – Hardware Information...

  • Page 30: Digital I/O Connector (Cn20)

    2.4.4 Digital I/O Connector (CN20) Signal Signal +GP_V GPI0 GPO0 GPI1 GPO1 GPI2 GPO2 GPI3 GPO3 Mating Connector: 16522X0003 (Dinkle EC350VM-05P). 2.4.5 CAN Bus 2.0B Connector (CN22) Signal Signal CAN DATA + CAN DATA- Chapter 2 – Hardware Information...

  • Page 31: Com 4 Rs-232 Serial Port Connector (Com1)

    2.4.6 COM 4 RS-232 Serial Port Connector (COM1) Signal Signal 2.4.7 COM 3 RS-232 Serial Port Connector (COM2) Signal Signal 2.4.8 COM1 & COM2 RS-232/422/485 Connector (COM3) Signal Signal DCD (RS485 Data-/RS422 TX-) RXD (RS485 Data+/RS422 RX-) TXD (RS422 RX+) DTR (RS422 RX-) Chapter 2 –...

  • Page 32: Power On/Off Delay Select (Sw3)

    2.4.9 Power On/Off Delay Select (SW3) Power On Delay Time Power Off Delay Time Switch Pin (Sec) (Sec) Number 1800 Control Table Null 2 Days Null Null Null Null Null Null Chapter 2 – Hardware Information...

  • Page 33: 2.5 2.5" Drive Installation

    2.5 2.5” Drive Installation Step 1: Loosen the screws and remove the bottom cover. Step 2: Attach the brackets to the 2.5” drives. Brackets support up to two drives. Chapter 2 – Hardware Information...
  • Page 34 Step 3: Install the drive assembly onto the bottom cover. Step 4: Attach the cables to the motherboard. Step 5: Replace the bottom cover and tighten the screws. Chapter 2 – Hardware Information...

  • Page 35: 2.6 Msata Drive Installation

    2.6 mSATA Drive Installation Step 1: Loosen the screws and remove the bottom cover Chapter 2 – Hardware Information...
  • Page 36 Step 2: Remove the screws from the following six (6) locations. Chapter 2 – Hardware Information...
  • Page 37 Step 3: Remove the top cover. Chapter 2 – Hardware Information...
  • Page 38 Step 4: Install the mSATA drive onto the motherboard and tighten the screw. Step 5: Replace the top cover and tighten the screws. Step 6: Replace the bottom cover and tighten the screws. Chapter 2 – Hardware Information...

  • Page 39: Gps & Ram Installation

    GPS & RAM Installation Step 1: Loosen the screws and remove the bottom cover Chapter 2 – Hardware Information...
  • Page 40 Step 2: Remove the screws from the following six (6) locations. Chapter 2 – Hardware Information...
  • Page 41 Step 3: Remove the top cover. Chapter 2 – Hardware Information...
  • Page 42 Step 4: Install the GPS cable and Wi-Fi antenna connector. Chapter 2 – Hardware Information...
  • Page 43 Step 5: Install the RAM and thermal pad. Chapter 2 – Hardware Information...

  • Page 44: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 45: System Test And Initialization

    System Test and Initialization The system uses certain routines to perform testing and initialization during the boot up sequence. If an error, fatal or non-fatal, is encountered, the system will output a few short beeps or an error message. The board can usually continue the boot up sequence with non-fatal errors.

  • Page 46: Ami Bios Setup

    AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press <Del>...

  • Page 47: Setup Submenu: Main

    Setup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 48: Setup Submenu: Advanced

    Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 49: Cpu Configuration

    3.4.1 CPU Configuration Options Summary Active Processor Cores Number of cores to enable in each processor package. Hyper-Threading Disabled Enabled Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and Disabled for other OS (OS not optimized for Hyper-Threading Technology). Chapter 3 –...

  • Page 50: Pch-Fw Configuration

    3.4.2 PCH-FW Configuration Options Summary ME FW Image Re-Flash Disabled Enabled Enable/Disable Me FW Image Re-Flash function. Chapter 3 – AMI BIOS Setup...

  • Page 51: Sata Configuration

    3.4.3 SATA Configuration Options Summary SATA Controller(s) Disabled Enabled Enable/Disable SATA Device. Hot Plug Disabled Enabled Designates this port as Hot Pluggable. Chapter 3 – AMI BIOS Setup...

  • Page 52: Trusted Computing

    3.4.4 Trusted Computing Options Summary Security Device Support Disabled Enabled Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. TPM State Disabled Enabled Enable/Disable Security Device. NOTE: Your Computer will reboot during restart in order to change State of the Device.

  • Page 53: Hardware Monitor

    Options Summary TPM 1.2 will restrict support to TPM 1.2 devices. TPM 2.0 will restrict support to TPM 2.0 devices. Auto will support both with the default set to TPM 2.0 devices if not found. TPM 1.2 devices will be enumerated. 3.4.5 Hardware Monitor Chapter 3 –...

  • Page 54: Sio Configuration

    3.4.6 SIO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 55: Serial Port Configuration

    3.4.6.1 Serial Port Configuration Chapter 3 – AMI BIOS Setup...

  • Page 56: Serial Port 1 Configuration

    3.4.6.2 Serial Port 1 Configuration Options Summary Use This Device Disabled Enabled Enable or Disable this Logical Device. Possible: Use Automatic Settings IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 57: Serial Port 2 Configuration

    3.4.6.3 Serial Port 2 Configuration Options Summary Use This Device Disabled Enabled Enable or Disable this Logical Device. Possible: Use Automatic Settings IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 58: Serial Port 3 Configuration

    3.4.6.4 Serial Port 3 Configuration Options Summary Use This Device Disabled Enabled Enable or Disable this Logical Device. Possible: Use Automatic Settings IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 59: Serial Port 4 Configuration

    3.4.6.5 Serial Port 4 Configuration Options Summary Use This Device Disabled Enabled Enable or Disable this Logical Device. Possible: Use Automatic Settings IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 60: Serial Port 5 Configuration

    3.4.6.6 Serial Port 5 Configuration Options Summary Use This Device Disabled Enabled Enable or Disable this Logical Device. Possible: Use Automatic Settings IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 61: Serial Port 6 Configuration

    3.4.6.7 Serial Port 6 Configuration Options Summary Use This Device Disabled Enabled Enable or Disable this Logical Device. Possible: Use Automatic Settings IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 62: Digital Io Port Configuration

    3.4.7 Digital IO Port Configuration Options Summary DIO Port5~8 Output Input Set DIO as Input or Output. Output Level High Set output level when DIO pin is output. Chapter 3 – AMI BIOS Setup...

  • Page 63: Power Management

    3.4.8 Power Management Options Summary Power Mode ATX Type AT Type Select Power Supply Mode. Restore AC Power Loss Power Off Power On Last State Select AC power state when power is re-applied after a power failure. Chapter 3 – AMI BIOS Setup...

  • Page 64: Setup Submenu: Chipset

    Setup Submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 65: System Agent (Sa) Configuration

    3.5.1 System Agent (SA) Configuration Chapter 3 – AMI BIOS Setup...

  • Page 66: Graphics Configuration

    3.5.1.1 Graphics Configuration Options Summary VT-d Enabled Disabled VT-d capability. Primary Display Auto IGFX Select which of IGFX/PEG/PCI Graphics device should be Primary Display Or select SG for Switchable Gfx. Primary IGFX Boot Display VBIOS Default HDMI Select the Video Device which will be activated during POST. This has no effect if external graphics present.

  • Page 67: Setup Submenu: Security

    Setup Submenu: Security Change User/Administrator Password You can set an Administrator Password or User Password. An Administrator Password must be set before you can set a User Password. The password will be required during boot up, or when the user enters the Setup utility. A User Password does not provide access to many of the features in the Setup utility.

  • Page 68: Setup Submenu: Boot

    Setup Submenu: Boot Options Summary Quiet Boot Disabled Enabled Enables or disables Quiet Boot option. Launch PXE ROM Disabled Enabled Controls the execution of UEFI and Legacy PXE OpROM Chapter 3 – AMI BIOS Setup...

  • Page 69: Setup Submenu: Save & Exit

    Setup Submenu: Save & Exit Chapter 3 – AMI BIOS Setup...

  • Page 70: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 71: Driver Download And Installation

    Driver Download and Installation Drivers for the VPC-5600S can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/in-vehicle-nvr-vpc-5600s Download the driver(s) you need and follow the steps below to install them. Install Chipset Drivers Open the Chipset folder followed by SetupChipset.exe Follow the instructions Drivers will be installed automatically...
  • Page 72 Install Audio Driver Open the Audio folder and select your OS Open the .exe file in the folder Follow the instructions Drivers will be installed automatically Install USB 3.0 Driver Open the USB3.0 folder and select your OS Open the .exe file in the folder Follow the instructions Drivers will be installed automatically Install ME Driver...

  • Page 73: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...

  • Page 74: Watchdog Timer Initial Program

    Watchdog Timer Initial Program Table 1: SuperIO Relative Register Table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2: Watchdog Relative Register Table Register BitNum Value...
  • Page 75 ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Watch Dog relative definition (Please reference to Table 2) #define byte TimerLDN //This parameter is represented from Note3 #define byte TimerReg //This parameter is represented from Note4 #define byte TimerVal // This parameter is represented from Note24...
  • Page 76 ************************************************************************************ VOID Main(){ // Procedure : AaeonWDTConfig // (byte)Timer : Time of WDT timer.(0x00~0xFF) // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. AaeonWDTEnable(); ************************************************************************************ Appendix A – Watchdog Timer Programming...
  • Page 77 ************************************************************************************ // Procedure : AaeonWDTEnable VOID AaeonWDTEnable (){ WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 1); // Procedure : AaeonWDTConfig VOID AaeonWDTConfig (){ // Disable WDT counting WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 0); // Clear Watchdog Timeout Status WDTClearTimeoutStatus(); // WDT relative parameter setting WDTParameterSetting(); VOID WDTEnableDisable(byte LDN, byte Register, byte BitNum, byte Value){ SIOBitSet(LDN, Register, BitNum, Value);...
  • Page 78 ************************************************************************************ VOID SIOEnterMBPnPMode(){ Switch(SIOIndex){ Case 0x2E: IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x01); IOWriteByte(SIOIndex, 0x55); IOWriteByte(SIOIndex, 0x55); Break; Case 0x4E: IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x01); IOWriteByte(SIOIndex, 0x55); IOWriteByte(SIOIndex, 0xAA); Break; VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0x02); IOWriteByte(SIOData, 0x02); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN);...

  • Page 79: Appendix B - I/O Information

    Appendix B Appendix B - I/O Information...

  • Page 80: I/O Address Map

    I/O Address Map Appendix B – I/O Information...

  • Page 81: Irq Mapping Chart

    IRQ Mapping Chart Appendix B – I/O Information...

  • Page 82: Appendix C - Digital I/O Ports

    Appendix C Appendix C – Digital I/O Ports...

  • Page 83: Digital I/O Programming

    Digital I/O Programming VPC-5600S utilizes FINTEK F81866 chipset as its Digital I/O controller. Below are the procedures to complete its configuration. AAEON initial DI/O program is also attached for developing customized program for your application. There are three steps to complete the configuration setup: (1) Enter the MB PnP Mode (2) Modify the data of configuration registers (3) Exit the MB PnP Mode.

  • Page 84: Digital I/O Register

    Digital I/O Register Table 1: SuperIO Relative Register Table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2: Digital Input Relative Register Table Register BitNum Value...

  • Page 85: Digital I/O Sample Program

    Digital I/O Sample Program ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Digital Input Status relative definition (Please reference to Table 2) #define byte DInput1LDN // This parameter is represented from Note3 #define byte DInput1Reg // This parameter is represented from Note4...
  • Page 86 ************************************************************************************ // Digital Output control relative definition (Please reference to Table 3) #define byte DOutput1LDN // This parameter is represented from Note27 #define byte DOutput1Reg // This parameter is represented from Note28 #define byte DOutput1Bit // This parameter is represented from Note29 #define byte DOutput1Val // This parameter is represented from Note30 #define byte DOutput2LDN // This parameter is represented from Note31 #define byte DOutput2Reg // This parameter is represented from Note32...
  • Page 87 ************************************************************************************ VOID Main(){ Boolean PinStatus ; // Procedure : AaeonReadPinStatus // Input : Example, Read Digital I/O Pin 3 status // Output : InputStatus : 0: Digital I/O Pin level is low 1: Digital I/O Pin level is High PinStatus = AaeonReadPinStatus(DInput3LDN, DInput3Reg, DInput3Bit); // Procedure : AaeonSetOutputLevel // Input : Example, Set Digital I/O Pin 6 level...
  • Page 88 ************************************************************************************ Boolean AaeonReadPinStatus(byte LDN, byte Register, byte BitNum){ Boolean PinStatus ; PinStatus = SIOBitRead(LDN, Register, BitNum); Return PinStatus ; VOID AaeonSetOutputLevel(byte LDN, byte Register, byte BitNum, byte Value){ ConfigToOutputMode(LDN, Register, BitNum); SIOBitSet(LDN, Register, BitNum, Value); ************************************************************************************ Appendix C – Digital I/O Ports...
  • Page 89 ************************************************************************************ VOID SIOEnterMBPnPMode(){ IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x87); VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0xAA); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN); VOID SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData);...
  • Page 90 ************************************************************************************ Boolean SIOBitRead(byte LDN, byte Register, byte BitNum){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData); TmpValue &= (1 << BitNum); SIOExitMBPnPMode(); If(TmpValue == 0) Return 0; Return 1; VOID ConfigToOutputMode(byte LDN, byte Register, byte BitNum){ Byte TmpValue, OutputEnableReg; OutputEnableReg = Register-1;...

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