Page 1: Table Of Contents
SECTION 1 DSP56156 OVERVIEW INTRODUCTION ......... . 1-3 DSP56100 CORE BLOCK DIAGRAM DESCRIPTION .
Page 2 SECTION 2 DSP56156 PIN DESCRIPTIONS INTRODUCTION ......... . 2-3 ADDRESS AND DATA BUS (32 PINS) .
Page 3 RAM MEMORY DESCRIPTION ......3-3 3.1.1 DSP56156 RAM Part Memory Introduction ....3-3 3.1.1.1 X Data Memory .
Page 4 HSR Host Flag 1 (HF1) Bit 4 ......5-12 TABLE OF CONTENTS MOTOROLA...
Page 5 Host Programmer Considerations ......5-21 5.15.2 DSP programmer considerations ......5-23 SECTION 6 MOTOROLA TABLE OF CONTENTS...
Page 6 ANALOG I/O DEFINITION ........6-4 INTERFACE WITH THE DSP56156 CORE PROCESSOR ..6-5 6.4.1...
Page 7 TIMER RESOLUTION ........7-8 FUNCTIONAL DESCRIPTION OF THE TIMER ....7-8 SECTION 8 MOTOROLA TABLE OF CONTENTS...
Page 8 CRB Sync/Async (SYN) Bit 10 ......8-18 8.12.11 CRB SSI Mode Select (MOD) Bit 11 ......8-18 viii TABLE OF CONTENTS MOTOROLA...
Page 9 Example One ......... . 9-5 MOTOROLA...
Page 10 Bootstrap Firmware Program........14 APPENDIX B DSP56156 APPLICATION EXAMPLES APPENDIX C PROGRAMMING SHEETS PERIPHERAL ADDRESSES .
Page 11 C.11 SSI ............58 MOTOROLA...
Page 12 Table of Contents (Continued) Paragraph Page Number Title Number TABLE OF CONTENTS MOTOROLA...
Page 13 Bus Operation ....... . 2-4 DSP56156 Pinout ......2-5 TA Controlled Accesses .
Page 14 ....6-50 6-31 Example of a Receive Reconstruction-interpolation IIR Filter ..6-51 LIST of FIGURES MOTOROLA...
Page 15 On-chip Frequency Synthesizer Programming Model Summary ..9-10 DSP56156 Bootstrap Program Listing ......15...
Page 16 No Glue Logic, Low Cost Memory Port Bootstrap — Mode 0 ... . 21 DSP56156 Host Bootstrap Example — Mode 1 ..... . 21 32K Words of External Program ROM —...
Page 17 C-41 SSI Status Register (SSISR) ........62 MOTOROLA...
Page 18 LIST of FIGURES MOTOROLA...
Page 19 1-11 DSP56156 Addressing Modes ........1-32...
Page 20 Move Peripheral Instructions 37 C-13 Transfer with Parallel Move Instruction ......37 LIST of TABLES MOTOROLA...
Page 21 C-22 Special Instructions ......... . . 41 MOTOROLA...
Page 22: Dsp56156 Overview
SECTION 1 DSP56156 OVERVIEW MOTOROLA 1 - 1...
Page 23 INSTRUCTION SET SUMMARY ........1-26 1 - 2 DSP56156 OVERVIEW MOTOROLA...
Page 24: Introduction
DSP56100 CORE56100 CORE processor (see Figure 1-2) which is common to all DSP56100 family processors (except for the DSP56116) and includes a detailed descrip- tion of the basic DSP56100 CORE instruction set. The DSP56156 User’s Manual and DSP56166 User’s Manual (see Figure 1-1) provide a brief overview of the core processor and detailed descriptions of the memory and peripherals that are chip specific.
Page 25 INTRODUCTION Table 1-1 DSP56156 Feature List 1 - 4 DSP56156 OVERVIEW MOTOROLA...
Page 26 • Two instruction LMS adaptive filter loop • Fast auto-return interrupts • Two external interrupt request pins DSP56156 On-chip Resources — RAM Version • 2K x 16 on-chip data RAM • 27 general purpose I/O pins • 2K x 16 on-chip program RAM •...
Page 27: Dsp56100 Core Block Diagram Description
RESET Figure 1-2 Detailed RAM Based Part Block Diagram A general block diagram of the DSP56156 is shown in Figure 1-2 (see Section 3.2 for in- formation on the ROM based part). The DSP56156 is optimized for applications such as medium to low bit rate speech encoding but can also be used in many other types of ap- plications.
Page 28 SSI0 SSI0 16-bit DSP 16-bit DSP SSI1 SSI1 SIGMA SIGMA Core Core DELTA DELTA CODEC HOST CODEC HOST TIMER TIMER OnCE OnCE Ext. Ext. Figure 1-4 DSP56156 RAM and ROM Based Functional Block Diagram MOTOROLA DSP56156 OVERVIEW 1 - 7...
Page 29: Data Buses
X Address Bus One (XAB1) and X Address Bus Two (XAB2). Program memory address- es are specified on the PAB. External memory spaces are addressed via a single 16-bit, unidirectional address bus driven by a three input multiplexer that can select the XAB1, 1 - 8 DSP56156 OVERVIEW MOTOROLA...
Page 30: Data Alu
40-bit result and logical operations are performed on 16-bit operands yielding 16- bit results in one of the two accumulators. The DSP56156 supports the two’s complement representation of binary numbers. Un- signed numbers are only supported by the multiply and multiply-accumulate instruction.
Page 31: Address Generation Unit (Agu)
Saturation arithmetic is provided to selectively limit overflow when reading a data ALU ac- cumulator register. The DSP56156 implements two types of rounding: convergent rounding and two’s comple- ment rounding. The type of rounding is selected by the status register rounding bit (R bit).
Page 32: Program Control Unit (Pcu)
XAB2. See the DSP56100 Family Manual for additional information. 1.2.5 Program Control Unit (PCU) The PCU performs instruction fetch, instruction decoding, hardware REP, DO loop con- trol, and exception processing. The interrupt priority register (IPR) (used to program the MOTOROLA DSP56156 OVERVIEW 1 - 11...
Page 33 (see Figure 1-8, Table 1-2, and Table 1-4). There are 30 inter- rupts available and two reserved on the DSP56156. Table 1-6 shows each of these inter- rupts with their respective starting address and Interrupt Priority Level (IPL). The four level...
Page 34 DSP56100 CORE BLOCK DIAGRAM DESCRIPTION MOTOROLA DSP56156 OVERVIEW 1 - 13...
Page 35 SSI0 TX Data X:$FFD1 SSI1 RX Data with X:$FFD9 Exception Status SSI1 RX Data X:$FFD9 SSI1 TX Data with X:$FFD9 Exception Status SSI1 TX Data X:$FFD9 Timer Overﬂow Interrupt X:$FFEC Lowest Timer Compare Interrupt X:$FFEC 1 - 14 DSP56156 OVERVIEW MOTOROLA...
Page 36 DSP56100 CORE BLOCK DIAGRAM DESCRIPTION Figure 1-9 Input/Output Block Diagram MOTOROLA DSP56156 OVERVIEW 1 - 15...
Page 37 B I/O PB10 HR/W PB11 PB12 PB13 HREQ PB14 HACK STD0 SRD0 SCK0 SSI0 SC10 Port SC00 C I/O STD1 SRD1 SCK1 SSI1 SC11 SC01 PC10 Timer PC11 Tout Codec SPKP SPKM Bias Vref Vdiv 1 - 16 DSP56156 OVERVIEW MOTOROLA...
Page 38: Interrupt Priority Structure
MEMORY ORGANIZATION Two independent memory spaces of the DSP56156 — X data and program, are described in detail in Section 3. These memory spaces are configured by control bits in the Operat- ing Mode Register.
Page 39: External Bus, I/O, And On-Chip Peripherals
16-bit timer, two Synchronous Serial Interfaces (SSI1 and SSI0), and a sigma-del- ta codec (see Figure 1-7). The DSP56156 provides 16 pins for an external address bus and 16 pins for an external data bus. These pins are grouped to form the Port A bus interface.
Page 40: Memory Expansion Port (Port A)
1.4.1 Memory Expansion Port (Port A) The DSP56156 expansion port is designed to synchronously interface over a common 16-bit data bus with a wide variety of memory and peripheral devices such as high speed static RAMs, slower memory devices, and other DSPs and MPUs in master/slave configurations.
Page 41: Timer
(use a common clock and frame sync) or asynchronous (use a common clock but different frame sync) with respect to each other. The SSI supports a subset of the Motorola SPI interface. The SSI requires three to six pins depending on the operating mode selected.
Page 42: Once
DSP56156. The host may select any one of 31 DSP56156 exception routines to be executed by writing a Vector Address Register in the HI. This flexibility allows the host programmer to execute up to 31 functions preprogrammed in the DSP56156.
Page 43 COUNTER (PC) REGISTER (OMR) 16 15 STACK POINTER (SP) RESERVED – WRITTEN AS ZERO, READ AS ZERO # READ AS SIGN EXTENSION BITS, WRITTEN AS DON’T CARE SYSTEM STACK Figure 1-10 DSP56156 Programming Model 1 - 22 DSP56156 OVERVIEW MOTOROLA...
Page 44: Data Alu Input Registers (X1, X0, Y1, Y0)
Global Data Bus. Each address register may be used as an input to the modulo arithmetic unit for a register update calculation. Each reg- ister may be written by the GDB or by the output of the modulo arithmetic unit. MOTOROLA DSP56156 OVERVIEW 1 - 23...
Page 45: Offset Register File (N0-N3)
The CCR is a special purpose control register which defines the current user state of the pro- 1 - 24 DSP56156 OVERVIEW MOTOROLA...
Page 46: Loop Counter (Lc)
BRKcc or an ENDDO instruction. When the end of a hardware program loop is reached, the contents of the loop counter register are tested for one. If the LC is one, the program loop is terminated and the LC register is loaded with MOTOROLA DSP56156 OVERVIEW 1 - 25...
Page 47: Loop Address Register (La)
SS and the status of the stack (underflow, empty, full, and overflow conditions – see Table 1-7). The SP is referenced implicitly by some instructions (DO, REP, JSR, RTI, etc.) or directly by the MOVEC instruction. Note that the stack pointer register is implemented 1 - 26 DSP56156 OVERVIEW MOTOROLA...
Page 48: Operating Mode Register (Omr)
The Rounding bit (R)selects between convergent rounding and two’s complement round- ing. When set, two’s complement rounding (always round up) is used. The Stop Delay bit (SD) is used to select the delay that the DSP needs to exit the STOP mode. MOTOROLA DSP56156 OVERVIEW 1 - 27...
Page 49 External reset at P:$E000 Normal Internal PRAM enabled Development 1 1 Internal PROM disabled Expanded External reset at P:$E000 Expanded External reset at P:$0000 Development 1 1 Internal program RAM Expanded disabled; External reset at P:$000 1 - 28 DSP56156 OVERVIEW MOTOROLA...
Page 50: Instruction Set Summary
DSP language compilers. Execution time is enhanced by the hardware looping capabilities. 1.7.1 Instruction Groups The instruction set is divided into the following groups: Arithmetic Logical Bit Field Manipulation Loop Move Program Control MOTOROLA DSP56156 OVERVIEW 1 - 29...
Page 51: Arithmetic Instructions
Sign Extend Accumulator from bit 31* IMAC Integer Multiply-Accumulate* IMPY Integer Multiply* Increment Accumulator INC24 Increment 24 MSBs of Accumulator Signed Multiply-Accumulate † MACR Signed Multiply-Accumulate and Round † Signed Multiply † MPYR Signed Multiply and Round † 1 - 30 DSP56156 OVERVIEW MOTOROLA...
Page 52: Logical Instructions
AND Immediate Program Controller Register* Logical Exclusive OR Logical Shift Left Logical Shift Right Logical Complement Logical Inclusive OR OR Immediate Program Controller Register* Rotate Left Rotate Right *These instructions do not allow parallel data moves. MOTOROLA DSP56156 OVERVIEW 1 - 31...
Page 53: Bit Field Manipulation Instructions
These instructions do not allow optional data transfers. Load Effective Address MOVE Move Data with or without Register Transfer – TFR(3) MOVE(C) Move Control Register MOVE(I) Move Immediate Short MOVE(M) Move Program Memory 1 - 32 DSP56156 OVERVIEW MOTOROLA...
Page 54: Program Control Instructions
The assembly language source code for a typical one word instruction is shown below. The source code is organized into four col- umns. Opcode Operands X Bus Data G Bus Data X0,Y0,A X:(R0)+,X0 X:(R3)+,Y0 MOTOROLA DSP56156 OVERVIEW 1 - 33...
Page 55: Addressing Modes
R1;N1;M1, R2;N2;M2, and R3;N3;M3. This structure is unique and extremely powerful in general, and particularly powerful in setting up DSP oriented data structures. Two sets of address registers can be used by the instruction set: one set for the first memory operation 1 - 34 DSP56156 OVERVIEW MOTOROLA...
Page 56 INSTRUCTION SET SUMMARY Table 1-11 DSP56156 Addressing Modes Operand Reference Uses Mn Addressing Mode Modifier X XX Register Direct Data or Control Register Address Register Rn Address Modifier Register Mn Address Offset Register Nn Address Register Indirect No Update Postincrement by 1...
Page 57: Address Arithmetic
1.7.4 Address Arithmetic The DSP56156 Address Generation Unit supports linear, modulo, and bit-reversed ad- dress arithmetic for all address register indirect modes. The address modifiers, Mn, deter- mine the type of arithmetic used to update addresses. Address modifiers allow the creation of data structures in memory for FIFOs (queues), delay lines, circular buffers, stacks, and bit-reversed FFT buffers.
Page 58: Dsp56156 Pin Descriptions
SECTION 2 DSP56156 PIN DESCRIPTIONS MOTOROLA 2 - 1...
Page 59 ON-CHIP CODEC (7 PINS) ........2-14 2 - 2 DSP56156 PIN DESCRIPTIONS MOTOROLA...
Page 60: Introduction
INTRODUCTION INTRODUCTION The DSP56156 pinout is shown in Figure 2-2. The input and output signals on the chip are organized into the 13 functional groups shown in Table 2-1. Figure 2-1 illustrates the relative timing for the bus signals. See the timing descriptions in the technical data sheet for exact information.
Page 61 Bus Operation (Read-Write- 0WT) T2 Tw T2 Tw T2 Tw T2 T2 Tw T2 Tw T2 Tw T2 T0 T1 CLKO PS/DS A0-A15 Data in Data out D0-D15 Bus Operation (Read-Write- 3WT) Figure 2-1 Bus Operation 2 - 4 DSP56156 PIN DESCRIPTIONS MOTOROLA...
Page 62 1 Apower pin) Vdd port C Vss Port C Figure 2-2 DSP56156 Pinout (Read/Write)- three state, active low output. Timing is the same as for the ad- dress lines, providing an “early write” signal. R/W (which changes in t0) is high for a read access and is low for a write access.
Page 63 BCR register, zero wait states will be inserted in the external bus cycle, regard- less the status of TA during the leading edge of T2. 2 - 6 DSP56156 PIN DESCRIPTIONS MOTOROLA...
Page 64 Mode). In this mode, the DSP is not the external bus master and has to assert BR to request the bus mastership. The DSP bus controller will insert wait states until BG input is asserted and will then begin normal bus accesses after the ris- MOTOROLA DSP56156 PIN DESCRIPTIONS 2 - 7...
Page 65 (Bus Busy) - active low input when not bus master, active low output when bus master. This pin is asserted by the DSP when it becomes the bus master and it performs an external access. It is deasserted when the DSP re- 2 - 8 DSP56156 PIN DESCRIPTIONS MOTOROLA...
Page 66: Interrupt And Mode Control (3 Pins)
(Reset) - This input is a direct hardware reset of the processor. When RESET is asserted, the DSP is initialized and placed in the reset state. A Schmitt trigger input is used for noise immunity. When the reset pin is deasserted, the initial MOTOROLA DSP56156 PIN DESCRIPTIONS 2 - 9...
Page 67: Power, Ground, And Clock (28 Pins)
(External Filter Capacitor) - This pin is used to add an external capacitor to SXFC the PLL filter circuit. A low leakage capacitor should be connected between SXFC and VDDS; it should be located very close to those pins. 2 - 10 DSP56156 PIN DESCRIPTIONS MOTOROLA...
Page 68: Host Interface (15 Pins)
HI DMA data transfers. If programmed as an MC68000 Host Interrupt Acknowledge, HACK is used to enable the HI Interrupt Vector Register (IVR) onto the Host Data Bus H0-H7 if the Host Request HREQ output MOTOROLA DSP56156 PIN DESCRIPTIONS 2 - 11...
Page 69: 16-Bit Timer (2 Pins)
(SSI1 Transmit Data) - This output pin transmits serial data from the SSI1 Transmit Shift Register. STD1 may be programmed as a general purpose I/O pin called PC5 when the SSI1 STD1 function is not being used. 2 - 12 DSP56156 PIN DESCRIPTIONS MOTOROLA...
Page 70: On-Chip Emulation (4 Pins)
DSO line will be asserted (negative true logic) for four T cycles (one instruction cycle) to indicate that the serial shift register is ready to receive clocks in order to deliver the data. When the chip enters the MOTOROLA DSP56156 PIN DESCRIPTIONS 2 - 13...
Page 71: On-Chip Codec (7 Pins)
(2/5)VDDA. This pin should be connected to the ground via a capacitor when the codec is used and should be left floating when the codec is not used. 2 - 14 DSP56156 PIN DESCRIPTIONS MOTOROLA...
Page 72: Operating Modes And Memory Spaces
SECTION 3 OPERATING MODES AND MEMORY SPACES MOTOROLA 3 - 1...
Page 73 ROM MEMORY DESCRIPTION ......3-9 3 - 2 OPERATING MODES AND MEMORY SPACES MOTOROLA...
Page 74: Ram Memory Description
This part of the DSP56156 memory description describes the part that uses RAM memory for the Program Memory . The memory of the DSP56156 can be partitioned in several ways to provide high-speed parallel operation and additional off-chip memory expansion.
Page 75: Data Memory
(the host processor can terminate down-loading early by setting HF0=0). If bit-15 = 1, the bootstrap program will load through SSI0. Data is packed into program RAM least sig- nificant byte of P:$0000 first. 3 - 4 OPERATING MODES AND MEMORY SPACES MOTOROLA...
Page 76: Chip Operating Modes
OMR and changing the MA and MB bits. When the operating mode is first changed to Mode 0, the DSP56156 executes a boot- strap program which loads program memory from a byte wide memory located at P:$C000 (see Table 3-1).
Page 77: Bootstrap Mode (Mode 1)
MB bits (see Table 3-1). When the operating mode is first changed to Mode 1, the DSP56156 executes a bootstrap program which loads program memory from either the host port or SSI0 depending on whether bit 15 of location P:C000 is a zero (host port) or a one (SSI0).
Page 78: Bootstrap Control Logic
DSP’s internal program RAM (see Appendix A for a listing of the bootstrap code). The program is written in DSP56100 core assembly language. It contains three separate methods of initializing the PRAM: loading from a byte-wide memory starting at location MOTOROLA OPERATING MODES AND MEMORY SPACES 3 - 7...
Page 79 If bit 15 of P:$C000 is set (a pull-up resistor can be used in some applications), the boot- strap is performed through the Synchronous Serial Interface SSI0. The bootstrap program sets up the SSI0 in 8 bit mode, external clock, and asynchronous mode. 3 - 8 OPERATING MODES AND MEMORY SPACES MOTOROLA...
Page 80: Rom Memory Description
Figure 3-2 DSP56156 ROM Memory Map ROM MEMORY DESCRIPTION This part of the DSP56156 memory description describes the part that uses 12K of ROM memory for the Program Memory . The memory of the DSP56156 can be partitioned in several ways to provide high-speed parallel operation and additional off-chip memory ex- pansion.
Page 81: Data Memory
OMR and changing the MA and MB bits. The memory maps for Mode 0 and Mode 1 are identical. The difference between Mode 0 and Mode 2 is the 3 - 10 OPERATING MODES AND MEMORY SPACES MOTOROLA...
Page 82: Mode 1
MA and MB bits (see Table 3-3). DSP56156ROM chips with bad or ob- solete internal program ROM code can be used with external program memory in the development mode. Reset vectors to program memory location P:$0000. MOTOROLA OPERATING MODES AND MEMORY SPACES 3 - 11...
Page 84 SECTION 4 I/O INTERFACE MOTOROLA 4 - 1...
Page 85 INTRODUCTION ..........4-3 I/O PORT SET-UP AND PROGRAMMING ......4-3 4 - 2 I/O INTERFACE MOTOROLA...
Page 86: Introduction
INTRODUCTION INTRODUCTION The DSP56156 provides 16 pins for an external address bus and 16 pins for an external data bus. These pins are grouped to form the Port A bus interface. The DSP56156 also provides 27 programmable I/O pins. These pins may be used as general purpose I/O pins or allocated to an on-chip peripheral.
Page 87: Port Registers
5 bit wait control fields specify between 0 and 31 wait states for an external X memory and P memory ac- cess. Wait state fields are set to $1F during hardware reset. 4 - 4 I/O INTERFACE MOTOROLA...
Page 88 PB10 PB11 HR/W PB12 PB13 HREQ PB14 HACK STD0 SRD0 SCK0 SSI0 SC10 Port C SC00 STD1 SRD1 SSI1 SCK1 SC11 SC01 PC10 Timer PC11 TOUT Figure 4-1 DSP56156 Input / Output Block Diagram MOTOROLA I/O INTERFACE 4 - 5...
Page 89: Port B And Port C Registers
12-bit Port C Data Direction Register (PCDDR), and a 12 bit Port C Data Register (PCD). These registers are shown in Figure 4-2. All registers are read/write. Bit manipulation instructions can be used to access individual bits. 4 - 6 I/O INTERFACE MOTOROLA...
Page 90 REGISTER (PCD) X:$FFE3 15 14 13 12 11 10 9 * Reserved Bits; Read as zero and should be written as zero for future compatibility. Figure 4-2 I/O Port B and C Programming Models MOTOROLA I/O INTERFACE 4 - 7...
Page 91 Port B Data Register (PBD) $FFC2 Port B Data Direction Register $FFE1 $FFC1 Port C Control Register (PCC) $FFE0 $FFC0 Port B Control Register (PBC) Note: The underlined addresses indicate Figure 4-3 DSP56156 On-chip peripherals Memory Map 4 - 8 I/O INTERFACE MOTOROLA...
Page 92: Host Interface
SECTION 5 HOST INTERFACE MOTOROLA 5 - 1...
Page 93 DMA MODE OPERATION ........5-18 5.15 HOST PORT USAGE – GENERAL CONSIDERATIONS ....5-21 5 - 2 HOST INTERFACE MOTOROLA...
Page 94: Introduction
If the full handshake is not needed, the host processor can treat the DSP56156 as fast memory and data can be transferred between the host and DSP56156 at the fastest host processor rate. DMA hardware may be used with the external Host Request and Host Acknowledge pins to transfer data at the maximum DSP56156 interrupt rate.
Page 95 DATA BUS INTERRUPT VECTOR REGISTER INTERRUPT CONTROL REGISTER HF2,3 CONTROL INTERRUPT REGISTER STATUS REGISTER HF0,1 STATUS COMMAND REGISTER VECTOR REGISTER HA0-HA2 HOST HR/W INTERRUPTS INTERFACE CONTROL HACK LOGIC HREQ Figure 5-1 Host Interface Block Diagram 5 - 4 HOST INTERFACE MOTOROLA...
Page 96: Host Interface Programming Model
HOST INTERFACE PROGRAMMING MODEL HOST INTERFACE PROGRAMMING MODEL The HI has two programming models - one for the DSP56156 programmer and one for the host processor programmer. In most cases, the notation used in this manual reflects the DSP56156 perspective. The Host Interface - DSP56156 Programming Model is shown in Figure 5-2.
Page 97: Host Receive Data Register (Hrx)
The Host Receive Data register (HRX) is used for host processor to DSP data transfers. The HRX register is viewed as a 16-bit read-only register by the DSP. The HRX register is loaded with 16-bit data from the Transmit Data Registers TXH: TXL when both the 5 - 6 HOST INTERFACE MOTOROLA...
Page 98: Command Vector Register (Cvr)
This will cause an improper fast exception. 5.7.2 CVR Reserved bits – Bits 5 and 6 Reserved bits are unused and are read by the host as zeros. Reserved bits should be writ- ten as zero for future compatibility. MOTOROLA HOST INTERFACE 5 - 7...
Page 99 ADDRESS MAP IVR (8 BIT) IVR (8 BIT) read zeros not used reserved reserved RXH (8 BIT) TXH (8 BIT) RXL (8 BIT) TXL (8 BIT) Figure 5-3 Host Interface - Host Processor Programming Model 5 - 8 HOST INTERFACE MOTOROLA...
Page 100: Cvr Host Command Bit (Hc) Bit 7
The Host Control Register (HCR) is an 8-bit read/write control register used by the DSP to control the HI interrupts and flags. HCR cannot be accessed by the host processor. The HCR register occupies the low order byte of the internal data bus - the high order portion MOTOROLA HOST INTERFACE 5 - 9...
Page 101: Hcr Host Receive Interrupt Enable (Hrie) Bit 0
Changing HF3 will change the Host Flag 3 (HF3) bit of the Interrupt Sta- tus Register ISR on the host processor side of the host interface. HF3 may be set or cleared by the DSP. 5 - 10 HOST INTERFACE MOTOROLA...
Page 102: Hcr Reserved Control - Bits 5, 6 And 7
HC and HCP are cleared by the DSP exception hardware when the exception is taken. The host processor can clear HC which also clears HCP. The HCP is cleared by DSP reset. This bit is typically used for polling operations. MOTOROLA HOST INTERFACE 5 - 11...
Page 103: Hsr Host Flag 0 (Hf0) Bit 3
Interrupt Status register (ISR) is set. When RREQ is cleared, RXDF inter- rupts are disabled. When RREQ is set, the external Host Request HREQ pin will be as- serted if RXDF is set. 5 - 12 HOST INTERFACE MOTOROLA...
Page 104: Icr Transmit Request Enable (Treq) Bit 1
HF0 may be set or cleared by the host processor and cannot be changed by the DSP. Changing HF0 also changes the Host Flag bit 0 (HF0) of the Host Status reg- ister HSR on the DSP side of the HI. HF0 is cleared by DSP reset. MOTOROLA HOST INTERFACE 5 - 13...
Page 105: Icr Host Flag 1 (Hf1) Bit 4
HA0 of the HI during a DMA transfer. The Host Address bit HA2 is forced to one dur- ing each DMA transfer. The address counter can be initialized with the INIT bit feature. After each DMA transfer on the Host Data Bus, the address counter is incremented to the 5 - 14 HOST INTERFACE MOTOROLA...
Page 106: Icr Initialize Bit (Init) Bit 7
— DMA Mode (HM1 or HM0 = 1) TREQ RREQ After INIT Execution INIT=0; address counter = HM1,HM0 INIT=0; RXDF=0; HTDE=1; address counter = HM1,HM0 INIT=0; TXDE=1; HRDF=0; address counter = HM1,HM0 Undefined (illegal) MOTOROLA HOST INTERFACE 5 - 15...
Page 107: Interrupt Status Register (Isr)
HI to the DSP CPU is clear. By testing TRDY, the host processor programmer can be assured that the first word received by the DSP will be the first word the host pro- cessor transmits. 5 - 16 HOST INTERFACE MOTOROLA...
Page 108: Isr Host Flag 2 (Hf2) Bit 3
DSP reset will clear HREQ. 5.12 INTERRUPT VECTOR REGISTER (IVR) The Interrupt Vector Register (IVR) is an 8-bit read/write register which contains the ex- ception vector number for use with MC68000 processor family vectored interrupts. This MOTOROLA HOST INTERFACE 5 - 17...
Page 109: Ivr Host Interface Interrupts
DMA memory. The external DMA controller must provide the address to the external DMA memory. The address of the selected HI register is provided by a DMA address counter in the DSP HI. 5 - 18 HOST INTERFACE MOTOROLA...
Page 110: 5.14.1 Host To Dsp - Host Interface Action
Enable the DMA controller channel. 2. Set TXDE and clear HRDF. This can be done with the appropriate Initialize function. The host must also initialize the DMA counter in the HI using the Initialize feature. MOTOROLA HOST INTERFACE 5 - 19...
Page 111: 5.14.3 Dsp To Host Interface Action
HTDE=0) before Step 2 will be executed. NOTES: • The HOST→ DSP data transfers can occur normally in the channel not used for DMA except that the HOST must use polling and not interrupts. 5 - 20 HOST INTERFACE MOTOROLA...
Page 112: 5.14.4 Dsp To Host - Host Processor Procedure
When reading receive byte registers, RXH or RXL, the host programmer should use interrupts or poll the RXDF flag which indicates that data is available. This guarantees that the data in the receive byte registers will be stable. MOTOROLA HOST INTERFACE 5 - 21...
Page 113 DSP. Because the host does not know exactly when the exception will be recognized, because of synchronization, and because pipelining of exception processing, the DSP may execute the host exception 5 - 22 HOST INTERFACE MOTOROLA...
Page 114: 5.15.2 Dsp Programmer Considerations
DSP will read the status bits that were synchronized during transition. The solution to this potential problem is to read the bits twice for consensus. MOTOROLA HOST INTERFACE 5 - 23...
Page 116: Dsp56156 On-Chip Sigma/Delta Codec
SECTION 6 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA 6 - 1...
Page 117 ANALOG I/O DEFINITION ........6-4 INTERFACE WITH THE DSP56156 CORE PROCESSOR ... . . 6-5 ON-CHIP CODEC FREQUENCY RESPONSE AND GAIN ANALYSIS .
Page 118: Introduction
DEC block. It discusses the general block diagram of the A/D and D/A sections, the hand- shake between the DSP56156 core processor and the codec, as well as the last decima- tion antialiasing filter and first interpolation reconstruction filter performed in software by the DSP56156 core processor.
Page 119: Analog I/O Definition
DSP core in order to reduce the codec cell die area. ANALOG I/O DEFINITION This section describes the Motorola DSP56156 analog input and output characteristics (see Figure 6-2). There are two analog inputs MIC and AUX. Selection between MIC or AUX is made via one control bit (INS bit) and can be changed any time as desired.
Page 120: Interface With The Dsp56156 Core Processor
Analog Decoupling VssA near DSP Ext. GND Ext. Supply Single trace Figure 6-2 DSP56156 Analog Input and Output Diagram INTERFACE WITH THE DSP56156 CORE PROCESSOR This section discusses the use of each bit in the codec control registers. 6.4.1 Interface Definition The Σ∆...
Page 121: On-Chip Codec Programming Model
INTERFACE WITH THE DSP56156 CORE PROCESSOR 6.4.2 On-chip Codec Programming Model Figure 6-3 shows the four memory mapped registers (mapped into three memory loca- tions) used by the on-chip codec. On-chip Codec DATA REGISTERS READ-ONLY CODEC RECEIVE DATA CRX REGISTER...
Page 122: Codec Control Register (Cocr)
INTERFACE WITH THE DSP56156 CORE PROCESSOR clears the CTDE bit in the codec status register COSR. The DSP may program the COIE bit to cause a Codec Interrupt when CTDE is set. 6.4.5 Codec Control Register (COCR) The Codec Control Register COCR is a 16-bit read/write register used to direct the on- chip codec operation.
Page 123: Cocr Mute Bit (Mut) Bit 10
INTERFACE WITH THE DSP56156 CORE PROCESSOR Table 6-3 Audio Level Control with DSP Filter Gain VC3 VC2 VC1 VC0 Relative Level Digital Filter Final Output Gain Level 6.4.5.2 COCR Codec Ratio Select Bits (CRS1-0) Bits 8,9 The Codec Ratio Select Bits are used by the DSP core to program the decimation and interpolation ratio of the on-chip codec comb filter sections.
Page 124: Cocr Input Select Bit (Ins) Bit 13
INTERFACE WITH THE DSP56156 CORE PROCESSOR up to 3dB below the full scale saturation values. The full scale saturation analog values result in a maximum digital A/D output ($7FFF) when the A/D comb filter has a unity gain. Table 6-5 Microphone Gain Control...
Page 125: Cosr Codec Receive Overrun Error Flag Bit (Croe) Bit 1
INTERFACE WITH THE DSP56156 CORE PROCESSOR 6.4.6.2 COSR Codec Receive Overrun Error Flag Bit (CROE) Bit 1 The Codec Receive Overrun Error Flag bit is set when a new sample is received from the codec section while the previous received sample in the CRX receive register has not been read by the DSP (overrun error).
Page 126 INTERFACE WITH THE DSP56156 CORE PROCESSOR Table 6-6 On-Chip Codec Programming Model Summary On-chip Codec STATUS REGISTERS (COSR X:$FFE8) CRDF CTDE CROE CTUE CRDF Data From A/D not received in CRX (read-only) Data From A/D received in CRX CTDE Data in CTX has not been transferred to D/A...
Page 127: On-Chip Codec Frequency Response And Gain Analysis
2.048 MHz master clock and a decimation ratio of D=128. The figures show the frequency response in the bands 0-1.024 MHz and 0-16 KHz (Figure 6-4) and in the band 0-4 KHz (Figure 6-5). 6 - 12 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 128 -160 0.001 1024 Frequency (KHz) Cascade of: sum3-128.Filter diff3-128.Filter -100 -120 -140 -160 0.001 Frequency (KHz) Figure 6-4 Log Magnitude Frequency Response of the A/D Comb Filter for F=2.048 MHz and D=128 MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 13...
Page 129 Table 6-8 gives an example of a 4 biquad IIR low pass filter whose transfer function has been shaped accordingly. Figure 6-6 shows the filter frequency response and the effects on the overall D/A section response. 6 - 14 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 130 ; n2_4 = 0.7316442217/2 $1b24 ; n1_4 = 0.42404578/2 NOTE: This filter, as well as all the figures representing filter re- sponses, has been generated using ZOLA Technologies, Inc., DSP Designer™ software package. MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 15...
Page 131 Frequency (KHz) IIR Decimation Filter Response A/D Comb Filter Response A/D Final Filter Response 0.001 Frequency (KHz) Figure 6-6 IIR Decimation and A/D Section Log Magnitude Frequency Response for F=2.048 MHz and D=128 6 - 16 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 132: D/A Section Frequency Response And Dc Gain
The on-chip codec D/A section is formed of three different filtering steps which are studied in the next subsections. The frequency responses of the different D/A sections are illus- trated in Figure 6-7. MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 17...
Page 133 D/A Comb Filter Response D/A Analog LP Filter Response -100 0.001 1024 Frequency (KHz) Figure 6-7 Log Magnitude Frequency Responses of the Three Sections in the D/A for F=2.048 MHz and D=128 6 - 18 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 134: D/A Second Order Digital Comb Filter
Figure 6-8 shows an example of the D/A digital comb filter log magnitude response using a 2.048 MHz master clock and a decimation ratio of D=128. The figure shows the comb filter frequency response in the bands 0-1024 KHz and 0-16 KHz. MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 19...
Page 135 -100 -200 -300 0.001 1024 Frequency (KHz) Cascade of: diff2-128.Filter sum2-128.Filter -100 0.001 Frequency (KHz) Figure 6-8 Log Magnitude Frequency Response of the D/A Comb Filter for F=2.048MHz and D=128 6 - 20 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 136: D/A Analog Comb Decimating Filter
2.048 MHz master clock. The figures show the comb filter frequency re- sponse in the 0-1024 KHz, 0-256 KHz, and 0-8 KHz bands. It can be noticed that the re- sponse in the band 0-8 KHz is flat. MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 21...
Page 137 ON-CHIP CODEC FREQUENCY RESPONSE AND GAIN ANALYSIS Cascade of: analogsum3-128.Filter analogdiff3-128.Filter -100 0.001 1024 Frequency (KHz) Figure 6-9 Log Magnitude Frequency Response of the D/A Analog Comb Filter for F=2.048 MHz 6 - 22 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 138 ON-CHIP CODEC FREQUENCY RESPONSE AND GAIN ANALYSIS Cascade of: analogsum3-128.Filter analogdiff3-128.Filter -100 0.001 Frequency (KHz) Cascade of: analogsum3-128.Filter analogdiff3-128.Filter -100 0.001 Frequency (KHz) Figure 6-10 Log Magnitude Frequency Response of the D/A Analog Comb Filter for F=2.048 MHz MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 23...
Page 139: D/A Analog Low Pass Filter
Figure 6-11 shows an example of the D/A analog low-pass filter log magnitude response using a 512Khz master clock. This figure shows the filter frequency response in the bands 0- 256 KHz and 0-8 KHz. 6 - 24 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 140 0.001 Frequency (KHz) analog-lp.Filter 0.001 Frequency (KHz) analog-lp.Filter 0.08 0.06 0.04 0.02 -0.02 -0.04 0.001 Frequency (KHz) Figure 6-11 Log Magnitude Frequency Response of the D/A Analog Low-pass Filter for F=512 KHz MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 25...
Page 141: D/A Section Overall Frequency Response
The D/A analog comb filter frequency response is flat in the audio band and does not need any compensation (see Figure 6-10). The digital second order D/A comb filter is the only filter that needs to be compensated. 6 - 26 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 142 -100 0.001 Frequency (KHz) Cascade of: diff2-128.Filter sum2-128.Filter analogsum3-128.Filter analogdiff3-128.Filter analog-lp.Filter 0.001 Frequency (KHz) Figure 6-13 Log Magnitude Frequency Response of the D/A Section for F=2.048 MHz and D=128 MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 27...
Page 143 ; n2_4 = 0.7366593399/2 $1c8f ; n1_4 = 0.4462262322/2 NOTE: This filter, as well as all the figures representing filter re- sponses, has been generated using ZOLA Technologies, Inc., DSP Designer™ software package. 6 - 28 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 144 Frequency (KHz) IIR Interpolation Filter Response D/A Section Filter Response D/A Final Filter Response 0.001 Frequency (KHz) Figure 6-14 IIR Interpolation and D/A Section Log Magnitude Frequency Response for F=2.048 MHz and D=128 MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 29...
Page 145: Application Examples
8 KHz 1 bit digital 2nd order 16-bit Σ∆ modulator Comb Filter compensation sample filter ÷ 500KHz 2MHz 3 pole 2 zero 3rd order Comb Filter Figure 6-15 Example 1 functional block diagram 6 - 30 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 146 Figure 6-16 shows the characteristics of the transmit and receive filters that we consider for this example. ±0.5dB Frequency (kHz) Figure 6-16 Example of Transmit and Receive Filter Performance Constraints MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 31...
Page 147: A/D Decimation Dsp Filter
Figure 6-17 Example of a Transmit Antialiasing-decimation IIR Filter The IIR filter shown in Figure 6-17 is implemented using 4 biquadratic sections. The gain and coefficients of the four sections are listed in Table 6-12. 6 - 32 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 148 ; -d1_4 = 1.894549449/2 $f477 ; n2_4 = -0.1802356271/2 $285f ; n1_4 = 0.6307957449/2 Figure 6-18 shows the overall response of the A/D section cascaded with the DSP IIR filter described above. MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 33...
Page 149 Cascade of: sum3-125.Filter diff3-125.Filter compad125.IIR.Filter 0.001 Frequency (kHz) Cascade of: sum3-125.Filter diff3-125.Filter compad125.IIR.Filter 0.001 Frequency (kHz) Figure 6-18 Overall Response of the A/D Section when Using the IIR Filter of Figure 6-17. 6 - 34 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 150: D/A Interpolation Filter
Figure 6-19 Example of a Receive Reconstruction-interpolation IIR Filter The IIR filter shown in Figure 6-19 is implemented using 4 biquadratic sections. The gain and coefficients of the four section are listed in Table 6-13. MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 35...
Page 151 $7923 ; -d1_4 = 1.892747933/2 $19a1 ; n2_4 = 0.4004225192/2 $5060 ; n1_4 = 1.255851238/2 Figure 6-20 shows the overall response of the DSP IIR filter cascaded with the D/A sec- tion. 6 - 36 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 152 0.001 Frequency (kHz) Cascade of: compda125.IIR.Filter diff2-125.Filter sum2-125.Filter analogsum3-125.Filter analogdiff3-125.Filter analog-lp.Filter 0.001 Frequency (kHz) Figure 6-20 Overall Response of the D/A Section When Using the IIR Filter of Figure 6-19 MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 37...
Page 153: Example 3
8 KHz 1 bit digital 2nd order 16-bit Σ∆ modulator compensation Comb Filter sample filter ÷ 750KHz 3MHz 3 pole 2 zero 3rd order Comb Filter Figure 6-21 Example 2 functional block diagram 6 - 38 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 154 Figure 6-22 shows the characteristics of the transmit and receive filters that we consider for this example. ±0.5dB Frequency (kHz) Figure 6-22 Example of Transmit and Receive Filter Performance Constraints MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 39...
Page 155: A/D Decimation Dsp Filter
Figure 6-23 Example of a Transmit Antialiasing-decimation IIR Filter The IIR filter shown in Figure 6-23 is implemented using 5 biquadratic sections. The gain and coefficients of the four section are listed in Table 6-15. 6 - 40 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 156 ; -d1_5 = 1.938610906/2 $dd40 ; n2_5 = -0.5429834643/2 $e4dd ; n1_5 = -0.4240192654/2 Figure 6-24 shows the overall response of the A/D section cascaded with the DSP IIR filter described above. MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 41...
Page 157 Cascade of: sum3-125.Filter diff3-125.Filter compad125-3.IIR.Filter 0.001 Frequency (kHz) Cascade of: sum3-125.Filter diff3-125.Filter compad125-3.IIR.Filter 0.001 Frequency (kHz) Figure 6-24 Overall Response of the A/D Section when Using the IIR Filter of Figure 6-23. 6 - 42 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 158: D/A Interpolation Filter
Figure 6-25 Example of a Receive Reconstruction-interpolation IIR Filter The IIR filter shown in Figure 6-25 is implemented using 5 biquadratic sections. The gain and coefficients of the four section are listed in Table 6-16. MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 43...
Page 159 $7c4e ; -d1_5 = 1.942249147/2 $ce92 ; n2_5 = -0.7723597585/2 $f27d ; n1_5 = -0.211141353/2 Figure 6-26 shows the overall response of the DSP IIR filter cascaded with the D/A sec- tion. 6 - 44 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 160 0.001 Frequency (kHz) Cascade of: compda125-3.IIR.Filter diff2-125.Filter sum2-125.Filter analogsum3-125.Filter analogdiff3-125.Filter analog-lp.Filter 0.001 Frequency (kHz) Figure 6-26 Overall Response of the D/A Section When Using the IIR Filter of Figure 6-25 MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 45...
Page 161 8 KHz 1 bit digital 2nd order 16-bit Σ∆ modulator compensation Comb Filter sample filter ÷ 1.68MHz 420KHz 3 pole 3rd order 2 zero Comb Filter Figure 6-27 Example 3 functional block diagram 6 - 46 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 162 6-28 shows the characteristics of the transmit and re- ceive filters that we consider for this example. ±0.5dB Frequency (kHz) Figure 6-28 Example of Transmit and Receive Filter Performance Constraints MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 47...
Page 163 Figure 6-29 Example of GSM Transmit Antialiasing-decimation IIR Filter The IIR filter shown in Figure 6-29 is implemented using 4 biquadratic sections. The gain and coefficients of the four section are listed in Table 6-18. 6 - 48 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 164 ; -d1_4 = 1.89978731/2 $e7fd ; n2_4 = -0.3751780353/2 $d812 ; n1_4 = -0.6238880148/2 Figure 6-30 shows the overall response of the A/D section cascaded with the DSP IIR filter described above. MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 49...
Page 165 Cascade of: sum3.Filter diff3.Filter compad105.IIR.Filter 0.001 Frequency (kHz) Cascade of: sum3.Filter diff3.Filter compad105.IIR.Filter 0.001 Frequency (kHz) Figure 6-30 Overall Response of the A/D Section when Using the IIR Filter of Figure 6-29. 6 - 50 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 166 Figure 6-31 Example of a Receive Reconstruction-interpolation IIR Filter The IIR filter shown in Figure 6-31 is implemented using 4 biquadratic sections. The gain and coefficients of the four section are listed in Table 6-19. MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 51...
Page 167 $7990 ; -d1_4 = 1.899401635/2 $e724 ; n2_4 = -0.3884263941/2 $d908 ; n1_4 = -0.6089069362/2 Figure 6-32 shows the overall response of the DSP IIR filter cascaded with the D/A sec- tion. 6 - 52 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 168 0.001 Frequency (kHz) Cascade of: compda105.IIR.Filter diff2-105.Filter sum2-105.Filter analogsum3-105.Filter analogdiff3-105.Filter analog-lp.Filter 0.001 Frequency (kHz) Figure 6-32 Overall Response of the D/A Section When Using the IIR Filter of Figure 6-31 MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 53...
Page 169 8 KHz 1 bit digital 2nd order 16-bit Σ∆ modulator compensation Comb Filter sample filter ÷ 1.944MHz 486KHz 3 pole 2 zero 3rd order Comb Filter Figure 6-33 Example 4 functional block diagram 6 - 54 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 170 6-34 shows the characteristics of the transmit and re- ceive filters that we consider for this example. ±0.5dB Frequency (kHz) Figure 6-34 Example of Transmit and Receive Filter Performance Constraints MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 55...
Page 171 Figure 6-35 Example of a Transmit Antialiasing-decimation IIR Filter The IIR filter shown in Figure 6-35 is implemented using 5 biquadratic sections. The gain and coefficients of the four section are listed in Table 6-21. 6 - 56 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 172 ; -d1_5 = 1.936312495/2 $d103 ; n2_5 = -0.7341826041/2 $ef0b ; n1_5 = -0.2649274056/2 Figure 6-36 shows the overall response of the A/D section cascaded with the DSP IIR filter described above. MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 57...
Page 173 Cascade of: sum3-81.Filter diff3-81.Filter compad81.IIR.Filter 0.001 Frequency (kHz) Cascade of: sum3-81.Filter diff3-81.Filter compad81.IIR.Filter 0.001 Frequency (kHz) Figure 6-36 Overall Response of the A/D Section when Using the IIR Filter of Figure 6-35 6 - 58 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 174 Figure 6-37 Example of a Receive Reconstruction-interpolation IIR Filter The IIR filter shown in Figure 6-37 is implemented using 4 biquadratic sections. The gain and coefficients of the four section are listed in Table 6-22. MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 59...
Page 175 $7bd9 ; -d1_5 = 1.935136984/2 $ca80 ; n2_5 = -0.8359239371/2 $f59e ; n1_5 = -0.1622571097/2 Figure 6-38 shows the overall response of the DSP IIR filter cascaded with the D/A sec- tion. 6 - 60 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 176 0.001 Frequency (kHz) Cascade of: compda81.IIR.Filter diff2-81.Filter sum2-81.Filter analogsum3-81.Filter analogdiff3-81.Filter analog-lp.Filter 0.001 Frequency (kHz) Figure 6-38 Overall Response of the D/A Section When Using the IIR Filter of Figure 6-37 MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 61...
Page 177: Example 5 - Real-Time I/O Example With On-Chip Codec And Pll
The routine in this example performs real-time input-output for the main DSP routine. As mentioned, the DSP56156 has an on-chip A/D and D/A codec which allows the DSP to communicate with a microphone and a speaker directly. Thus, the set-up sequences for the codec as well as the on-chip frequency synthesizer (PLL) are included.
Page 178 ; d1_2 = -0.3304817315/2 $34d4 ; n2_2 = 0.8254454107/2 $1767 ; n1_2 = 0.3656574962/2 ; Biquad stage no. 3 -$1078 ; d2_3 = 0.2573392333/2 $f271 ; d1_3 = -0.2118237522/2 $1ab7 ; n2_3 = 0.4174162168/2 MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 63...
Page 179 ; enable Scale Up mode x:(r3)+,x0 ; a = x(n)/2,x0=g/2 move a,y0 ; y0 = x(n) y0,x0,a ; a = g/2 * x(n) move x:(r0)+,y0 x:(r3)+,x0 ; y0 = w(n-2), x0 = a2/2 #nstages,_end1 6 - 64 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 180: Dsp Program Flowchart
#$800,sr DSP PROGRAM FLOWCHART The last A/D section decimation-compensation filter as well as the first D/A section interpolation/ compensation filters are performed by the DSP core of the DSP56156 processor. The same in- MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 65...
Page 181 • the number and size of general tasks handled by the interrupt routine itself Figure 6-39 shows an example of a flowchart for a long interrupt routine. 6 - 66 DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA...
Page 182 8KHz? to D/A COMB store sample in the speech End of frame INTERPOLATION End of restore context DECIMATION End of long interrupt routine Figure 6-39 Flowchart of a Decimation/Interpolation Routine MOTOROLA DSP56156 ON-CHIP SIGMA/DELTA CODEC 6 - 67...
Page 184: 16-Bit Timer And Event Counter
SECTION 7 16-BIT TIMER AND EVENT COUNTER MOTOROLA 7 - 1...
Page 185 TIMER RESOLUTION ......... . 7-8 FUNCTIONAL DESCRIPTION OF THE TIMER ..... . 7-8 7 - 2 16-BIT TIMER AND EVENT COUNTER MOTOROLA...
Page 186: Introduction
If the timer is disabled (TE=0) during the write, the value is immediately written to the count register and will not be overwritten by the value stored in the preload register when MOTOROLA 16-BIT TIMER AND EVENT COUNTER 7 - 3...
Page 187: Timer Preload Register (Tpr)
(TPR), this new value is transferred to the count register the next time the count register is loaded (after it reaches zero), unless a direct write to the count register is performed while the TCTR is zero. 7 - 4 16-BIT TIMER AND EVENT COUNTER MOTOROLA...
Page 188: Timer Compare Register (Tcpr)
Timer Out Enable bits (TO2-TO0) of the timer control register. This is useful for providing a pulse width modulated timer output. The compare register is initialized to zero by hardware RESET and software reset (RESET instruction). MOTOROLA 16-BIT TIMER AND EVENT COUNTER 7 - 5...
Page 189: Timer Control Register (Tcr)
When the OIE bit is cleared, this in- terrupt in disabled. OIE bit is cleared on hardware RESET and software reset (RESET in- struction). 7 - 6 16-BIT TIMER AND EVENT COUNTER MOTOROLA...
Page 190: Tcr Compare Interrupt Enable (Cie) Bit 10
8-bit decrement register. All 1 to 0 transitions of the TIN pin will then decre- ment the decrement register. When the INV is cleared, the external signal on TIN is not MOTOROLA 16-BIT TIMER AND EVENT COUNTER 7 - 7...
Page 191: Tcr Timer Enable (Te) Bit 15
74 ns 18.94 µs (27 MHz-13.5MIPS) 1.242 s FUNCTIONAL DESCRIPTION OF THE TIMER The figures given in this section illustrate most configurations in which the timer can be enabled, disabled and used. 7 - 8 16-BIT TIMER AND EVENT COUNTER MOTOROLA...
Page 192: Functional Description Of The Timer
Overflow Interrupt Figure 7-4 Standard Timer Operation with Overflow Interrupt disable timer Event DC7-DC0 Decrement XXXX XXXX-1 XXXX-1 Register Preload PRELOAD Register Counter YYYY PRELOAD Register Figure 7-5 Standard Timer Disable MOTOROLA 16-BIT TIMER AND EVENT COUNTER 7 - 9...
Page 193 DC-1 Register PRELOAD Preload Register Direct Value COUNT written to Count Register by DSP COUNT PRELOAD PRELOAD-1 PRELOAD Count Register Figure 7-7 Timer Disable After a Write to the Count Register 7 - 10 16-BIT TIMER AND EVENT COUNTER MOTOROLA...
Page 194 Preload PRELOAD Register Value to write to the count COUNT register Count PRELOAD COUNT PRELOAD XXXX Register Overflow Interrupt Figure 7-8 Write to the Count Register when the Timer is Enabled MOTOROLA 16-BIT TIMER AND EVENT COUNTER 7 - 11...
Page 195 DC7-DC0 Event DC7-DC0 Decrement DCx-1 Register Preload PRELOAD Register Count XXXX-1 XXXX XXXX-1 XXXX-2 PRELOAD Register Overflow Interrupt Figure 7-9 Write to DC7-DC0 when the Timer is Enabled 7 - 12 16-BIT TIMER AND EVENT COUNTER MOTOROLA...
Page 196 DC7-DC0 preload compare timer Event DC7-DC0 Decrement DC-1 Register Preload PRELOAD Register Compare COMP Register Counter PRELOAD PRELOAD-1 COMP COMP-1 Register Compare Interrupt Figure 7-10 Standard Timer Operation with Compare Interrupt MOTOROLA 16-BIT TIMER AND EVENT COUNTER 7 - 13...
Page 198: Synchronous Serial Interface (Ssi0 And Ssi1)
SECTION 8 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA 8 - 1...
Page 199 SSI OPERATING MODES ........8-24 8 - 2 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 200: Introduction
INTRODUCTION INTRODUCTION The DSP56156 contains two identical Synchronous Serial Interfaces (SSI’s) named SSI0 and SSI1. This section describes both. In cases where the text or a figure applies equally to both SSI’s, they will be referred to as the SSI. In cases where the information differs between the SSI’s such as when pin numbers are mentioned, control addresses are men-...
Page 201: Ssi Clock And Frame Sync Generation
SCKx and FS don’t have to be in the same direction. Note that the first pin name in these figures apply to SSI0 and the second applies to SSI1 i.e., PC2/PC7 means PC2 for SSI0 and PC7 for SSI1. 8 - 4 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 202: Ssix Data And Control Pins
SSIx DATA AND CONTROL PINS PC0/PC5 STDx PC1/PC6 SRDx DSP56156 PC2/PC7 SCKx PC3/PC8–SC1x CODEC PC4/PC9–SC0x Figure 8-1 SSIx Internal Clock, Synchronous Operation PC0/PC5 STDx PC1/PC6 SRDx DSP56156 PC2/PC7 SCKx CODEC PC3/PC8–SC1x PC4/PC9–SC0x Figure 8-2 SSIx External Clock, Synchronous Operation PC0/PC5...
Page 203 SSIx DATA AND CONTROL PINS DSP56156 CODEC TDC/RDC STDx PC0/PC5 SRDx TDE/RDE PC1/PC6 SCKx PC2/PC7 PC3/PC8–SC1x PC4/PC9–SC0x CODEC TDC/RDC TDE/RDE Figure 8-5 SSIx Internal Clock, Synchronous Operation Dual Codec Interface Figure 8-6 shows the internal clock path connections in block diagram form. The serial bit clock can be internal or external depending on SCKD bit in the control register.
Page 204: Serial Transmit Data Pin - Stdx
OF1 in CRB. When SCIx is configured as an input or output (with synchronous or asynchronous operations), this pin will update status bit IF1 of the SSI status register as described in Section 8.13.1. MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 7...
Page 205: Serial Control - Sc0X
This reset is generated by either the DSP hardware reset (generated by asserting the RESET pin) or software reset (generated by executing the RESET instruction). The DSP reset clears the Port Control Register bits, 8 - 8 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 206: Ssix Interface Programming Model
Codec devices label the Most Significant Bit as bit 0, whereas the DSP labels the LSB as bit 0. Therefore, when using a standard Codec (requiring LSB first), the SHFD bit in the CRB should be cleared (MSB first). MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 9...
Page 207: Ssi Transmit Shift Register
SERIAL TRANSMIT SHIFT REGISTER HIGH BYTE LOW BYTE (Cannot be accessed directly) WRITE-ONLY SERIAL TRANSMIT REGISTER HIGH BYTE LOW BYTE (SSI0 Address X:$FFF1 SSI1 Address X:$FFF9) Figure 8-8 SSIx Programming Model 8 - 10 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 208 15 14 13 12 11 10 REGISTERS SSI0: $FFF4 TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS SSI1: $FFFC Figure 8-8 SSIx Programming Model (Continued) MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 11...
Page 209: Ssi Transmit Data Register (Tx)
SSI. The CRA controls the SSI clock generator bit and frame sync rates, word length, and number of words per frame for the serial data. The DSP reset 8 - 12 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 210: Cra Prescale Modulus Select (Pm0
In normal mode, this ratio determines the word transfer rate. The divide ratio may range from 1 to 32 (DC = 00000 to 11111) for normal mode and 2 to 32 (DC = 00001 to 11111) for network mode. MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 13...
Page 211: Cra Word Length Control (Wl0,Wl1) Bits 13, 14
The Word Length Control bits are used to select the length of the data words being trans- ferred via the SSI. Word lengths of 8, 12, or 16 bits may be selected as shown in Table 8-3. 8 - 14 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 212: Cra Prescaler Range (Psr) Bit 15
When PSR is cleared the fixed prescaler is bypassed. When PSR is set the fixed divide-by-8 prescaler is operational. This allows a 128kHz master clock to be generated for Motorola codecs. The maximum internally generated bit clock frequency is Fosc/4 and the minimum internally generated bit clock frequency is Fosc/(4*8*256).
Page 213: Crb Serial Output Flag 0 And 1 (Of0, Of1) Bit 0, 1
Illegal for on-demand Sync FS out (Reserved) Sync F1 out F0 out Flags used for sync as in Figure 8-5 RFS: Receive Frame Sync; TFS: Transmit Frame Sync; FS: Frame Sync 8 - 16 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 214: Crb A/Mu Law Selection Bit (A/Mu) Bit 3
The Frame Sync Invert (FSI) bit selects the logic of frame sync I/O and I/O flag pins. If FSI=1, the frame sync or flag pins are active low. If FSI=0, the frame sync or flag pins are active high. MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 17...
Page 215: Crb Sync/Async (Syn) Bit 10
Note: RE does not inhibit RDF or receiver interrupts. RE does not affect the generation of a frame sync. 8 - 18 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 216: Ssi Status Register (Ssisr)
The SSI Status Register is an 8-bit read only status register used by the DSP to interro- gate the status and serial input flags of the SSI. The status bits are described in the fol- lowing paragraphs. MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 19...
Page 217 In network mode, if the first slot is disabled, this flag will be set after reception in the first active slot and will only be cleared after receiving the next enabled time slot into the RX register. 8 - 20 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 218 Register are transferred to the Transmit Shift Register.When set, TDE indicates that data should be written to the TX or to the TSR before the transmit shift register becomes empty (which would cause an underrun error). MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 21...
Page 219: Time Slot Register - Tsr
When bit number N in TSMx is set, the transmit sequence is as usual: data is transferred from TX to the shift register, it is transmitted during transmit time slot number N, and the TDE flag is set. 8 - 22 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 220: Transmit Slot Mask Shift Register - Tsms
When bit number N in RSMx is set, the receive sequence is as usual: data which is shifted into the receive shift register is transferred to the Receive Data register and the RDF flag is set. MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 23...
Page 221: Receive Slot Mask Shift Register - Rsms
TFS In RFS Out TFS Out RFS In TFS Out Sync — FS In — FS Out On-Demand Async RFS Out TFS Out RFS In TFS Out Sync — FS Out 8 - 24 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 222 The receiver is treated in the same manner except that data is always being shifted into the MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)
Page 223 To summarize, the network mode transmitter generates interrupts every enabled time slot (TE=1, TIE=1) and requires the DSP program to respond to each enabled time slot. These responses may be: 8 - 26 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 224 A divide ratio of one (DC=00000) in the network mode is a special case. This is the only data driven mode of the SSI and is defined as the on-demand mode. This special case MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)
Page 225 Data transmission is data driven and is enabled by writing data into the TX register. Receive and transmit interrupts function with the TDE and RDF flags as normally; however, transmit underruns (TUE) are impossible for on-demand transmission. 8 - 28 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 226 SECTION 8 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA 8 - 1...
Page 227 SSI OPERATING MODES ........8-24 8 - 2 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 228: Introduction
INTRODUCTION INTRODUCTION The DSP56156 contains two identical Synchronous Serial Interfaces (SSI’s) named SSI0 and SSI1. This section describes both. In cases where the text or a figure applies equally to both SSI’s, they will be referred to as the SSI. In cases where the information differs between the SSI’s such as when pin numbers are mentioned, control addresses are men-...
Page 229: Ssi Clock And Frame Sync Generation
SCKx and FS don’t have to be in the same direction. Note that the first pin name in these figures apply to SSI0 and the second applies to SSI1 i.e., PC2/PC7 means PC2 for SSI0 and PC7 for SSI1. 8 - 4 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 230 SSIx DATA AND CONTROL PINS PC0/PC5 STDx PC1/PC6 SRDx DSP56156 PC2/PC7 SCKx PC3/PC8–SC1x CODEC PC4/PC9–SC0x Figure 8-1 SSIx Internal Clock, Synchronous Operation PC0/PC5 STDx PC1/PC6 SRDx DSP56156 PC2/PC7 SCKx CODEC PC3/PC8–SC1x PC4/PC9–SC0x Figure 8-2 SSIx External Clock, Synchronous Operation PC0/PC5...
Page 231 SSIx DATA AND CONTROL PINS DSP56156 CODEC TDC/RDC STDx PC0/PC5 SRDx TDE/RDE PC1/PC6 SCKx PC2/PC7 PC3/PC8–SC1x PC4/PC9–SC0x CODEC TDC/RDC TDE/RDE Figure 8-5 SSIx Internal Clock, Synchronous Operation Dual Codec Interface Figure 8-6 shows the internal clock path connections in block diagram form. The serial bit clock can be internal or external depending on SCKD bit in the control register.
Page 232 OF1 in CRB. When SCIx is configured as an input or output (with synchronous or asynchronous operations), this pin will update status bit IF1 of the SSI status register as described in Section 8.13.1. MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 7...
Page 233: Ssi Reset And Initialization Procedure
This reset is generated by either the DSP hardware reset (generated by asserting the RESET pin) or software reset (generated by executing the RESET instruction). The DSP reset clears the Port Control Register bits, 8 - 8 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 234: Ssix Interface Programming Model
Codec devices label the Most Significant Bit as bit 0, whereas the DSP labels the LSB as bit 0. Therefore, when using a standard Codec (requiring LSB first), the SHFD bit in the CRB should be cleared (MSB first). MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 9...
Page 235: Ssi Transmit Shift Register
SERIAL TRANSMIT SHIFT REGISTER HIGH BYTE LOW BYTE (Cannot be accessed directly) WRITE-ONLY SERIAL TRANSMIT REGISTER HIGH BYTE LOW BYTE (SSI0 Address X:$FFF1 SSI1 Address X:$FFF9) Figure 8-8 SSIx Programming Model 8 - 10 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 236 15 14 13 12 11 10 REGISTERS SSI0: $FFF4 TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS SSI1: $FFFC Figure 8-8 SSIx Programming Model (Continued) MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 11...
Page 237: Ssi Transmit Data Register (Tx)
SSI. The CRA controls the SSI clock generator bit and frame sync rates, word length, and number of words per frame for the serial data. The DSP reset 8 - 12 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 238 In normal mode, this ratio determines the word transfer rate. The divide ratio may range from 1 to 32 (DC = 00000 to 11111) for normal mode and 2 to 32 (DC = 00001 to 11111) for network mode. MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 13...
Page 239 The Word Length Control bits are used to select the length of the data words being trans- ferred via the SSI. Word lengths of 8, 12, or 16 bits may be selected as shown in Table 8-3. 8 - 14 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 240: Ssi Control Register B (Crb)
When PSR is cleared the fixed prescaler is bypassed. When PSR is set the fixed divide-by-8 prescaler is operational. This allows a 128kHz master clock to be generated for Motorola codecs. The maximum internally generated bit clock frequency is Fosc/4 and the minimum internally generated bit clock frequency is Fosc/(4*8*256).
Page 241 Illegal for on-demand Sync FS out (Reserved) Sync F1 out F0 out Flags used for sync as in Figure 8-5 RFS: Receive Frame Sync; TFS: Transmit Frame Sync; FS: Frame Sync 8 - 16 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 242 The Frame Sync Invert (FSI) bit selects the logic of frame sync I/O and I/O flag pins. If FSI=1, the frame sync or flag pins are active low. If FSI=0, the frame sync or flag pins are active high. MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 17...
Page 243 Note: RE does not inhibit RDF or receiver interrupts. RE does not affect the generation of a frame sync. 8 - 18 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 244: Ssi Status Register (Ssisr)
The SSI Status Register is an 8-bit read only status register used by the DSP to interro- gate the status and serial input flags of the SSI. The status bits are described in the fol- lowing paragraphs. MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 19...
Page 245 In network mode, if the first slot is disabled, this flag will be set after reception in the first active slot and will only be cleared after receiving the next enabled time slot into the RX register. 8 - 20 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 246 Register are transferred to the Transmit Shift Register.When set, TDE indicates that data should be written to the TX or to the TSR before the transmit shift register becomes empty (which would cause an underrun error). MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 21...
Page 247: Time Slot Register - Tsr
When bit number N in TSMx is set, the transmit sequence is as usual: data is transferred from TX to the shift register, it is transmitted during transmit time slot number N, and the TDE flag is set. 8 - 22 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 248: Transmit Slot Mask Shift Register - Tsms
When bit number N in RSMx is set, the receive sequence is as usual: data which is shifted into the receive shift register is transferred to the Receive Data register and the RDF flag is set. MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 23...
Page 249: Receive Slot Mask Shift Register - Rsms
TFS In RFS Out TFS Out RFS In TFS Out Sync — FS In — FS Out On-Demand Async RFS Out TFS Out RFS In TFS Out Sync — FS Out 8 - 24 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 250 The receiver is treated in the same manner except that data is always being shifted into the MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)
Page 251 To summarize, the network mode transmitter generates interrupts every enabled time slot (TE=1, TIE=1) and requires the DSP program to respond to each enabled time slot. These responses may be: 8 - 26 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 252 A divide ratio of one (DC=00000) in the network mode is a special case. This is the only data driven mode of the SSI and is defined as the on-demand mode. This special case MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)
Page 253 Data transmission is data driven and is enabled by writing data into the TX register. Receive and transmit interrupts function with the TDE and RDF flags as normally; however, transmit underruns (TUE) are impossible for on-demand transmission. 8 - 28 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA...
Page 254 SECTION 9 ON-CHIP FREQUENCY SYNTHESIZER Φ ∫ x x d MOTOROLA 9 - 1...
Page 255 ON-CHIP CLOCK SYNTHESIS EXAMPLES......9-5 ON-CHIP CLOCK SYNTHESIS CONTROL REGISTER PLCR ..9-7 9 - 2 ON-CHIP FREQUENCY SYNTHESIZER MOTOROLA...
Page 256 The DSP56156 does not contain an on-chip oscillator. An external system clock must be connected to the EXTAL pin. Figure 9-1 shows the on-chip frequency synthesizer gen- eral block diagram.This clock, after being squared, can be divided on-chip by a four bit...
Page 257 (PLLD=0) when entering the STOP mode. STOP will power down the ED register and the CLKO circuitry if the PLL is disabled (PLLD=1) and if the CLKO is turned off (CD=0 in OMR) when entering the STOP mode (see section 9.3.5). 9 - 4 ON-CHIP FREQUENCY SYNTHESIZER MOTOROLA...
Page 258 10MHz and higher than the maximum DSP core operating frequency. The PLL can also be disabled (PLLE=0), in which case the core will directly use the 13 MHz clock and will run at 6.5 MIPS. MOTOROLA ON-CHIP FREQUENCY SYNTHESIZER 9 - 5...
Page 259 In the second example, the 4-bit input divider divides the input clock by 5 providing a 1.944 MHz clock to the Σ∆ codec and to the PLL. The PLL can multiply the 1.944 MHz clock up 9 - 6 ON-CHIP FREQUENCY SYNTHESIZER MOTOROLA...
Page 260 Voltage Controlled Oscillator (VCO) can relock. Any time a new value is written to the YD bits, the LOCK bit is cleared. The resulting DSP core system clock must be within the limits specified by DSP56156 technical data sheet.
Page 261 PLLD bit: when the PLLD bit is set, the PLL is in the power down mode and when the PLLD bit is cleared, the PLL is in the active mode. Table 9-2 summarizes the function of PLLE and PLLD. 9 - 8 ON-CHIP FREQUENCY SYNTHESIZER MOTOROLA...
Page 262 PLLE bit unless PLLD, YD, and ED are also changed. This bit is read-only and can- not be written by the DSP core. 9.3.8 PLCR Reserved Bits (Bits 8-9,12) These bits are reserved and should be written as zero by the user. They read as a logic zero. MOTOROLA ON-CHIP FREQUENCY SYNTHESIZER 9 - 9...
Page 263 PLL multiplies the clock by 48 PLL multiplies the clock by 52 PLL multiplies the clock by 56 PLL multiplies the clock by 60 PLL multiplies the clock by 64 Figure 9-3 On-chip Frequency Synthesizer Programming Model Summary 9 - 10 ON-CHIP FREQUENCY SYNTHESIZER MOTOROLA...
Page 264 1000101010100100 0100010101011101 1010100011010101 1001011001110100 0100101001011010 1010101010110110 1010100011010101 1001011001110100 10110111011010011010010101 1000101010100100 0100010101011101 1010101010010111 0101001010010111 0100101001011010 1010101010110110 1010100011010101 1001011001110100 1000101010100100 0100010101011101 01010 10110111011010011010010101 1010101010010111 0101001010010111 1010100011010101 1001011001110100 1000101010100100 0100010101011101 01010 1010100011010101 1001011001110100 1000101010100100 0100010101011101 10110111011010011010010101 1010100011010101 1001011001110100 01010 MOTOROLA A - 1...
Page 265 BOOTSTRAP ROM..........A-3 A - 2 BOOTSTRAP MODE — OPERATING MODE 0 OR 1 MOTOROLA...
Page 266 Mode 0 or 1. The control logic maps the bootstrap ROM into program memory space as long as the DSP56156 remains in Operating Mode 0 or Mode 1. If the DSP is in Operating Mode 0 it will load 4096 bytes from a byte-wide memory (usually an EPROM) beginning at location P:$C000.
Page 267 JMP #<00 (e.g., see Bootstrap code for DSP56156) to begin the bootstrap process as described above in steps 1-4. This technique allows the DSP56156 user to reboot the system (with a different program if desired).
Page 268 ; (C) Copyright 1989 Motorola Inc. ; Host Bootstrap, SSI0 Bootstrap and External Bus Bootstrap ; This is the Bootstrap program contained in the DSP56156 RAM based part. This program ; can load the internal program memory from one of 3 external sources.
Page 269 ; Shift 4 bit data into A1 ASR4 ; Shift 4 bit data into A1 _LOOP2 <_STORE ; Then put the word in P: memory Figure A-1 Listing of the DSP56156 Bootstrap Program (Continued) A - 6 BOOTSTRAP MODE — OPERATING MODE 0 OR 1 MOTOROLA...
Page 270 ; Clear SR as if HW reset and ; introduce delay needed for ; operating mode change. <$0 ; Start fetching from PRAM. Figure A-1 Listing of the DSP56156 Bootstrap Program (Continued) MOTOROLA BOOTSTRAP MODE — OPERATING MODE 0 OR 1 A - 7...
Page 272 APPENDIX B DSP56156 APPLICATION EXAMPLES MOTOROLA B - 1...
Page 273 SECTION CONTENTS B - 2 DSP56156 APPLICATION EXAMPLES MOTOROLA...
Page 274 The lowest cost DSP56156-based system is shown in Figure B-1. This system uses no run time external memory and requires only two chips; the DSP56156 and a low cost EPROM. Figure B-2 shows the DSP56156 bootstrapping via the Host Interface from an MC68000.
Page 275 Systems with external program memory can load the on-chip PRAM without using the bootstrap mode. In Figure B-3, the DSP56156 is operated in mode 2 with the reset vector at external program memory at location $E000. The programmer can overlay the high speed on-chip PRAM with DSP algorithms by using the MOVEM instruction.
Page 276 • • TRIGGER • MASTER 1 µ f CONTROL OUTPUT RESET 0.1 µ f 0.47 µ f • • LOGIC RESET RESET 74LS04 OnCE Connector Reset_IN Figure B-5 Reset Circuit Using 555 Timer MOTOROLA DSP56156 APPLICATION EXAMPLES B - 5...
Page 278 INDEX MOTOROLA INDEX - 1...
Page 279 Codec Receive Data Register ..6-6 Bootstrap Program Listing ..15 Bootstrap ROM ....3-6 MOTOROLA INDEX - 3...
Page 280 Bit 15 ....8-19 DSP to Host ....5-20 INDEX - 4 MOTOROLA...
Page 281 Host to DSP ....5-19 ISR Host Request (HREQ) Bit 7 . . . 5-17 Host Transmit Data Register ..5-5 MOTOROLA INDEX - 5...
Page 282 Normal Operating Mode ..8-25 Port B ......4-6 INDEX - 6 MOTOROLA...
Page 283 .....7-5 SSI Transmit Slot Mask ... .60 Timer Control Register ... . 7-3 MOTOROLA INDEX - 7...
Page 284 XDB ......1-7 —Y— YD3-YD0 ..... . . 9-4 INDEX - 8 MOTOROLA...
Page 285 The following pages are a set of programming sheets intended to be copied and used to simplify programming the various programmable registers in the DSP56156. These programming sheets are grouped for the core processor and each peripheral. Each register includes the name, address, reset value, and meaning of each bit. There is room to write in the value for each bit and also the hexadecimal equivalent for each register.
Page 286 C.11 SSI ............C-34 C - 2 PROGRAMMING SHEETS MOTOROLA...
Page 287 DSP56156 On-chip Peripheral Memory Map PERIPHERAL ADDRESSES $FFFF Reserved for on-chip emulation $FFDF IPR: Interrupt Priority Register $FFFE $FFDE BCR: Bus Control Register $FFFD TSMB1 SSI1 Register $FFDD reserved for future use $FFFC TSMA1 SSI1 Register $FFDC PLCR $FFFB RSMB1 SSI1 Register...
Page 288 DSP56156 Interrupts Starting Addresses and Sources INTERRUPT VECTOR ADDRESSES Table C-1 Interrupts Starting Addresses and Sources Interrupt Starting Address IPL Interrupt Source $0000 Hardware RESET $0002 Illegal Instruction $0004 Stack Error $0006 Reserved $0008 $000A IRQA $000C IRQB $000E Reserved...
Page 289 DSP56156 Instruction Set Summary INSTRUCTIONS Table C-2 Instruction Set Summary — Sheet 1 of 3 Mnemonic Syntax Parallel Moves Instruction Osc. Program Clock Words Cycles S LE UNZVC (parallel move) ..1 2+mv * * * * * * * –...
Page 290 DSP56156 Instruction Set Summary INSTRUCTIONS Table C-2 Instruction Set Summary — Sheet 2 of 3 Mnemonic Syntax Parallel Moves Instruction Osc. Program Clock Words Cycles S LE UNZVC X:(Rn),expr ....2...
Page 291 DSP56156 Instruction Set Summary INSTRUCTIONS Table C-2 Instruction Set Summary — Sheet 3 of 3 Mnemonic Syntax Parallel Moves Instruction Osc. Program Clock Words Cycles S LE UNZVC MOVE(M) P:<ea>,D ....1+ea...
Page 292 DSP56156 Functional Instruction Set Summary INSTRUCTIONS Table C-3 Dual Read Instructions DSP56156 DOUBLE DATA ALU DOUBLE EFFECTIVE OPERATION DESTINATION ADDRESS Oper. Reg. Read1 Read2 Dest1 Dest2 MOVE (Rn)+ (R3)+ MAC/R X1,Y1,F (Rn)+Nn (R3)+ MPY/R X1,Y0,F (Rn)+ (R3)+N3 X0,Y1,F X0,Y0,F (Rn)+Nn...
Page 293 DSP56156 Functional Instruction Set Summary INSTRUCTIONS Table C-5 Data ALU Instructions with One Parallel Operation DSP56156 PARALLEL MEMORY DATA ALU READ or WRITE OPERATION Oper. Reg. Eff. Address Dest/Source ± X0,X0,F (Rn)+ ± X1,X0,F (Rn)+Nn ± A1,Y0,F (~F1) ± B1,X0,F (R2+xx) ±...
Page 294 DSP56156 Functional Instruction Set Summary INSTRUCTIONS Table C-6 Bit Field Manipulation Instructions DSP56156 OPERATION OPERAND COMMENTS BFTSTH #iiii, X:(Rn) n=[0,3] BFTSTL #iiii, X:<aa> first 32 word of X mem- BFCHG #iiii, BFSET #iiii, 5 bit address BFCLR #iiii, X:<pp> last 32 word of X mem-...
Page 295 DSP56156 Functional Instruction Set Summary INSTRUCTIONS Table C-8 Jump/branch Instructions DSP56156 OPERATION OPERAND COMMENTS (Rn) n=[0,3] $xxxx 16-bit absolute address JScc (Rn) n=[0,3] $xxxx 16-bit absolute address BScc 8-bit absolute address [0,256] 8-bit PC relative address [-128,+127] 6-bit PC relative...
Page 296 DSP56156 Functional Instruction Set Summary INSTRUCTIONS Table C-10 Short Immediate Move Instructions DSP56156 OPERATION DESTINATION COMMENTS MOVE(I) #xx, immediate short 8 bit signed data (data is put in the LSByte) Table C-11 Move — Program and Control Instructions DSP56156 OPERATION Source/Dest.
Page 297 DSP56156 Functional Instruction Set Summary INSTRUCTIONS Table C-12 Move Absolute Short and Move Peripheral Instructions DSP56156 OPERATION Source/Dest. Dest./Source COMMENTS MOVE(S) X:<aa> A, B, first 32 word of X X0, Y0 memory 5 bit address A, B, last 32 word of X MOVE(P) X:<pp>...
Page 298 DSP56156 Functional Instruction Set Summary INSTRUCTIONS Table C-15 Register Transfer Conditional Move Instruction DSP56156 OPERATION Data ALU Address Reg. A, F R0,R0 B, F R0,Rm Y0, F X0, F Table C-16 Conditional Program Controller Instructions DSP56156 OPERATION BRKcc DEBUGcc Table C-17...
Page 299 DSP56156 Functional Instruction Set Summary INSTRUCTIONS Table C-18 Double Precision Data Alu Instructions DSP56156 DATA ALU OPERATION Operation sign unsign DMAC MPY(su,uu) MAC(su,uu) Table C-19 Integer Data ALU Instructions DSP56156 DATA ALU OPERATION Operation IMAC X0,X0,F X1,X0,F IMPY A1,Y0,F B1,X0,F...
Page 300 DSP56156 Functional Instruction Set Summary INSTRUCTIONS Table C-21 Other Data ALU Instructions DSP56156 OPERATION Norm Rn,F n=[0,3] TST2 X1,X0,Y1,Y0 Test data registers CHKAAU Set V,N,Z according to last address ALU operation ZERO zero F from bit 32 to 39 s. ext. F from bit 31 to 39...
Page 301 DSP56156 Functional Instruction Set Summary INSTRUCTIONS Table C-22 Special Instructions DSP56156 OPERATION WAIT STOP ENDDO RESET DEBUG MOTOROLA PROGRAMMING SHEETS C - 17...
Page 302 DSP56156 Core Programming Sheet Date: Application: Programmer: Sheet 1 of 3 CORE Program Memory Wait States Set to zero for fast memory. Data Memory Wait States Set to zero for fast memory. Bus State Status — Read Only 0 = DSP NOT a Bus Master...
Page 303 DSP56156 Core Programming Sheet Date: Application: Programmer: Sheet 2 of 3 CORE IRQA Mode IAL1 IAL0 Enabled IPL IAL2 Trigger — Level Neg. Edge IRQB Mode IBL1 IBL0 Enabled IPL IBL2 Trigger — Level Neg. Edge Codec IPL 0 = Lowest Level...
Page 304 DSP56156 Core Programming Sheet Date: Application: Programmer: Sheet 3 of 3 CORE Operating Mode 00 = Boot: Byte-wide at P:$C000 01 = Boot: Host or SSI0 10 = Int. Mem; Reset at P:$E000 11 = Ext. Mem; Reset at P:$0000...
Page 305 DSP56156 Phase Locked Loop Programming Sheet Date: Application: Programmer: Sheet 1 of 1 P.L.L. Input Divider Divides Clock Frequency by 1 to 16 Feedback Divider Multiplies Clock Frequency by 4 to 64; Increments of 4 Clockout Select CS1 CS0 CLKOUT...
Page 306 DSP56156 Phase Locked Loop Programming Sheet ÷ 6.5 CODEC EXTAL P.L.L. ÷ 1 to ÷ 16 PLLE=1 PHASE ED3-ED0 Filter COMP. Fosc 4-bit VCO down counter PLLE=0 ÷ 1 to ÷ 16 ÷4 CS1-CS0 CLKO YD3-YD0 ÷ 2 internal phase PH0 at Fosc...
Page 307 DSP56156 Timer Programming Sheet Date: Application: Programmer: Sheet 1 of 1 Timer Timer Output Enable Compare Interrupt Enable 000 = TOUT Disabled 0 = Disable interrupt 001 = Compare/Overﬂow Pulse 1 = Interrupt DSP after TCTR = TCPR 010 = Overﬂow Pulse 011 = Compare Pulse Overﬂow Interrupt Enable...
Page 308 Reset = $0000 Figure C-10 Timer Compare Register (TCPR) Number to Load into Count Register 15 14 13 12 11 10 Timer Preload Register (TPR) X:$FFEF Read/Write Reset = $0000 Figure C-11 Timer Preload Register (TPR) C - 24 PROGRAMMING SHEETS MOTOROLA...
Page 309 DSP56156 Codec Programming Sheet Date: Application: Programmer: Sheet 1 of 2 Codec Input Select Codec Ratio Select Bits Microphone Gain Audio Level Control Bits Ratio A/D (dB) D/A (dB) 0 = MIC Selected Select Bits 0000 = -20dB 1000 = 00 = 125 -0.618...
Page 310 Reset = $0000 Figure C-13 Transmit Data Register (CTX) Read Under Program Control 15 14 13 12 11 10 Receive Data Register (CRX) X:$FFE9 Read Only Reset = $0000 Figure C-14 Receive Data Register (CRX) C - 26 PROGRAMMING SHEETS MOTOROLA...
Page 311 DSP56156 General Purpose I/O Programming Sheet Date: Application: Programmer: Sheet 1 of 2 GP I/O Port B Port B Control 0 = General Purpose I/O 1 = Host Interface 15 14 13 12 11 10 Port B * * * * * * * * * * * * * * *...
Page 312 DSP56156 General Purpose I/O Programming Sheet Date: Application: Programmer: Sheet 2 of 2 GP I/O Port C Port C Pin Control 0 = General Purpose I/O Pin 1 = Peripheral Pin 15 14 13 12 11 10 Port C * * *...
Page 313 DSP56156 Host Programming Sheet Date: Application: Programmer: Sheet 1 of 5 HOST Port B Port B Control 0 = General Purpose I/O 1 = Host Interface 15 14 13 12 11 10 9 Port B * * * * * * * * * * * * * * *...
Page 314 DSP56156 Host Programming Sheet Date: Application: Programmer: Sheet 2 of 5 HOST HOST – DSP SIDE Host Receive Data Full 0 = ∏ Wait 1 = ∏ Read Host Transmit Data Empty 0 = ∏ Wait 1 = ∏ Write Host Command Pending 0 = ∏...
Page 315 DSP56156 Host Programming Sheet Date: Application: Programmer: Sheet 3 of 5 HOST HOST – HOST PROCESSOR SIDE Receive Request Enable 0 = ∏ Interrupts Disabled DMA Off 1 = Interrupts Enabled 0 = Host → DSP 1 = DSP → Host...
Page 316 DSP56156 Host Programming Sheet Date: Application: Programmer: Sheet 4 of 5 HOST HOST – HOST PROCESSOR SIDE Receive Data Register Full 0 = Wait 1 = Read Transmit Data Register Empty 0 = Wait 1 = Write Transmitter Ready 0 = Data in HI 1 = Data Not in HI...
Page 317 Transmit Byte Registers 15 14 13 12 11 10 $6, $7 Write Only H I G H B Y T E L O W B Y T E Reset = $xxxx Figure C-31 Transmit Byte Registers MOTOROLA PROGRAMMING SHEETS C - 33...
Page 318 DSP56156 SSI Programming Sheet Date: Application: Programmer: Sheet 1 of 5 SSI Port C Pin Control 0 = General Purpose I/O Pin 1 = SSI Pin 15 14 13 12 11 10 PORT C * * * CC11 CC10 CC9 CC8 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0...
Page 319 DSP56156 SSI Programming Sheet Date: Application: Programmer: Sheet 2 of 5 SSI Receive Slot Mask 0 = Ignore Time Slot 1 = Active Time Slot 15 14 13 12 11 10 SSI Receive Slot Mask RS15 RS14 RS13 RS12 RS11 RS10 RS9...
Page 320 SSI Transmit Slot Mask TS31 TS30 TS29 TS28 TS27 TS26 TS25 TS24 TS23 TS22 TS21 TS20 TS19 TS18 TS17 TS16 TSMBx SSI0: $FFF5 Read/Write SSI1: $FFFD Read/Write Reset = $FFFF Figure C-38 SSI Transmit Slot Mask C - 36 PROGRAMMING SHEETS MOTOROLA...
Page 321 DSP56156 SSI Programming Sheet Date: Application: Programmer: Sheet 4 of 5 Word Length Control 00 = 8 Bits/Word 01 = 8 with Log Exp/Comp 10 = 12 Bits/Word 11 = 16 Bits/Word Prescaler Range Frame Rate Divider Control 0 = / 1...
Page 322 DSP56156 SSI Programming Sheet Date: Application: Programmer: Sheet 5 of 5 Serial Input Flags IF1 = SC1x IF0 = SC0x Transmit Frame Sync 0 = ∏ Sync Inactive1 = ∏ Sync Active Receive Frame Sync 0 = ∏ Wait 1 = ∏ Read RX Transmitter Underrun Error 0 = ∏...
Page 323 INDEX MOTOROLA INDEX - 1...
Page 324 Codec Receive Data Register ..6-6 Bootstrap Program Listing ..15 Bootstrap ROM ....3-6 MOTOROLA INDEX - 3...
Page 325 Bit 15 ....8-19 DSP to Host ....5-20 INDEX - 4 MOTOROLA...
Page 326 Host to DSP ....5-19 ISR Host Request (HREQ) Bit 7 . . . 5-17 Host Transmit Data Register ..5-5 MOTOROLA INDEX - 5...
Page 327 Normal Operating Mode ..8-25 Port B ......4-6 INDEX - 6 MOTOROLA...
Page 328 .....7-5 SSI Transmit Slot Mask ... .60 Timer Control Register ... . 7-3 MOTOROLA INDEX - 7...
Page 329 XDB ......1-7 —Y— YD3-YD0 ..... . . 9-4 INDEX - 8 MOTOROLA...

Motorola DSP56156 Manual

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Section 1

Section 2

Section 3

Section 4

Section 5

Section 6

Section 7

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Table of Contents