Page 1 Data Book 32bit Micro controller TLCS-900/H1 series TMP92CZ26AXBG TENTATIVE It’s first version technical data sheet. Since this revision 0.2 is still under working, there may be some mistakes in it. When you will start to design, please order the latest one.
Page 2 TLCS-900/H1 Devices TMP92CZ26A 1. Outline and Features ････････････････････････････････････････ 92CZ26A-1 2. Pin Assignment and Pin Functions ････････････････････････････ 92CZ26A-6 2.1 Pin Assignment Diagram ････････････････････････････････ 92CZ26A-6 2.2 Pin names and Functions ･･･････････････････････････････ 3. Operation ･･････････････････････････････････････････････････ 92CZ26A-14 3.1 CPU ･･･････････････････････････････････････････････････ 92CZ26A-14 3.2 Memory Map ･･････････････････････････････････････････ 3.3 Clock Function and Standby Function ････････････････････...
Page 3 3.12 8 bit timers (TMRA) ･･････････････････････････････････ 3.13 16 bit timer (TMRB) ･･････････････････････････････････ 92CZ26A-294 3.14 Serial channel (SIO) ･･････････････････････････････････ 92CZ26A-315 3.15 Serial Bus Interface (SBI) ･････････････････････････････ 92CZ26A-344 3.16 USB controller ･･････････････････････････････････････ 3.17 SPIC (SPI controller) ･････････････････････････････････ 3.18 I2S ･････････････････････････････････････････････････ 3.19 LCD controller (LCDC) ･･･････････････････････････････ 3.20 Touch screen interface (TSI) ･･････････････････････････...
Page 4 Outline and Features TMP92CZ26A is high-speed advanced 32-bit micro-controller developed for controlling equipment which processes mass data. TMP92CZ26AXBG is housed in a 228-pin BGA package. (1) CPU : 32-bit CPU(High-speed 900/H1 CPU) • Compatible with TLCS-900/L1 instruction code • 16Mbytes of linear address space •...
Page 5 (4) External memory expansion • Expandable up to 3.1G bytes (shared program/data area) • Can simultaneously support 8/16-bit width external data bus …… Dynamic data bus sizing • Separate bus system (5) Memory controller • Chip select output • One channel in 4 channels is enabled detailed AC enable setting (6) 8-bit timers (7) 16-bit timer/event counter (8) General-purpose serial interface : 1 channels...
Page 6 (17) Touch screen interface • Built-in Switch of Low-resistor, and available to delete external components for shift change row/column (18) Watch dog timer (19) Melody/alarm generator • Melody: Output of clock 4 to 5461Hz • Alarm: Output of the 8 kinds of alarm pattern •...
Page 7 (28) Stand-by function • Three Halt modes : IDLE2 (programmable), IDLE1, STOP • Each pin status programmable for stand-by mode • Built-in power supply management circuits (PMC) for leak current provision (29) Clock controller • Built-in two blocks of clock doubler (PLL). PLL supplies 48 MHz for USB and 80 MHz for CPU from 10MHz •...
Page 8 (AN0 to AN1)PG0 to PG1 10-bit 6ch (AN2, MX)PG2 (AN3, MY, ADTRG )PG3 Converter (AN4 to AN5)PG4 to PG5 AVCC, AVSS VREFH, VREFL Touch Screen (PX, INT4)P96 (PY)P97 (TSI) (TXD0)P90 SERIAL I/O (RXD0)P91 SIO0 (CTS0, SCLK0)P92 (I2S0CKO)PF0 (I2S0DO)PF1 (I2S0WS)PF2 (I2S1CKO)PF3 (I2S1DO)PF4 (I2S1WS)PF5 (SDA)PV6...
Page 9 2. Pin Assignment and Pin Functions The assignment of input/output pins for TMP92CZ26A, their names and functions are as follows; 2.1 Pin Assignment Diagram (Top View) Figure 2.1.1 shows the pin assignment of the TMP92CZ26A. C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D5 D6 D7 D8 D9 D10 D11 D12 D13 G1 G2 G3 G4...
Page 10 Ball Ball Pin name Dummy1 P73,EA24 PG2,AN2, MX PF4,I2S1DO PA6,KI6 PF7,SDCLK PA5,KI5 PJ4,SDLUDQM PA3,KI3 P85, CSZC PA1,KI1 PU6,LD22 DVCC1A5 P61,A17 PF1,I2S0DO P60,A16 PJ6,NDCLE P96,PX,INT4 PJ1, SDCAS , SRLUB P87, CSXB , P83, CS , CSXA P81, CS , SDCS PU7,LD23,EO_TRGOUT P72, WRLU , NDWE PU4,LD20 P70, RD...
Page 11 2.2 Pin names and Functions The names of the input/output pins and their functions are described below. Number of Pin name Pins D0 to D7 P10 to P17 D8 to D15 P40 to P47 Output A0 to A7 Output P50 to P57 Output A8 to A15 Output...
Page 12 Number Pin name of Pins Output CSZD Output Output Output CSXB Output Output TXD0 Output RXD0 Input SCLK0 Input Input INT4 Input Output Input Output PA0 to PA7 Input KI0 to KI7 Input INT0 Input INT1 Input TA0IN Input INT2 Input INT3 Input...
Page 13 Number of Pin name Pins I2S0CKO Output I2S0DO Output I2S0WS Output I2S0WS Output I2S1CKO Output I2S1WS Output Output SDCLK Output PG0 to PG1 Input AN0 to AN1 Input Input Input Output Input Input Output ADTRG Input PG4 to PG5 Input AN4 to AN5 Input Output...
Page 14 Number of Pin name Pins Output LCP0 Output Output LLOAD Output Output Output Output LVSYNC Output Output LHSYNC Input Output LGOE0 Output Output LGOE1 Output Output LGOE2 Output PL0 to PL7 Output LD0 to LD7 Output Output TA1OUT Output MLDALM Output Output Output...
Page 15 Number of Pin name Pins SPCLK Output PT0 to PT7 LD8 to LD15 Output PU0 to PU4,PU6 Output LD16 to LD20,LD22 LD21 Output LD23 Output EO_TRGOUT Output SCLK0 Output PV3 to PV4 Output PW0 to PW7 Output CLKOUT Output LDIV Output X1USB Input...
Page 16 Number of Pin name Pins D+, D- CLKOUT Output AM1,AM0 Input DBGE Input X1/X2 XT1/XT2 RESET Input VREFH Input VREFL Input − AVCC − AVSS − DVCC3A − DVCC3B − DVCC1A − DVCC1B − DVSSCOM − DVCC1C − DVSS1C − Dummy4-1 Table 2.2.2 shows the range of operational voltage for power supply pins.
Page 17 Operation This section describes the basic components, functions and operation of the TMP92CZ26A. 3.1 CPU The TMP92CZ26A contains an advanced high-speed 32-bit CPU (900/H1 CPU) 3.1.1 CPU Outline 900/H1 CPU is high-speed and high-performance CPU based on 900/L1 CPU. 900/H1 CPU has expanded 32-bit internal data bus to process Instructions more quickly.
Page 18 3.1.2 Reset Operation When resetting the TMP92CZ26A microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the X1=10MHz). At reset, since the clock doublers (PLL0) is bypassed and clock-gear is set to 1/16, system clock operates at 625 kHz(X1=10MHz).
Page 19 TMP92CZ26A W r i t e R e a d Figure 3.1.1 TMP92CZ26A Reset timing chart 92CZ26A-16...
Page 20 This LSI has the restriction for the order of supplying power. Be sure to supply external 3.3V power with 1.5V power is supplied. Power On DVCC1A 1.5V DVCC1B Power DVCC1C After 1.5V power supply is rising, set 3.3V to ON. 3.3V DVCC3A Power...
Page 21 3.1.3 Setting of AM0 and AM1 Set AM1 and AM0 pins as Table 3.1.2 shows according to system usage. Table 3.1.2 Operation Mode Setup Table Mode Setup input pin RESET Operation Mode DBGE Debug mode 16-bit external bus starting Test mode (Prohibit to set) Test mode (Prohibit to set) BOOT(32-bit internal-MROM ) starting...
Page 22: Memory Map
3.2 Memory Map Figure 3.2.1 is a memory map of the TMP92CZ26A. 000000H 000100H 001FF0H 002000H 010000H 046000H (Internal Back Up RAM 16kbyte) 04A000H F00000H Provisional Emulator Control Area F10000H FFFF00H Vector table (256 Byte) FFFFFFH Note1: Don’t use specified 64kbyte area of above 16M byte when using debug mode. This is because the area is reserved for control in the debug mode.
Page 23 3.3 Clock Function and Standby Function TMP92CZ26A contains (1) clock gear, (2) clock doubler (PLL), (3) standby controller and (4) noise-reducing circuit. They are used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 Block diagram of system clock 3.3.2 SFRs 3.3.3 System clock controller 3.3.4 Prescaler clock controller...
Page 24 The clock operating modes are as follows: (a) PLL-OFF Mode (X1, X2 pins only), (b) PLL-ON Mode (X1, X2, and PLL). Figure 3.3.1 shows a transition figure. The clock frequency input from the X1 and X2 pins is called fOSCH and the clock frequency input from the XT1 and XT2 pins is called fs.
Page 25 3.3.1 Block diagram of system clock SYSCR0<WUEF> SYSCR2<WUPTM1:0> (High/Low frequency oscillator circuit) SYSCR0<XTEN > PLLCR1<PLLON>, PLLCR0<LUPFG> Low frequency Oscillator circuit Clock Doubler0 (PLL0) × (12 or16) High frequency Oscillator circuit OSCH Clock Doubler1 (PLL1)× 24 X1USB φT0TMR φT0 Figure 3.3.2 Block Diagram of System clock Warming up timer Lock up timer (PLL)
Page 26 TMP92CZ26A has two PLL circuits: one is for CPU (PLL0) and the other for USB (PLL1). Each PLL can be controlled independently. Frequency of external oscillator is 6 to 10MHz. Don’t connect oscillator more than10MHz. When clock is input by using external oscillator, range of input frequency is 6 to10MHz.
Page 27 3.3.2 SFR bit Symbol SYSCR0 Read/write (10E0H) After Reset -frequency oscillator circuit (fs) 0: Stop 1: Oscillation Function SYSCR1 bit Symbol (10E1H) Read/write After Reset Function – bit Symbol CKOSEL SYSCR2 (10E2H) Read/write After Reset Always Select write “0” CLKOUT Function 0: f 1: f...
Page 28 PROTECT Bit symbol EMCCR0 (10E3H) Read/Write After reset Protect flag 0: OFF Function 1: ON Bit symbol EMCCR1 (10E4H) Read/Write After reset Function Bit symbol EMCCR2 Read/Write (10E5H) After reset Function Note: In case restarting the oscillator in the stop oscillation state (e.g. Restart the oscillator in STOP mode), set EMCCR0<DRVOSCH>, <DRVOSCL>...
Page 29 PLLCR0 bit symbol FCSEL (10E8H) Read/Write After reset Select fc-clock Function 0 : f 1 : f Note: Be carefull that logic of PLLCR0<LUPFG> is different from 900/L1’s DFM. PLLCR1 bit symbol PLL0 (10E9H) Read/Write After reset PLL1 for PLL0 for 0: Off 0: Off 1: On...
Page 30 3.3.3 System clock controller The system clock controller generates the system clock signal (f internal I/O. SYSCR0<XEN> and SYSCR0<XTEN> control enabling and disabling of each oscillator. SYSCR1<GEAR2:0> sets the high frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4, fc/8, fc/16).
Page 31 3.3.4 Clock doubler (PLL) PLL0 outputs the f low-speed frequency oscillator can be used as external oscillator, even though the internal clock is high-frequency. Since Reset initializes PLL0 to stop status, setting to PLLCR0 and PLLCR1-register is needed before use. Like an oscillator, this circuit requires time to stabilize.
Page 32 The following is a setting example for PLL0-starting and PLL0-stopping. (Example-1) PLL0-starting PLLCR0 10E8H PLLCR1 10E9H (PLLCR1),1XXXXXXXXB LUP: 5,(PLLCR0) Z,LUP (PLLCR0), X1XXXXXXB X: Don't care <PLL0> <FCSEL> PLL output: f Lockup timer <LUPFG> System clock f Starts PLL0 operation and Starts lock-up.
Page 33 Limitation point on the use of PLL0 1. If you stop PLL operation during using PLL0, you should execute following setting in the same order. (PLLCR0),X0XXXXXXB (PLLCR1),0XXXXXXXB X: Don't care 2. If you shift to STOP mode during using PLL, you should execute following setting in the same order.
Page 34 3.3.5 Noise reduction circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator circuit (2) Reduced drivability for low-frequency oscillator circuit (3) Single drive for high-frequency oscillator circuit (4) SFR protection of register contents These are set in EMCCR0 to EMCCR2 registers.
Page 35 (2) Reduced drivability for low-frequency oscillator circuit (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) XT1 pin Resonator XT2 pin (Setting method) The drivability of the oscillator is reduced by writing 0 to the EMCCR0<DRVOSCL> register.
Page 36 (4) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that it is in the state which is fetch impossibility by stopping of clock, memory control register (Memory controller, MMU) is changed.
Page 37 3.3.6 Standby controller (1) Halt Modes and Port Drive-register When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP Mode, depending on the contents of the SYSCR2<HALTM1 to 0> register and each pin-status is set according to PxDR-register. bit symbol Px7D PxDR...
Page 38 The operation of each of the different Halt Modes is described in Table 3.3.3. Table 3.3.3 I/O operation during Halt Modes Halt Mode SYSCR2 <HALTM1:0> CPU, MAC I/O ports TMRA, TMRB SIO,SBI A/D converter Block I2S, LCDC, SDRAMC, Interrupt controller, SPIC, DMAC, NDFC,...
Page 39 Table 3.3.4 Source of Halt state clearance and Halt clearance operation Status of Received Interrupt Halt mode INTWDT INT0 to 5 (Note1) INTKEY INTUSB INT6 to 7(PORT) (Note1) INT6 to 7(TMRB) INTALM, INTRTC INTTA0 to INTTP0 INTTB00 to 01, INTTB10 to 11 INTRX,INTTX, INTSBI INTI2S0 to 1, INTLCD, INTAD, INTADHP...
Page 40 (Example - releasing IDLE1 Mode) An INT0 interrupt clears the Halt state when the device is in IDLE1 Mode. Address 8200H (PCFC), 02H 8203H (IIMC0), 00H 8206H (INTE0), 06H 8209H 820BH (SYSCR2), 28H 820EH HALT INT0 820FH XX, XX 92CZ26A-37 ;...
Page 41 (3) Operation a. IDLE2 Mode In IDLE2 Mode, only specific internal I/O operations, as designated by the IDLE2 Setting Register, can take place. Instruction execution by the CPU stops. Figure 3.3.8 illustrates an example of the timing for clearance of the IDLE2 Mode Halt state by an interrupt.
Page 42 STOP Mode When STOP Mode is selected, all internal circuits stop, including the internal oscillator. After STOP Mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. Figure 3.3.10 illustrates the timing for clearance of the STOP Mode Halt state by an interrupt.
Page 43 Input Function Port Name Name During Reset D0-D7 D0-D7 16bit Start OFF P10-P17 D8-D15 Boot Start ON 16bit Start OFF − P60-P67 Boot Start ON − P71-P74 NDR/ WAIT − RXD0 CTS ,SCLK0 P96 *1 INT4 − PA0-PA7 *1 KI0-7 INT0 INT1,TA0IN INT2...
Page 44 Output Function Port Name Name During Reset D0-7 D0-7 16bit Start ON P10-17 D8-15 Boot Start OFF P40-P47 A0-A7 P50-P57 A8-A15 16bit Start ON P60-67 A16-A23 Boot Start OFF WRLL , NDRE WRLU , NDWE EA24 EA25 R/ W − CS , SDCS CS , CSZA SDCS...
Page 45 Output Function Port Name Name During Reset MLDALM,TA1OUT MLDALM ALARM PN0-PN7 KO0-KO7 TA3OUT TA5OUT TA7OUT − PP4-PP5 TB0OUT0 TB1OUT0 − SPDO SPCS SPCLK PT0-PT7 LD8-LD15 PU0-PU6 LD16-LD22 LD23 EO_TRGOUT SCLK0 − − − PV3-PV4 − PW0-PW7 CLKOUT, LDIV − − −...
Page 46: Boot Rom
Boot ROM The TMP92CZ26A contains boot ROM for downloading a user program, and supports two kinds of downloading methods. 3.4.1 Operation Modes The TMP92CZ26A has two operation modes: MULTI mode and BOOT mode. The operation mode is selected according to the AM1 and AM0 pin levels when asserted.
Page 47 3.4.2 Hardware Specifications of Internal Boot ROM (1) Memory map Figure 3.4.1 shows a memory map of BOOT mode. The boot ROM incorporated in the TMP92CZ26A is an 8-Kbyte ROM area mapped to addresses 3FE000H to 3FFFFFH. In MULTI mode, the boot ROM is not mapped and the above area is mapped as an external area.
Page 48 3.4.3 Outline of Boot Operation The method for downloading a user program can be selected from two types: from UART, or via USB. After reset, the boot program on the internal boot ROM executes as shown in Figure 3.4.2. Regardless of the downloading method used, the boot program downloads a user program into the internal RAM and then branches to the internal RAM.
Page 49 002000H Work Area for Boot Program (4 Kbytes) 003000H Download Area for User Program (282 Kbytes) 049800H Stack Area for Boot Program (2 Kbytes) 049FFFH Figure 3.4.3 How the Boot Program Uses Internal RAM 92CZ26A-46 TMP92CZ26A...
Page 50 (1) Port settings Table 3.4.3 shows the port settings by the boot program. When designing your application system, please also refer to Table 3.4.4 for recommended pin connections for using the boot program. The boot program only sets the ports shown in the table below; other ports are left as they are after reset or at startup of the boot program.
Page 51 Table 3.4.4 Recommended Pin Connections Function Port Name Name UART TXD0 RXD0 −−− −−− D− PUCTL Note 1: When a user program is downloaded from UART and USB is used in the system, the pull-up resistor for USB’s D+ pin should not be turned on in BOOT mode.
Page 52 (2) I/O register settings Table 3.4.5 shows the I/O registers that are set by the boot program. After the boot sequence, if execution moves to an application system program without a reset being asserted, the settings of these I/O registers must be taken into account.
Page 53 3.4.4 Downloading a User Program via UART (1) Connection example Figure 3.4.4 shows an example of connections for downloading a user program via UART (using a 16-bit NOR Flash memory device as program memory). Level Shifter Note: When USB is not used, add a pull-up or pull-down resistor to the D+ and D- pins to prevent flow-through current.
Page 54 (3) UART data transfer format Table 3.4.6 to Table 3.4.11 show the supported frequencies, data transfer format, baud rate modification command, operation command, and version management information, respectively. Please also refer to the description of boot program operation later in this section. 6.00 MHz Note: The built-in PLL (clock multiplier) is not used regardless of the oscillation frequency.
Page 55 Table 3.4.8 Baud Rate Modification Command Baud Rate (bps) 9600 Modification Command Note 1: If f (oscillation frequency) is 10.0 MHz, 57600 and 115200 bps are not supported. OSCH Note 2: If f (oscillation frequency) is 6.00, 8.00, or 9.00 MHz, 38400, 57600, and 115200 bps are not OSCH supported.
Page 56 the baud rate is not changed, the initial baud rate data (28H: 9600 bps) must be sent. Baud rate modification becomes effective after the echo back transmission is completed. The 9th byte is used to echo back the received data to the PC when the data received in the 8th byte is one of the baud rate modification data corresponding to the operating frequency of the microcontroller.
Page 57 b) Error codes The boot program uses the error codes shown in Table 3.4.12 to notify the PC of its processing status. Table 3.4.12 Error Codes Error Code Unsupported baud rate Invalid operation command Framing error in received data Overrun error in received data Note 1: If a receive error occurs while a user program is being received, no error code will be sent to the PC.
Page 58 d) Notes on Intel Hex format (binary) After receiving the checksum of a record, the boot program waits for the start mark (3AH for “:”) of the next record. If data other than 3AH is received between records, it is ignored. Once the PC program has finished sending the checksum of an end record, it must wait for 2 bytes of data (upper and lower bytes of SUM) before sending any other data.
Page 59 User program receive error If either of the following error conditions occurs while a user program is being received, the boot program stops operation. If the record type is other than 00H, 01H, or 02H If a checksum error occurs Measured frequency/baud rate error When the boot program receives matching data, it measures the oscillation frequency.
Page 60 (5) Others Handshake function Although the pin is available in the TMP92CZ26A, the boot program does not use it for transfer control. RS-232C connector The RS-232C connector must not be connected or disconnected while the boot program is running. Software on the PC When downloading a user program via UART, special application software is needed on the PC.
Page 61 3.4.5 Downloading a User Program via USB (1) Connection example Figure 3.4.5 shows an example of connections for downloading a user program via USB (using a 16-bit NOR Flash memory device as program memory). PUCTL R4 = 100 kΩ R1 = 1.5 kΩ R2 = 27 Ω...
Page 62 The following shows an overview of the USB communication flow. Host (PC) Send GET_DISCRIPTOR Connection Recognition Send DESCRIPTOR information Send the microcontroller information command Send microcontroller information data Check data Data Transfer Send the microcontroller information command Convert Intel Hex format data into binary data Send microcontroller information data...
Page 63 Table 3.4.15 Vendor Request Commands Command Name Value of bRequest Microcontroller information command User program transfer start command User program transfer result command Table 3.4.16 Setup Command Data Structure Field Name Value bmRequestType bRequest 00H, 02H, 04H wValue 00H~FFFFH wIndex 00H~FFFFH wLength 0000H...
Page 64 Table 3.4.17 Standard Request Commands Standard Request GET_STATUS CLEAR_FEATURE SET_FEATURE SET_ADDRESS GET_DISCRIPTOR SET_DISCRIPTOR GET_CONFIGRATION SET_CONFIGRATION GET_INTERFACE SET_INTERFACE SYNCH_FRAME Table 3.4.18 Information Returned by GET_DISCRIPTOR DeviceDescriptor Field Name Blength BdescriptorType BcdUSB 0110H BdeviceClass BdeviceSubClass BdeviceProtocol BmaxPacketSize0 IdVendor 0930H IdProduct 6504H BcdDevice 0001H Imanufacturer Iproduct...
Page 65 ConfigrationDescriptor Field Name bLength bDescriptorType wTotalLength 0020H bNumInterfaces bConfigurationValue iConfiguration bmAttributes MaxPower InterfaceDescriptor Field Name bLength bDescriptorType bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iIinterface EndpointDescriptor Field Name <Endpoint1> blength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize 0040H bInterval <Endpoint2> bLength bDescriptor bEndpointAddress bmAttributes wMaxPacketSize 0040H bInterval...
Page 66 Table 3.4.19 Information Returned for the Microcontroller Information Command Microcontroller Information TMP92CZ26A 54H, 4DH, 50H, 39H, 32H, 43H, 5AH, 32H, 36H,20H, 20H, 20H, 20H, 20H, 20H Table 3.4.20 Information Returned for the User Program Transfer Result Command Transfer Result No error User program not received Received file not in Intel Hex format User program size error...
Page 67 (3) Description of the USB boot program operation The boot program loads a user program in Intel Hex format sent from the PC into the internal RAM. When the user program has been loaded successfully, the user program starts executing from the first address received. The boot program thus enables users to perform customized on-board programming.
Page 68 Notes on the user program format (binary) After receiving the checksum of a record, the boot program waits for the start mark (3AH for “:”) of the next record. If data other than 3AH is received between records, it is ignored. Since the address pointer is initially set to 00H, the record type to be transferred first does not have to be an address record.
Page 69 (4) Others USB connector The USB connector must not be connected or disconnected while the boot program is running. Software on the PC To download a user program via USB, a USB device driver and special application software are needed on the PC. 92CZ26A-66 TMP92CZ26A...
Page 70 3.5 Interrupts Interrupts are controlled by the CPU Interrupt Mask Register <IFF2 to 0> (bits 12 to 14 of the Status Register) and by the built-in interrupt controller. TMP92CZ26A has a total of 56 interrupts divided into the following five types: Interrupts generated by CPU: 9 sources •...
Page 71 Interrupt processing Interrupt specified by DMA start vector ? Interrupt vector calue “V” read interrupt request F/F clear General-purpose interrupt PUSH processing PUSH SR<IFF2:0> ← Level of INTNEST ← INTNEST + 1 PC ← (FFFF00H + V) Interrupt processing program RETI instruction POP SR POP PC...
Page 72 3.5.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and illegal instruction interrupts generated by the CPU, the CPU skips steps (1) and (3), and executes only steps (2), (4), and (5).
Page 73 Table 3.5.1 TMP92CZ26A Interrupt Vectors and Micro DMA/HDMA Start Vectors Default Interrupt Source and Source of Type Priority Reset or [SWI0] instruction [SWI1] instruction Illegal instruction or [SWI2] instruction [SWI3] instruction [SWI4] instruction maskable [SWI5] instruction [SWI6] instruction [SWI7] instruction (Reserved) INTWD: Watchdog timer −...
Page 74 Default Interrupt Source and Source of Type Priority INTADHP: AD most priority conversion end INTAD: AD conversion end INTTC0/INTDMA0: Micro DMA0 /HDMA0 end INTTC1/INTDMA1: Micro DMA1 /HDMA1 end INTTC2/INTDMA2: Micro DMA2 /HDMA2 end INTTC3/INTDMA3: Micro DMA3 /HDMA3 end Maskable INTTC4/INTDMA4: Micro DMA4 /HDMA4 end INTTC5/INTDMA5: Micro DMA5 /HDMA5 end INTTC6 INTTC7...
Page 75 3.5.2 Micro DMA processing In addition to general-purpose interrupt processing, the TMP92CZ26A also includes a micro DMA function and HDMA function. This section explains about Micro DMA function. For the HDMA function, please refer 3.23 DMA controller. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (Level 6), regardless of the priority level of the interrupt source.
Page 76 If micro DMA requests are set simultaneously for more than one channel, priority is not based on the interrupt priority level but on the channel number: The lower the channel number, the higher the priority (Channel 0 thus has the highest priority and channel 7 the lowest).
Page 77 (2) Soft start function The TMP92CZ26A can initiate micro DMA/HDMA either with an interrupt or by using the micro DMA /HDMA soft start function, in which micro DMA or HDMA is initiated by a Write cycle which writes to the register DMAR. Writing “1”...
Page 78 (4) Detailed description of the transfer mode register Mode DMAMn[4:0] 0 0 0 z z Destination INC mode (DMADn +) ← (DMASn) DMACn if DMACn = 0 then INTTCn 0 0 1 z z Destination DEC mode (DMADn -) ← (DMASn) DMACn if DMACn = 0 then INTTCn 0 1 0 z z...
Page 79 3.5.3 Interrupt Controller Operation The block diagram in Figure 3.5.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 59 interrupts channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA /HDMA start vector register.
Page 80 TMP92CZ26A Figure 3.5.3 Block Diagram of Interrupt Controller 92CZ26A-77...
Page 81 (1) Interrupt priority setting registers Symbol Name Address INT0 INTE0 enable INT1 & INT2 INTE12 enable INT3 & INT4 INTE34 enable INT5 & INT6 INTE56 enable INT7 INTE7 enable INTTA0 & INTETA01 INTTA1 enable INTTA2 & INTETA23 INTTA3 enable INTTA4 & INTETA45 INTTA5 enable...
Page 82 Symbol Name Address INTTB00 & INTETB0 INTTB01 enable INTTB10 & INTETB1 INTTB11 enable INTRX0 & INTES0 INTTX0 enable INTSBI & INTESBIADM INTADM enable INTSPI INTESPI enable INTUSB INTEUSB enable INTALM INTEALM enable INTRTC INTERTC enable INTKEY INTEKEY enable Interrupt request flag INTTB01 (TMRB0) ITB01C ITB01M2 ITB01M1 ITB01M0 ITB00C ITB00M2 ITB00M1 ITB00M0 INTTB11 (TMRB1)
Page 83 Symbol Name Address INTLCD INTELCD enable INTI2S0 & INTEI2S01 INTI2S1 enable INTRSC & INTENDFC INTRDY enable INTP0 INTEP0 enable INTAD & 0INTEAD INTADHP enable Interrupt request flag − − − − − Always write “0”. INTI2S1 II2S1C II2S1M2 II2S1M1 II2S1M0 I I2S0C II2S0M2 II2S0M1 II2S0M0 INTRSC IRSCC IRSCM2 IRSCM1 IRSCM0 IRDYC −...
Page 84 Symbol Name Address INTTC0/INTDMA0 & INTETC01 INTTC1/INTDMA1 /INTEDMA01 enable INTTC2/INTDMA2 & INTETC23 INTTC3/INTDMA3 /INTEDMA23 enable INTTC4/INTDMA4 & INTETC45 INTTC5/INTDMA5 /INTEDMA45 enable INTTC6 & INTTC7 INTETC67 enable INTWD INTWDT enable Interrupt request flag INTTC1/INTDMA1 ITC1C ITC1M2 ITC1M1 ITC1M0 /IDMA1C /IDMA1M2 /IDMA1M1 /IDMA1M0 INTTC3/INTDMA3 ITC3C...
Page 85 External interrupt control Symbol Name Address Interrupt INT5EDGE IIMC0 input mode (Prohibit 0: Rising control 0 RMW) 1: Falling Interrupt IIMC1 input mode (Prohibit control 0 RMW) Note 1: Disable INT0 request before changing INT0 pin mode from level sense to edge sense. (change <I0LE>from “1”...
Page 86 SIO receive interrupt control Symbol Name Address interrupt SIMC (Prohibit mode RMW) control Note: When using the micro DMA transfer end interrupt, always write “1”. INTRX0 edge enable Edge detect INTRX0 “H” level INTRX0 − − Always Always write “0” write “0”...
Page 87 (4) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA /HDMA start vector, as given in Table 3.5.1 to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction.
Page 88 Symbol Name Address DMA0 DMA0V start 100H vector DMA1 DMA1V start 101H vector DMA2 DMA2V start 102H vector DMA3 DMA3V start 103H vector DMA4 DMA4V start 104H vector DMA5 DMA5V start 105H vector DMA6 DMA6V start 106H vector DMA7 DMA7V start 107H vector...
Page 89 (7) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches “0”. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to “1” specifies that any micro DMA transfer on that channel will be a burst transfer.
Page 90 (8) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore, if immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag, the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector.
Page 91 DMAC (DMA Controller) The TMP92CZ26A incorporates a DMA controller (DMAC) having six channels. This DMAC can realize data transfer faster than the micro DMA function by the 900/H1 CPU. The DMAC has the following features: 1) Six independent channels of DMA 2) Two types of transfer start requests Hardware request (using an interrupt source connected with the INTC) or software request can be selected for each channel.
Page 92: Block Diagram
3.6.1 Block Diagram Figure 3.6.1 shows an overall block diagram for the DMAC. SDRAM Controller INTC (Interrupt Controller) Interrupt REQ DMAnV →DMAC or micro DMA request source setting DMAR →DMAC or micro DMA soft start setting DMAB →Micro DMA burst setting DMASEL →DMAC or micro DMA select setting...
Page 93 3.6.2 SFRs The DMAC has the following SFRs. These registers are connected to the CPU via a 16-bit data bus. (1) HDMASn (DMA Transfer Source Address Setting Register) The HDMASn register is used to set the DMA transfer source address. When the source address is updated by DMA execution, HDMASn is also updated.
Page 94 (2) HDMADn (DMA Transfer Destination Address Setting Register) The HDMADn register is used to set the DMA transfer destination address. When the destination address is updated by DMA execution, HDMADn is also updated. HDMAD0 to HDMAD5 have the same configuration. Although the bus sizing function is supported, the address alignment function is not supported.
Page 95 (3) HDMACAn (DMA Transfer Count A Setting Register) The HDMACAn register is used to set the number of times a DMA transfer is to be performed by one DMA request. HDMACAn contains 16 bits and can specify up to 65536 transfers (0001H = one transfer, FFFFH = 65535 transfers, 0000H = 65536 transfers).
Page 96 (4) HDMACBn (DMA Transfer Count B Setting Register) The HDMACBn register is used to set the number of times a DMA request is to be made. HDMACBn contains 16 bits and can specify up to 65536 requests (0001H = one request, FFFFH = 65535 requests, 0000H = 65536 requests).
Page 97 (5) HDMAMn (DMA Transfer Mode Setting Register) The HDMAMn register is used to set the DMA transfer mode. HDMAM0 to HDMAM5 have the same configuration. HDMAMn bit Symbol Read/Write After reset Function Transfer mode [7: 0] HDMAM0 Channel 0 (090CH) HDMAM1 Channel 1 (091CH)
Page 98 (6) HDMAE (DMA Operation Enable Register) The HDMAE register is used to enable or disable the DMAC operation. Bits 0 to 5 correspond to channels 0 to 5. Unused channels should be set to “0”. HDMAE bit Symbol (097EH) Read/Write After reset Function Note: Read-modify-write instructions can be used on this register.
Page 99 3.6.3 DMAC Operation Description (1) Overall flowchart Figure 3.6.9 shows a flowchart for DMAC operation when an interrupt (DMA) is requested. Figure 3.6.9 Overall Flowchart Interrupt (DMA) request To general-purpose interrupt or micro DMA processing flow Interrupt specified by DMA start vector? Interrupt request F/F clear &...
Page 100 (2) Bus arbitration The TMP92CZ26A includes three controllers (DMA controller, LCD controller, SDRAM controller) that function as bus masters apart from the CPU. These controllers operate independently and assert a bus request as required. The controller that receives a bus acknowledgement acts as the bus master.
Page 101 3.6.4 Setting Example This section explains how to set the DMAC using an example. (1) Transferring music data from internal RAM to I2S by DMA transfer The 32 Kbytes of data stored in the internal RAM at addresses 2000H to 9FFFH shall be transferred to FIFO-RAM via I2S.
Page 102 TMP92CZ26A 3.6.5 Note 1. In case of using S/W start with HDMA, transmission start is to set to "1" DMAR register. However DMAR register can't be used to confirm flag of transmission end. DMAR register reset to "0" when HDMA release bus occupation once with HDMATR function.
Page 103 3.6.6 Considerations for Using More Than One Bus Master In the TMP92CZ26A, the LCD controller, SDRAM controller, and DMA controller may act as the bus master apart from the CPU. Therefore, care must be exercised to enable each of these functions to operate smoothly.
Page 104 Sample 1) Calculation example for CPU + HDMA Conditions: CPU operation speed (f : 60 MHz I2S sampling frequency : 48 KHz (60 MHz/25/50 = 48 KHz) I2S data transfer bit length : 16 bits DMAC channel 0 used to transfer 5 Kbytes from internal RAM to I2S Calculation example: DMAC source data read time: Internal RAM data read time = 1 state/4 bytes (However, the first 1 byte requires 2 states.)
Page 105 (2) CPU + LDMA The LCD controller performs DMA transfer (LDMA) after issuing a bus request to the CPU and getting a bus acknowledgement. If LDMA is not performed properly, the LCD display function cannot work properly. Therefore, LDMA must have higher priority than the CPU. While LDMA is being performed, the CPU cannot execute instructions.
Page 106 Sample2) Calculation examples for CPU + LDMA Conditions 1: CPU operation speed (f : 60 MHz Display RAM : Internal RAM : QVGA (320seg × 240com) Display size Display quality : 65536 colors (TFT) Refresh rate : 70 Hz (including 20 clocks of dummy cycles) Calculation example 1: = ((SegNum ×...
Page 107 (3) CPU + LDMA + ARDMA The SDRAM controller owns the bus not only when SDRAM is used as the LCD display RAM but also when SDRAM is used as work, data, or stack area. The SDRAM controller occupies the bus (ARDMA) while it refreshes SDRAM data by the auto refresh function. No special consideration is needed for the ARDMA time normally as it ends within several clocks per specified number of states.
Page 108 Sample3) Calculation example for CPU + LDMA + ARDMA Conditions: CPU operating speed(f : 60 MHz Display RAM : 16-bit external SDRAM : QVGA (320seg × 240com) Display size Display quality : 65536 colors (TFT) Refresh rate : 70 Hz (including 20 clocks of dummy cycles) : Every 936 states (15.6 μ...
Page 109 (4) CPU + LDMA+ ARDMA + HDMA This is a case in which all the bus masters are active at the same time. Since the LCD display function cannot work properly if the LCD controller cannot perform LDMA properly, the priorities among the four bus masters should be set in the order of LDMA >...
Page 110 Sample 4) Calculation example for CPU + LDMA+ ARDMA + HDMA Conditions: CPU operation speed (f : 60 MHz : QVGA (320seg × 240com) Display RAM Display quality : 65536 colors (TFT) Refresh rate : 70 Hz (including 20 clocks of dummy cycles) : Every 936 states (15.6 μ...
Page 111 HDMATR bit Symbol DMATE (097FH) Read/Write After reset Timer operation Function 0: Disable 1: Enable Note: Read-modify-write instructions can be used on this register. By writing “87H” to the HDMATR register, the maximum HDMA time is set to 29.9 [μs] (256 ×...
Page 112 Sample 5) Calculation example when using CPU + LCDC + SDRAMC + HDMA at same time (Worst case) Conditions: CPU operation speed (f Display RAM Display size Display quality Refresh rate HDMA Calculation example: (LCD) STOP LHSYNC [period: S] (HDMA) STOP LCD driver data transfer time [S] LHSYNC [cycle S] - LCD driver data transfer time [S] −...
Page 113 3.7 Function of ports TMP92CZ26A has I/O port pins that are shown in Table 3.7.1 in addition to functioning as general-purpose I/O ports, these pins are also used by internal CPU and I/O functions. Table 3.7.2 lists I/O registers and their specifications. Table 3.7.1 Port Functions (1/3) Port Name Pin Name...
Page 114 Table 3.7.1 Port Functions (2/3) Number of Port Name Pin Name Pins Port J Port K Port L PL0 to PL7 Port M Port N PN0 to PN7 Port P Port R Port T PT0 to PT7 Port U PU0 to PU4 ,PU6 Port V Port W...
Page 115 Table 3.7.1 Port Functions (3/3) Number of Port Name Pin Name Pins Port Z Pin Name for built-in I/O Setting − EI_PODDATA − EI_SYNCLK − EI_PODREQ − EI_REFCLK − EI_TRGIN − EI_COMRESET − EO_MCUDATA − EO_MCUREQ 92CZ26A-112 TMP92CZ26A function...
Page 116 Table 3.7.2 I/O Port and Specifications (1/4) Port Pin name Port 1 P10 toP17 Input port Output port D8 to D15 bus Port 4 P40 to P47 Output port A0 to A7 Output Port 5 P50 to P57 Output port A8 to A15 Output Port 6 P60 to P67...
Page 117 Table3.7.2 I I/O Port and Specifications (2/4) Port Pin name Port 9 P90, P92 Input port Input port, RXD0 Input Input port Input port P90 to P92 Output port TXD0 Output TXD0 Output (Open-drain) SCLK0 Output SCLK0, INT4 Input Port A PA0 to PA7 Input port KI0 to KI7 Input...
Page 118 Table3.7.2 I/O Port and Specifications (3/4) Port Pin name Port G PG0 to PG5 Input port AN0 to AN5 Input ADTRG Input MX Output MY Output Port J PJ5 to PJ6 Input port PJ5 to PJ6 Output port PJ0 to PJ4, Output port SDRAS , SRLLB Output SDCAS , SRLUB Output...
Page 119 Table 3.7.2 I/O Port and Specifications (4/4) Port Pin name Port R PR0 to PR3 Input port PR0 to PR3 Output port SPDI Input SPDO Output SPCS Output SPCLK Output Port T PT0 to PT7 Input port PT0 toPT7 Output port PT0 to PT7 LD8 to LD15 Output Port U...
Page 120 3.7.1 Port 1 (P10 to P17) Port1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O port, port1 can also function as a data bus (D8 to D15).
Page 121 bit Symbol (0004H) Read/Write After reset P1CR bit Symbol P17C (0006H) Read/Write After reset Function P1FC bit Symbol (0007H) Read/Write After reset Note2: Function P1DR bit Symbol P17D (0081H) Read/Write After reset Function Note1: Read-modify-write is prohibited for P1CR, P1FC. Note2: It is set to “Port”...
Page 122 3.7.2 Port 4 (P40 to P47) Port4 is an 8-bit general-purpose Output ports. In addition to functioning as a general-purpose Output port, port4 can also function as an address bus (A0 to A7). Each bit can be set individually for function. Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 4 to the following function pins: P4FC Register P4 Register...
Page 123 bit Symbol (0010H) Read/Write After reset P4FC bit Symbol P47F (0013H) Read/Write After reset Note2: Function P4DR bit Symbol P47D (0084H) Read/Write After reset Function Note1: Read-modify-write is prohibited for P4FC. Note2: It is set to “Port” or “Data bus” by AM pins state. Port 4 register Port 4 Function register P46F...
Page 124 3.7.3 Port 5 (P50 to P57) Port5 is an 8-bit general-purpose Output ports. In addition to functioning as a general-purpose I/O port, port5 can also function as an address bus (A8 to A15). Each bit can be set individually for function. Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 5 to the following function pins: P5FC Register P5 Register...
Page 125 bit Symbol (0014H) Read/Write After reset P5FC bit Symbol P57F (0017H) Read/Write After reset Note2: Function bit Symbol P57D P5DR Read/Write (0085H) After reset Function Note1: Read-modify-write is prohibited for P5FC. Note2: It is set to “Port” or “Data bus” by AM pins state. Port 5 register Port 5 Function register P56F...
Page 126 3.7.4 Port 6 (P60 to P67) Port6 is an 8-bit general-purpose I/O ports. Bits can be individually set as either inputs or outputs and function by control register P6CR and function register P6FC. In addition to functioning as a general-purpose I/O port, port6 can also function as an address bus (A16 to A23).
Page 127 bit Symbol (0018H) Read/Write After reset P6CR bit Symbol P67C (001AH) Read/Write After reset Function P6FC bit Symbol P67F (001BH) Read/Write After reset Note2: Function bit Symbol P67D P6DR (0086H) Read/Write After reset Function Note: Read-modify-write is prohibited for P6CR, P6FC. Note2: It is set to “Port”...
Page 128 3.7.5 Port 7 (P70 to P76) Port7 is a 7-bit general-purpose I/O port (P70 is used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, P70 to P76 pins can also function interface-pin for external memory.
Page 129 P7CR register P7FC register P7 register EA24, EA25 Read data P7CR register P7FC register P7 register Port read data NDR/ B P7CR register P7FC register P7 register Port read data WAIT Selector Selector Selector Selector Figure 3.7.10 Port7 92CZ26A-126 TMP92CZ26A P73 (EA24) P74 (EA25) P75(R/W,...
Page 130 bit Symbol (001CH) Read/Write Data from external port After reset (Output latch register is P7CR bit Symbol (001EH) Read/Write After reset Function bit Symbol P7FC Read/Write (001FH) After reset 0:Port Function 1: WAIT bit Symbol P7DR Read/Write (0087H) After reset Function P73 setting <...
Page 131 3.7.6 Port 8 (P80 to P87) Port 80 to 87 are 8-bit output ports. Resetting sets output latch of P82 to “0” and output latches of P80 to P81, P83 to P87 to “1”. But if it is started at boot mode (AM [1:0]= “11”), output latch of P82 is set to “1”.
Page 132 bit Symbol (0020H) Read/Write After reset P87F P86F P8FC bit Symbol (0023H) Read/Write After reset 0: Port 0: Port Function 1: <P87F2> 1: <P86F2> P87F2 P86F2 P8FC2 bit Symbol (0021H) Read/Write After reset 0: CSZD CSXB Function P87D P86D P8DR bit Symbol (0088H) Read/Write...
Page 133 3.7.7 Port 9 (P90 to P92, P96, P97) P90 to P92 are 3-bit general-purpose I/O port. I/O can be set on bit basis using the control register. Resetting sets P90 to P92 to input port and all bits of output latch to”1”. P96 to P97 are 2-bit general-purpose input port.
Page 134 Reset Direction control (on bit basis) P9CRwrite Function control (on bit basis) P9FCwrite Output latch Selector P9 write SCLK0 output Selector P9 read SCLK0 input Reset Function control TSICR0<PXEN> P9FC write TSICR0<TSI7> P9 read Rising/Falling INT4 edge-ditection IIMC<I4EDGE> Figure 3.7.16 Port 96,97 RXD0 input input Figure 3.7.15 P91, 92...
Page 135 bit Symbol (0024H) Read/Write Data from external After reset port bit Symbol P9CR (0026H) Read/Write After reset Function bit Symbol P9FC Read/Write (0027H) After reset 0: Input Function 1: INT4 − bit Symbol P9FC2 (0025H) Read/Write After reset Always write “0” Function bit Symbol P97D...
Page 136 3.7.8 Port A (PA0 to PA7) Port A0 to A7 are 8-bit general-purpose input ports with pull-up resistor. In addition to functioning as general-purpose I/O ports, port A0 to A7 can also Key-on wake-up function as Keyboard interface. The various functions can each be enabled by writing a “1” to the corresponding bit of the Port A Function Register (PAFC).
Page 137 bit Symbol (0028H) Read/Write After reset bit Symbol PA7F PA6F PAFC Read/Write (002BH) After reset Function bit Symbol PA7D PA6D PADR Read/Write (008AH) After reset Function Note 1: Read-modify-write is prohibited for PAFC. Port A register Data from external port Port A Function register PA5F PA4F...
Page 138 3.7.9 Port C (PC0 to PC7) PC0 to PC7 are 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port C to an input port. It also sets all bits of the output latch register to “1”.
Page 139 (2) PC1 (INT1, TA0IN), PC3 (INT3, TA2IN) Reset Direction control PCCR write Function control PCFCwrite Output latch PCwrite Selector PC read Level/edge selection INT1 INT3 Rising/Falling selection IIMC<I1LE, I1EDGE> <I3LE, I3EDGE> TA0IN TA2IN Figure 3.7.21 Port C1,C3 92CZ26A-136 TMP92CZ26A PC1 (INT1,TA0IN) PC3 (INT3, TA2IN)
Page 140 (3) PC4 (EA26), PC5 (EA27), PC6 (EA28) Reset Direction control (on bit basis) PCCRwrite Function control (on bit basis) PCFC write Output latch Selector PC write EA26 EA27 EA28 PC read Figure 3.7.22 Port C4, C5, C6 (4) PC7 (KO8) Reset Direction control...
Page 141 bit Symbol (0030H) Read/Write After reset bit Symbol PC7C PCCR (0032H) Read/Write After reset Function bit Symbol PC7F PCFC Read/Write (0033H) After reset Function bit Symbol PC7D PCDR (008CH) Read/Write After reset Function PC2 setting <PC2C> <PC2F> Input port Output port INT2 Don’t setting PC5 setting...
Page 142 3.7.10 Port F (PF0 to PF5, PF7) Port F0 to F5 are 6-bit general-purpose I/O ports. Resetting sets PF0 to PF5 to be input ports. It also sets all bits of the output latch register to “1”. In addition to functioning as general-purpose I/O port pins, PF0 to PF5 can also function as the output for I pin can be enabled for I/O by writing a “1”...
Page 143 Reset Direction control (on bit basis) PFCR write Function control (on bit basis) PFFC write Output latch Selector PF write I2S0CKO output I2S1CKO/X1D4output Selector PF read Figure 3.7.25 Port F0, F3 Reset Direction control (on bit basis) PFCRwrite Function control (on bit basis) PFFC write Output latch...
Page 144 TMP92CZ26A (2) Port F7 (SDCLK), Port F7 is general-purpose output port. In addition to functioning as general-purpose output port, PF7 can also function as the SDCLK output. Reset Function control (on bit basis) PFFC write PF7(SDCLK) Output latch Selector SDCLK PF write PF read Figure 3.7.27 Port F7...
Page 145 bit Symbol (003CH) Read/Write After reset bit Symbol PFCR (003EH) Read/Write After reset Function bit Symbol PF7F PFFC Read/Write (003FH) After reset 0: Port Function 1: SDCLK bit Symbol PF7D PF6D PFDR (008FH) Read/Write After reset Function PF2 setting <PF2C> <PF2F>...
Page 146 3.7.11 Port G (PG0 to PG5) PG0 to PG5 are 6-bit input port and can also be used as the analog input pins for the internal AD converter. PG3 can also be used as ADTRG pin for the AD converter. PG2, PG3 can also be used as MX, MY pin for Touch screen interface.
Page 147 Bit Symbol (0040H) Read/Write After reset Note: Selection of the input channel of AD converter and ADTRG input mode register is enabled by setting AD converter. Bit Symbol PGFC Read/Write (0043H) After reset Function Bit Symbol PGDR (0090H) Read/Write After reset Function Note 1: Read-Modify-Write is prohibited for the registers PGFC.
Page 148 3.7.12 Port J (PJ0 to PJ7) PJ0 to PJ4 and PJ7 are 6-bit output port. Resetting sets the output latch PJ to “1”, and they output “1”. PJ5 to PJ6 are 2-bit input/output port. In addition to functioning as port, Port J also functions as output pins for SDRAM ( SDLUDQM, and SDCKE), SRAM ( and NDCLE).
Page 149 Reset Direction control PJCR write Function control PJFC write Output latch Selector PJ write NDALE, NDCLE output Selector P J read Figure 3.7.32 Port J5,J6 92CZ26A-146 TMP92CZ26A PJ5 (NDALE), PJ6 (NDCLE)
Page 150 bit Symbol (004CH) Read/Write Data from external port After reset (Output latch register is bit Symbol PJ6C PJCR (004EH) Read/Write After reset Function bit Symbol PJ7F PJ6F PJFC (004FH) Read/Write After reset 0: Port 0: Port Function 1: SDCKE 1: NDCLE PJ7D PJ6D bit Symbol...
Page 151 3.7.13 Port K (PK0 to PK7) PK0 to PK7 are 8-bit output ports. Resetting sets the output latch PK to “0”, and PK0 to PK7 pins output “0”. In addition to functioning as output port function, Port K also function as output pins for LCD controller (LCP0, LHSYNC, LLOAD, LFR, LVSYNC, and LGOE0 to LGOE2).
Page 152 bit Symbol (0050H) Read/Write After reset bit Symbol PK7F PK6F PKFC (0053H) Read/Write After reset 0:Port 0:Port Function 1:LGOE2 1:LGOE1 PK7D PK6D PKDR bit Symbol (0094H) Read/Write After reset Function Note 1: Read-Modify-Write is prohibited for the registers PKFC. Port K register Port K function register PK5F PK4F...
Page 153 TMP92CZ26A 3.7.14 Port L (PL0 to PL7) PL0 to PL7 are 8-bit output ports. Resetting sets the output latch PL to “0”, and PL0 to PL7 pins output “0”. In addition to functioning as a general-purpose output port, Port L can also function as a data bus for LCD controller (LD0 to LD7).
Page 154 bit Symbol (0054H) Read/Write After reset PLFC bit Symbol PL7F (0057H) Read/Write After reset Function PL7D bit Symbol PLDR (0095H) Read/Write After reset Function Note 1: Read-Modify-Write is prohibited for the registers PLFC. Port L register Port L function register PL6F PL5F PL4F...
Page 155 3.7.15 Port M (PM1, PM2, PM7) PM1, PM2 and PM7 are 3-bit output ports. Resetting sets the output latch PM to “1”, and PM1, PM2 and PM7 pins output “1”. In addition to functioning as output ports, Port M also function as output pin for timers (TA1OUT), output pins for RTC alarm ( ALARM ), output pin for melody/alarm generator (MLDALM, MLDALM ) and Power control pin (PWE).
Page 156 Reset Function control (on bit basis) PMFC write Output latch Selector PM write PM read MLDALM Selector ALARM Figure 3.7.39 Port M2 Reset Function control (on bit basis) PMFC write Output latch PM write PM read Figure 3.7.40 Port M7 92CZ26A-153 ALARM MLDALM...
Page 157 bit Symbol (0058H) Read/Write After reset bit Symbol PM7F PMFC (005BH) Read/Write After reset 0: Port 1: PWE Function bit Symbol PM7D PMDR (0096H) Read/Write After reset Input/Outp ut buffer drive Function register for standby mode Note 1: Read-Modify-Write is prohibited for the registers PMFC. Port M register Port M function register Port M drive register...
Page 158 3.7.16 Port N (PN0 to PN7) PN0 to PN7 are 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port N to an input port. In addition to functioning as a general-purpose I/O port, Port N can also function as interface pin for key-board (KO0 to KO7).
Page 159 bit Symbol (005CH) Read/Write After reset bit Symbol PN7C PN6C PNCR Read/Write (005EH) After reset Function bit Symbol PN7F PN6F PNFC Read/Write (005FH) After reset Function bit Symbol PN7D PN6D PNDR (0097H) Read/Write After reset Function Note 1: Read-Modify-Write is prohibited for the registers PNCR and PNFC. Port N register Data from external port (Output latch register is set to “1”) Port N control register...
Page 160 3.7.17 Port P (PP1 to PP7) Port P1 to P5 are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port P1 to P5 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port pins, P0 to P5 can also function as output pin for timers (TA3OUT, TA5OUT, TA7OUT), input pin for timers (TB0IN0, TB1IN0), input pin for external interruption (INT5 to INT7).
Page 161 Reset Direction control (on bit basis) PPCR write Function control (on bit basis) PPFC write Output latch Selector PP write TA7OUT Selector PP read Level/edge selection INT5 Rising/Falling selection IIMC<I5LE, I5EDGE> Figure 3.7.45 Port P3 Reset Direction control (on bit basis) PPCR write Function control (on bit basis)
Page 162 Reset Function control (on bit basis) PPFC write Output latch Selector PP write TB0OUT0 output TB1OUT0 output Figure 3.7.47 Port P6, P7 92CZ26A-159 TMP92CZ26A PP6 (TB0OUT0) PP7 (TB1OUT0)
Page 163 bit Symbol (0060H) Read/Write After reset PPCR bit Symbol (0062H) Read/Write After reset Function bit Symbol PP7F PPFC Read/Write (0063H) After reset Function 0:Port 0:Port 1:TB1OUT0 1:TB0OUT0 PP7D PPDR bit Symbol (0098H) Read/Write After reset Function PP3 setting < <PP3C> <PP3F>...
Page 164 3.7.18 Port R (R0 to R3) Port R0 to R3 are 4-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port R0 to R3 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port pins, PR0 to PR3 can also function as SPI controller pin (SPCLK, SPCS , SPDO and SPDI).
Page 165 Reset Direction control (on bit basis) PRCR write Function control (on bit basis) PRFC write Output latch Selector PR write SPDO, SPCS , SPCLK Selector PR read Figure 3.7.50 Port R1 to R3 92CZ26A-162 PR1(SPDO), PR2( SPCS ), PR3(SPCLK) TMP92CZ26A...
Page 166 bit Symbol (0064H) Read/Write After reset bit Symbol PRCR (0066H) Read/Write After reset Function bit Symbol PRFC Read/Write (0067H) After reset Function <PR1F> <PR3F> bit Symbol PRDR (0099H) Read/Write After reset Function Note: Read-Modify-Write is prohibited for the registers PRCR, PRFC. Port R register (Output latch register is cleared to “0”) Port R control register...
Page 167 3.7.19 Port T (PT0 to PT7) Port T0 to T7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port T0 to T7 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port pins, PT0 to PT7 can also function as data bus pin for LCD controller (LD8 to LD15).
Page 168 bit Symbol (00A0H) Read/Write After reset PTCR bit Symbol PT7C (00A2H) Read/Write After reset Function bit Symbol PT7F PTFC Read/Write (00A3H) After reset Function PT7D bit Symbol PTDR (009BH) Read/Write After reset Function Note1: Read-Modify-Write is prohibited for the registers PTCR, PTFC. Note2: When PT is used as LD15 to LD8, set applicable PTnC to”1”.
Page 169 3.7.20 Port U (PU0 to PU7) Port U0 to U7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port U0 to U7 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port pins, PU0 to PU7 can also function as data bus pin for LCD controller (LD16 to LD23) and SDCLK input function.
Page 170 Reset Direction control (on bit basis) PUCR wirte Function control (on bit basis) PUFC write Output latch Selector PU write LD21 Selector PU read Figure 3.7.55 Port U5 92CZ26A-167 TMP92CZ26A PU5 (LD21)
Page 171 Bit Symbol (00A4H) Read/Write After reset Bit Symbol PU7C PUCR Read/Write (00A6H) After reset Function Bit Symbol PU7F PUFC Read/Write (00A7H) After reset Function 0: Port 0: Port 1: LD23 1: LD22 Note: When PU is used as LD23 to LD16, set applicable PUnC to “1”. PU7D PUDR Bit Symbol...
Page 172 3.7.21 Port V (PV0 to PV4, PV6, PV7) Port V0 to V2, V6 and V7 are 5-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port V0 to V2, V6 and V7 to input port and output latch to “0”.
Page 173 Reset Output latch PV write PV read Figure 3.7.58 Port V3, V4 Reset Direction control (on bit basis) PVCR write Function control (on bit basis) PVFC write Output latch Selector PV write SDA,SCL output Selector PV read SDA,SCL input Figure 3.7.59 Port V6, V7 92CZ26A-170 PV6(SDA) PV7(SCL)
Page 174 bit Symbol (00A8H) Read/Write Data from external port After reset (Output latch register is cleared to “0”) PVCR bit Symbol PV7C (00AAH) Read/Write After reset Function 0: Input 1: Output bit Symbol PV7F PVFC (00ABH) Read/Write After reset Function Refer to following table PV2 setting <PV2C>...
Page 175 TMP92CZ26A 3.7.22 Port W (PW0 to PW7) Port W0 to W7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port W0 to W7 to input port and output latch to “0”. Above setting is used the control register PWCR and function register PWFC.
Page 176 bit Symbol (00ACH) Read/Write After reset bit Symbol PW7C PWCR Read/Write (00AEH) After reset Function bit Symbol PW7F PWFC Read/Write (00AFH) After reset Function PW7D bit Symbol PWDR (009EH) Read/Write After reset Function Note1: Read-Modify-Write is prohibited for the registers PWCR, PWFC. Port W register Data from external port (Output latch register is cleared to “0”) Port W control register...
Page 177 3.7.23 Port X (PX4, PX5 and PX7) Port X5 and X7 are 2-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port X5 and X7 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port pins, PX5 and PX7 can also function as USB clock input pin (X1USB).
Page 178 TMP92CZ26A Reset Direction control (on bit basis) PXCR write Function control (on bit basis) PXFC write PX5 (X1USB) Output latch PX write Selector PX read X1USB input Figure 3.7.64 Port X5, X7 92CZ26A-175...
Page 179 bit Symbol Read/Write (00B0H) Data from external port After reset (Output latch register is cleared to “0”) bit Symbol PX7C PXCR (00B2H) Read/Write After reset 0: Input Function 1: Output bit Symbol PX7F PXFC (00B3H) Read/Write After reset 0:Port 1: Reserved Function PXD7 bit Symbol...
Page 180 3.7.24 Port Z (PZ0 to PZ7) Port Z0 to Z7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port Z0 to Z7 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port function, Port Z can also function as communication for debug mode EI_REFCLK, EI_TRGIN, EI_COMRESET, EO_MCUDATA and EO_MCUREQ).
Page 181 Reset Debug mode Direction control (on bit basis) PZCR write Output latch Selector PZ write EO_MCUDATA EO_MCUREQ Selector PZ read Figure 3.7.67 Port Z6 to Z7 92CZ26A-178 PZ6(EO_MCUDATA) PZ7(EO_MCUREQ) TMP92CZ26A...
Page 182 bit Symbol (0068H) Read/Write After reset bit Symbol PZ7C PZ6C PZCR Read/Write (006AH) After reset Function bit Symbol PZ7D PZ6D PZDR (009AH) Read/Write After reset Function Note: Read-Modify-Write is prohibited for the registers PZCR. Port Z register Data from external port (Output latch register is cleared to “0”) Port Z control register PZ5C PZ4C...
Page 183 Memory Controller (MEMC) 3.8.1 Functions TMP92CZ26A has a memory controller with a variable 4-block address area that controls as follows. (1) 4-block address area support Specifies a start address and a block size for 4-block address area (block0 to 3). * SRAM or ROM * SDRAM * Page-ROM...
Page 184 3.8.2 Control register and Operation after reset release This section describes the registers to control the memory controller, the state after reset release and necessary settings. (1) Control Register The control registers of the memory controller are as follows and Table 3.8.1 to Table 3.8.2. ･...
Page 185 B0CSL Bit symbol B0WW3 B0WW2 (0140H) Read/Write After Reset B0CSH Bit Symbol (0141H) Read/Write After Reset MAMR0 Bit Symbol M0V20 (0142H) Read/Write After Reset MSAR0 Bit Symbol M0S23 (0143H) Read/Write After Reset B1CSL Bit symbol B1WW3 B1WW2 (0144H) Read/Write After Reset B1CSH Bit Symbol (0145H)
Page 186 BEXCSL Bit Symbol BEXWW3 (0159H) Read/Write After Reset BEXCSH Bit Symbol (0158H) Read/Write After Reset PMEMCR Bit Symbol (0166H) Read/Write After Reset CSTMGCR Bit Symbol (0168H) Read/Write After Reset WRTMGCR Bit Symbol (0169H) Read/Write After Reset RDTMGCR0 Bit Symbol B1TCRS1 (016AH) Read/Write After Reset...
Page 187 (2) Operation after releasing reset The data bus width at starting is determined depending on state of AM1/AM0 pins after releasing reset. Then, the external memory access as follows; Note: A memory to be used to start after releasing reset is either NOR-Flash or Masked-ROM.NAND-Flash, SDRAM can’t be used.
Page 188 3.8.3 Basic functions and register setting In this section, setting of the block address area, the connecting memory and the number of waits out of the memory controller’s functions are described. (1) Block address area specification The block address areas of CS0 to CS3 are specified by MSAR0 to MSAR3 and MAMR0 to MAMR3.
Page 189 (b) Memory address mask registers Figure 3.8.3 shows the memory address mask registers. MAMR0 to MAMR3 are used to set the size of the CS0 to CS3 areas by specifying a mask for each bit of the start address set in MAMR0 to MAMR3.
Page 190 (c) Setting memory start addresses and address areas An example of specifying a 64-Kbyte address area starting from 010000H using the CS0 areas i describes. Set 01H in MSAR0<S23:16> (Corresponding to the upper 8 bits of the start address). Next, calculate the difference between the start address and the anticipated end address (01FFFFH) based on the size of the CS0 area.
Page 191 Table 3.8.3 Valid Area Sizes for Each CS Area Size (Byte) 32 K CS area ○ ○ ○ ○ ○ ○ ○ Note:“Δ” indicates areas that cannot be set by memory start address register and address mask register combinations. (e) Block address area Priority When the set block address area overlaps with the built-in memory area, or both two address areas overlap, the block address area is processed according to priority as follows.
Page 192 (2) Connection Memory Specification Setting BnCSH<BnOM1:0> specifies the memory type to be connected with the block address areas. The interface signal is output according to the set memory as follows; BnCSH<BnOM1:0> BnOM1 BnOM0 Note1: SDRAM should be set only with CS1 or CS2 . (3) Data Bus Width Specification The data bus width is set for every block address area.
Page 193 Operand Start Operand Data Size (bit) Address 4n + 0 4n + 1 4n + 2 4n + 3 4n + 0 4n + 1 4n + 2 4n + 3 4n + 0 4n + 1 4n + 2 4n + 3 xxxxx: During read, input data to the bus is ignored.
Page 194 (4) Wait control The external bus cycle completes for two states minimum(25 ns at f Setting the BnCSL<BnWW3:0> specifies the number of waits in the write cycle, and BnCSL<BnWR3:0> specifies the number of waits in the read cycle. <BnWW3:0> is set with the same method as <BnWR3:0>...
Page 195 (5) Recovery (Data hold) cycle control Some memory have an AC specification about data hold time from cycle and a data confliction problem may occur. To avoid this problem, 1-dummy cycle can be inserted after CSm-block access cycle by setting “1” to BmCSH<BmREC> register. This 1-dummy cycle is inserted when the next cycle is for another CS-block.
Page 196 (6) Adjust Function for the timing of control signal This function can change the timing of signals and adjust the timing according to the set-up/hold time of the memories. As for the CSZx CSXx for only 1 CS area. While for areas.
Page 197 RDTMGCR0/1<BnTCRS1:0> TCRS = 0.5 × f TCRS = 1.5 × f TCRS = 2.5 × f TCRS = 3.5 × f TCRS:The delay from (CSn) to (RD,SRxxB). SDCLK (80MHz) A23 to 0 Read SRxxB cycle D15 to 0 WRxx Write SRWR cycle SRxxB...
Page 198 (7) Basic bus timing (a) External read/write cycle (0 waits) SDCLK (60 MHz) A23 to A0 SRxxB D15 to D0 SRWR SRxxB WRxx D15 to D0 (b) External read/write cycle (1 wait) SDCLK (60 MHz) A23 to A0 SRxxB D15 to D0 SRWR SRxxB WRxx...
Page 199 (c) External read bus cycle (1 wait + TAC: 1f External write bus cycle (1 wait + TAC: 1f SDCLK (80 MHz) A23 to 0 RD SRxxB D15 to 0 SRWR , SRxxB WRxx D15 to 0 WAIT (d) External read/write cycle (4 waits + SDCLK (80 MHz) A23 to 0...
Page 200 (e) External read/write cycle (4 waits + SDCLK (80 MHz) A23 to 0 RD SRxxB D15 to 0 SRWR , SRxxB WRxx D15 to 0 WAIT (f) External read bus cycle (4 waits + External write bus cycle (4 waits + SDCLK (80 MHz) A23 to 0...
Page 201 (8) Connecting to external memory Figure 3.8.4 shows an example of how to connect external 16-bit SRAM and 16-bit NOR flash to the TMP92CZ26A. TMP92CZ26A SRLLB SRLUB SRWR D [15:0] Figure 3.8.4 Example of External 16-Bit SRAM and NOR Flash Connection 16-bit SRAM I/O [16:1] Not connect...
Page 202 3.8.4 ROM Page mode Access Control This section describes ROM page mode accessing and how to set registers. ROM page mode is set by PMEMCR. Operation and how to set the registers TMP92CZ26A supports ROM access with the page mode. The ROM access with the page mode is specified only in CS2.
Page 203 3.8.5 Internal Boot ROM Control This section describes about built-in boot ROM. For the specification of S/W in boot ROM, refer to the section 3.4 boot ROM. (1) BOOT mode BOOT mode is started by following AM1 and AM0 pins condition with reset. (2) Boot ROM memory map Boot ROM is consist of 8-Kbyte masked ROM and assigned 3FE000H to 3FFFFFH address.
Page 204 (4) Disappearing boot ROM After boot sequence in BOOT mode, an application system program may continue to run without reset asserting. In this case, an external memory which is mapped 3FE000H to 3FFFFFH address can not be accessed because of boot ROM is assigned. To solve it, internal boot ROM can be disappered by setting BROMCR<ROMLESS>...
Page 205 3.8.6 Cautions (1) Note the timing between If the load capacitance of the select signal), it is possible that an unintended read cycle occurs due to a delay in the read signal. Such an unintended read cycle may cause a trouble as in the case of (a) in Figure 3.8.6.
Page 206 (2) Note the NAND flash area setting Figure 3.8.8 shows a memory map for NAND flash. And since CS3 area is recommended to assign address from 000000H to 3FFFFFH, this case is explained. In this case, “NAND flash” and CS3 area are overlapped. But active by setting BROMCR<CSDIS>...
Page 207 3.9 External Memory Extension Function (MMU) This is MMU function which can expand program/data area to 3.1G bytes by having 4-type local area. The recommendation address memory map is shown in Figure 3.9.1. However, when total capacity of used memory is less than 16M bytes, please refer to section of Memory controller.
Page 208 Address memory map 000000H Internal I/O, RAM COMMON-X (2MB) 200000H LOCAL-X Bank 0 (2MB) 400000H LOCAL-Y Bank 0 (2MB) 600000H : 64MB*(SDRAM case 2MB× 32) or SDCS COMMON-Y (2MB) 800000H LOCAL-Z Bank 0 (4MB) C00000H COMMON-Z (4MB) FFFF00H Vector area FFFFFFH Note1: CSZA is a chip-select for not only bank0 to 127 of LOCAL-Z but also COMMON-Z.
Page 209 LOCAL-X 92CZ26A CSXA to CSXB , EA24 to 28 512MB×2=1024MB CSXA 000000H Bank0 Internal-I/O and Internal RAM CSXB Bank256 Note: In case of connect SDRAM to Y-area, 64MB(2MB×32) is maximum Figure 3.9.2 Recommendation memory map for maximum specification (Physical address) LOCAL-Y LOCAL-Z SDCS or...
Page 210 Address memory map 000000H Internal-I/O, RAM COMMON-X (2MB) 200000H LOCAL-X (2MB) 3FE000H Internal Boot-ROM (8KB) 400000H LOCAL-Y (2MB) 600000H COMMON-Y (2MB) 800000H LOCAL-Z Bank 0 (4MB) C00000H COMMON-Z (4MB) FFFF00H Vector area FFFFFFH Note: In case of connect SDRAM to Z-area, 64MB (4MB Figure 3.9.3Recommendation memory map for simple system (Logical address) 000000H Internal-I/O...
Page 211 3.9.2 Control register There are 24-registers for MMU. They are prepared for 8-purpose using (as Program, read-data, write-data and LCDC-display-data, source-data for odd/even number channel DMA, destination-data for odd/even number channel DMA), and 3-local area (LOCAL-X, Y and Z). These 8-purpose registers can access a data accessed easily. (How to use) At first, set enable register and using bank-number of each LOCAL register.
Page 212 3.9.2.1 Program bank register The bank number used as program memory is set to these registers. In certain bank, cannot diverge directly to different bank of same local area. To change program bank number in the same local area is disable. LOCALPX bit Symbol (880H)
Page 213 3.9.2.2 LCD display bank register The bank page used as LCD display memory is set to these registers. Since the bank register for CPU and LCDC are prepared independently, the bank page for CPU (Program, Read-data, write-data) can change during LCD display on. bit Symbol LOCALLX Read/Write...
Page 214 3.9.2.3 Read-data bank register The bank number used as read-data memory is set to these registers. The following is an example which read data bank register of LOCAL-X is set to “1”. When “ldw wa, (xix)” instruction is executed, the bank becomes effective at only read data (operand) for xix address. (Example) xix, 200000h (localrx), 8001h...
Page 215 3.9.2.4 Write-data bank register The bank number used as write data memory is set to these registers. The following is an example which data bank register of LOCAL-X is set to “1”. When “ldw (xix), wa” instruction is extended, the bank becomes effective at only cycle for xix address. (Example) xix, 200000h (localwx), 8001h...
Page 216 3.9.2.5 DMA-function bank register In addition to functioning as read/write function of CPU, this LSI can also function which transfer data at high-speed by internal DMAC becoming bus master. (Please refer to DMAC section) In Bank for only DMA that different from Bank for CPU or LCDC display data, although condition of program bank, read-bank and write-bank for CPU, bank of Source address and Destination address are enable during operate DMA.
Page 217 bit Symbol LOCALESX Read/Write (8A0H) After reset Function Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.) bit Symbol Read/Write (8A1H) After reset BANK LOCALX Function 0: Disable 1: Enable bit Symbol LOCALESY Read/Write (8A2H) After reset Function bit Symbol Read/Write...
Page 218 bit Symbol LOCALEDX Read/Write (8A8H) After reset Function Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.) bit Symbol Read/Write (8A9H) After reset BANK for LOCALX Function 0: Disable 1: Enable bit Symbol LOCALEDY Read/Write (8AAH) After reset Function bit Symbol...
Page 219 bit Symbol LOCALOSX Read/Write (8B0H) After reset Function Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.) bit Symbol Read/Write (8B1H) After reset BANK LOCALX Function 0: Disable 1: Enable bit Symbol LOCALOSY Read/Write (8B2H) After reset Function bit Symbol (8B3H)
Page 220 bit Symbol LOCALODX (8B8H) Read/Write After reset Function Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.) bit Symbol Read/Write (8B9H) After reset BANK LOCALX Function 0: Disable 1: Enable bit Symbol LOCALODY (8BAH) Read/Write After reset Function bit Symbol (8BBH)
Page 221 3.9.3 Setting example This is in case of using like following condition. Used as Memory Main NOR-Flash Routine (16MB, 1pcs) Character- SRAM Routine (16MB, 1pcs) Display-RAM Stack- Internal-RAM (288KB) (a) Main routine (COMMON-Z) Logical Physical Address Address C00000H <-(Same) C000xxH <- C000yyH <-...
Page 222 (b) Sub routine (Bank-0 in LOCAL-Y) Logical Physical address address 400000H 000000H 4000xxH 0000xxH 5000yyH 1000yyH ・ No.17 and No.18 are setting for Bank-1 of LOCAL-Y. In this case, LCD Display data is written to SRAM by CPU. So, (LOCALWY) and (LOCALLY) should be set to same bank-1. ・...
Page 223 3.10 SDRAM Controller (SDRAMC) The TMP92CZ26A incorporates an SDRAM controller (SDRAMC) for accessing SDRAM that can be used as data memory, program memory, or display memory. The SDRAMC has the following features: (1) Supported SDRAM Data rate type Memory capacity Number of banks Data bus width Read burst length...
Page 224: Control Registers
3.10.1 Control Registers The SDRAMC has the following control registers. Bit symbol SRDS SDACR Read/Write (0250H) After reset Always Read data shift function 0: Disable Function 1: Enable Bit symbol STMRD SDCISR Read/Write (0251H) After reset TMRD Function 0: 1 CLK 1: 2 CLK −...
Page 225 Bit symbol SDCMM Read/Write (0253H) After reset Function Note 1: <SCMM2:0> is automatically cleared to “000” after the specified command is issued. Before writing the next command, make sure that <SCMM2:0> is “000”. In the case of the Self Refresh Entry command, however, <SCMM2:0>...
Page 226 3.10.2 Operation Description (1) Memory access control The SDRAMC is enabled by setting SDACR<SMAC> to “1”. When one of the bus masters (CPU, LCDC, DMAC) generates a cycle to access the SDRAM address area, the SDRAMC outputs SDRAM control signals. Figure3.10.2 to Figure3.10.5 shows the timing for accessing the SDRAM.
Page 227 Address multiplex function In access cycles, the A0 to A15 pins output low/column multiplexed addresses. The multiplex width is set by SDACR<SMUXW1:0>. Table3.10.2 shows the relationship between the multiplex width and low/column addresses. Table3.10.2 Address Multiplex 92CZ26A Pin Name Type A <SMUXW>...
Page 228 4CLK SDCLK SDCKE SDLUDQM SDLLDQM SDCS SDRAS SDCAS SDWE A15-A0 CA (n) D15-D0 tRCD= CAS Latency=2CLK 1CLK Bank Read Active Figure3.10.2 1-Word Read Cycle Timing 4CLK SDCLK SDCKE SDLUDQM SDLLDQM SDCS SDRAS SDCAS SDWE A15-A0 CA (n) D15-D0 tRCD= CAS Latency=2CLK 1CLK Bank Read...
Page 229 3CLK SDCLK SDCKE SDLUDQM SDLLDQM SDCS SDRAS SDCAS SDWE A15-A0 CA (n) D15-D0 D (n) tRCD= tWR= 1CLK 1CLK Bank Write Active Figure3.10.4 Single Write Cycle Timing 2CLK 1CLK SDCLK SDCKE SDLUDQM SDLLDQM SDCS SDRAS SDCAS SDWE A15-A0 CA(n) D15-D0 D(n) tRCD= 1CLK...
Page 230 (2) Execution of instructions on SDRAM The CPU can execute instructions that are stored in the SDRAM. However, the following operations cannot be performed. a) Executing the HALT instruction b) Changing the clock gear setting c) Changing the settings in the SDACR, SDCMM, and SDCISR registers These operations, if needed, must be executed by branching to other memory such as internal RAM.
Page 231 (d) Precharge command SDCLK PRECHARGE COMMAND (e) Read cycle SDCLK ACTIVE COMMAND Row Address A15-A0 D15-D0 Write cycle SDCLK ACTIVE COMMAND Row Address A15-A0 D15-D0 Next Command *TRP=2CLK (SDCISR<STRP>= “1”) READ Non MUX-address Column Address TRCD *TRCD=2CLK (SDCISR<STRCD>= “1”) *TRC=6CLK (SDCISR<STRC2:0>= “101”) WRITE Non MUX-address Column Address...
Page 232 (4) Read data shift function If the AC specifications of the SDRAM cannot be satisfied when data is read from the SDRAM, the read data can be latched in a port circuit so that the CPU can read the data in the next state.
Page 233 (c) Full-page read, the read data shift function enabled (SDACR<SRDS> = “1”, <SRDSCK> = “0”) SDCLK ACTIVE COMMAND Row Address A15-A0 D15-D0 Internal system clock Internal data bus (5) Read/Write commands The Read/Write commands to be used in 1-word read/single write mode can be specified by using SDACR<SPRE>.
Page 234 (6) Refresh control The TMP92CZ26A supports two kinds of refresh commands: Auto Refresh and Self Refresh. (a) Auto Refresh When SDRCR<SRC> is set to “1”, the Auto Refresh command is automatically issued at intervals specified by SDRCR<SRS2:0>. The Auto Refresh interval can be specified in a range of 47 states to 1248 states (0.78 μs to 20.8 μs at f The CPU operation (instruction fetch and execution) is halted while the Auto Refresh command is being executed.
Page 235 (b) Self Refresh The Self Refresh Entry command is issued by setting SDCMM<SCMM2:0> to “101”. Figure3.10.7 shows the Self Refresh cycle timing. Once Self Refresh is started, the SDRAM is refreshed internally without the need to issue the Auto Refresh command. Note 1: When standby mode is released by a system reset, the I/O registers are initialized and the Self Refresh state is exited.
Page 236 The Self Refresh state can be exited by the Self Refresh Exit command. The Self Refresh Exit command is executed when SDCMM<SCMM2:0> is set to “110”. It is also executed automatically in synchronization with HALT mode release. In either of these two cases, Auto Refresh is performed immediately after the Self Refresh state is exited.
Page 237 (7) SDRAM initialization sequence After reset release, the following sequence of commands can be executed to initialize the SDRAM. 1. Precharge All command 2. Eight Auto Refresh commands 3. Mode Register Set command The above commands are issued by setting SDCMM<SCMM2:0> to “001”. While these commands are issued, the CPU operation (instruction fetch, execution) is halted.
Page 238 (8) Connection example Figure3.10.10 shows an example of connections between the TMP92CZ26A and SDRAM. 92CZ26A Pin Name SDCS SDLUDQM SDLLDQM SDRAS SDCAS SDWE SDCKE SDCLK SDACR <SMUXW> TMP92CZ26A Figure3.10.10 An Example of Connections between TMP92CZ26A and SDRAM Table3.10.4 Pin Connections SDRAM Pin Name Data Bus Width 16 bits 128M...
Page 239 3.10.3 An Example of Calculating HDMA Transfer Time The following shows an example of calculating the HDMA transfer time when SDRAM is used as the transfer source. 1) Transfer from SDRAM to internal SRAM Conditions: System clock (f SDRAM read cycle SDRAM Auto Refresh interval Internal RAM write cycle Number of bytes to transfer...
Page 240 3.10.4 Considerations for Using the SDRAMC This section describes the points that must be taken into account when using the SDRAMC. Please carefully read the following to ensure proper use of the SDRAMC. 1) WAIT access When SDRAM is used, the following restriction applies to memory access to other than the SDRAM.
Page 241 3.11 NAND Flash Controller (NDFC) 3.11.1 Features The NAND Flash Controller (NDFC) is provided with dedicated pins for connecting with NAND Flash memory. The NDFC also has an ECC calculation function for error correction and supports two types of ECC calculation methods. The ECC calculation method using Hamming codes can be used for NAND Flash memory of SLC (Single Level Cell) type and is capable of detecting a single-bit error for every 256 bytes.
Page 242 3.11.1 Block Diagram Hamming Generator Code RS ECC Write Control Reed-Solomon Register Generator Address Reed-Solomon Data Calculator Figure 3.11.1 Block Diagram for NAND Flash Controller NAND Flash Controller Channel 0 (NDFC0) ND_CE* ND_ALE ND_CLE ND_RE* ND WE* Timing Generator ND_RB* DATA_OUT[15:0] DATA_IN[15:0] F/F 80-bit...
Page 243 3.11.2 Operation Description 3.11.2.1 Accessing NAND Flash Memory The NDFC accesses data on NAND Flash memory indirectly through its internal registers. This section explains the operations for accessing the NAND Flash. Since no dedicated sequencer is provided for generating commands to the NAND Flash, the levels of the NDCLE, NDALE, and NDCLE NDALE...
Page 244 NDRE NDWE the NAND Flash are performed through the ND0FDTR register. The actual write operation completes not when the ND0FDTR register is written to but when the data is written to the external NAND Flash. Likewise, the actual read operation completes not when the ND0FDTR register is read but when the data is read from the external NAND Flash.
Page 245 3.11.3 ECC Control NAND Flash memory devices may inherently include error bits. It is therefore necessary to implement the error correction processing using ECC (Error Correction Code). Figure 3.11.4 shows a basic flowchart for ECC control. Data Write Valid data write to NAND Flash Valid data write to ECC generator...
Page 246 3.11.3.1 Differences between Hamming Codes and Reed-Solomon Codes The NDFC includes an ECC generator supporting NAND Flash memory devices of SLC (or 2LC: two states) type and MLC (or 4LC: four states) type. The ECC calculation using Hamming codes (supporting SLC) generates 22 bits of ECC for every 256 bytes of valid data and is capable of detecting and correcting a single-bit error for every 256 bytes.
Page 247 3.11.3.2 Error Correction Methods Hamming ECC • The ECC generator generates 44 bits of ECC for a page containing 512 bytes of valid data. The error correction process must be performed in units of 256 bytes (22 bits of ECC). The following explains how to implement error correction on 256 bytes of valid data using 22 bits of ECC.
Page 248 Reed-Solomon ECC • The ECC generator generates 80 bits of ECC for up to 518 bytes of valid data. If the NAND Flash to be used has a large-capacity page size (e.g. 2048 bytes), the error correction process must be repeated several times to cover the entire page.
Page 249 3.11.4 Description of Registers NDFMCR0 bit Symbol (08C0H) Read/Write After reset Read-modify- write enable instructions cannot be 0: Disable used. 1: Enable Function (08C1H) bit Symbol SPLW1 Read/Write Read-modify- write After reset instructions Strobe pulse width cannot be (Low width of NDRE , used.
Page 250 (c) <ECCE> The <ECCE> bit is used for both Hamming and Reed-Solomon codes. This bit is used to enable or disable the ECC generator. To reset the ECC in the ECC generator (to set <ECCRST> to “1”), the ECC generator must be enabled (<ECCE> = “1”). (d) <CE1:0>, <CLE>, <ALE>...
Page 251 (i) <RSECCL> The <RSECCL> bit is used only for Reed-Solomon codes. When using Hamming codes, this bit should be set to “0”. The Reed-Solomon processing unit is comprised of two elements: an ECC generator and an ECC calculator. The latter is used to calculate the error address and error bit position. The error address and error bit position are calculated using an intermediate code generated from the ECC for written data and the ECC for read data.
Page 252 NDFMCR1 bit Symbol INTERDY (08C2H) Read/Write After reset Ready interrupt 0: Disable Function 1: Enable (08C3H) bit Symbol STATE3 Read/Write After reset Function Table 3.11.2 Reed-Solomon Calculation Result Status Table STATE<3:0> 0000 Calculation ended 0 (No error) 0001 Calculation ended 1(5 or more symbols in error; not correctable) 0010 Calculation ended 2 (Error found) 0011...
Page 253 This bit is used to enable or disable the interrupt to be generated when the calculation of error address and error bit position has ended. The interrupt is enabled when this bit is set to “1” and disabled when “0”. (e) <INTRDY>...
Page 254 NDFDTR0 bit Symbol (1FF0H) Read/Write After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Function bit Symbol (1FF1H) Read/Write After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Function NDFDTR1 bit Symbol (1FF2H) Read/Write After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Function bit Symbol (1FF3H)
Page 255 Table 3.11.3 How to Access the NAND Flash Data Register Write Access Data Size Example of instruction 1-byte access ld (0x1FF0),a 2-byte access ld (0x1FF0),wa 4-byte access ld (0x1FF0),xwa Read Access Data Size Example of instruction 1-byte access ld a,(0x1FF0) 2-byte access ld wa,(0x1FF0) 4-byte access...
Page 256 bit Symbol ECCD7 NDECCRD0 (08C4H) Read/Write After reset Function bit Symbol ECCD15 Read/Write (08C5H) After reset Function bit Symbol ECCD7 NDECCRD1 Read/Write (08C6H) After reset Function bit Symbol ECCD15 Read/Write (08C7H) After reset Function NDECCRD2 bit Symbol ECCD7 (08C8H) Read/Write After reset Function bit Symbol...
Page 257 The NAND Flash ECC register is used to read ECC generated by the ECC generator. After valid data has been written to or read from the NAND Flash, setting NDFMCR0<ECCE> to “0” causes the corresponding ECC to be set in this register. (The ECC in this register is updated when NDFMCR0<ECCE>...
Page 258 NAND Flash Reed-Solomon Calculation Result Address Register NDRSCA0 bit Symbol RS0A7 (08D0H) Read/Write After reset Function bit Symbol (08D1H) Read/Write After reset Function NDRSCA1 bit Symbol RS1A7 (08D4H) Read/Write After reset Function bit Symbol (08D5H) Read/Write After reset Function NDRSCA2 bit Symbol RS2A7 (08D8H)
Page 259 If error is found at only one address, the error address is stored in the NDRSCA0 register. If error is found at two addresses, the NDRSCA0 and NDRSCA1 registers are used to store the error addresses. In this manner, up to four error addresses can be stored in the NDRSCA0 to NDRSCA3 registers.
Page 260 3.11.5 An Example of Accessing NAND Flash of SLC Type Initialization ; ***** Initialize NDFC ***** Conditions: 8-bit bus, CE0, SLC, 512 (528) bytes/page, Hamming codes Write Writing valid data ; ***** Write valid data***** Generating ECC → Reading ECC ;...
Page 261 Executing page program ; ***** Set auto page program***** (ndfmcr0),20B0h ; WE enable, CLE enable (ndfdtr0),10h (ndfmcr0),2010h ; WE disable, CLE disable Wait setup time (from Busy to Ready) 1. Flag polling 2. Interrupt Reading status ; ***** Read Status***** (ndfmcr0),20B0h ;...
Page 262 Read Reading valid data ; ***** Read valid data***** (ndfmcr0),2010h ; CE0 enable (ndfmcr0),20B0h ; WE enable, CLE enable (ndfdtr0),00h (ndfmcr0),20D0h ; ALE enable (ndfdtr0),xxh Wait setup time (from Busy to Ready) 1. Flag polling 2. Interrupt (ndfmcr0),2015h ; Reset ECC, ECCE enable, CE0 enable xx,(ndfdtr0) (ndfmcr0),2010h ;...
Page 263 ID Read The ID read routine is as follows: (ndfmcr0),20B0h ; WE Enable, CLE enable (ndfdtr0),90h (ndfmcr0),20D0h ; ALE enable, CLE disable (ndfdtr0),00h (ndfmcr0),2010h ; WE disable, CLE disable xx,(ndfdtr0) xx,(ndfdtr0) ; Write ID read command ; Write 00 ; Read 1'st ID maker code ;...
Page 264 3.11.6 An Example of Accessing NAND Flash of MLC Type as 518byte) Initialization ; ***** Initialize NDFC ***** Conditions: 16-bit bus, CE1, MLC, 2048 (2112) bytes/page, Reed-Solomon codes Write Writing valid data ; ***** Write valid data***** Generating ECC → Reading ECC ;...
Page 265 Writing ECC to NAND Flash ; ***** Write dummy data & ECC ***** (ndfmcr0),5088h ; ECC circuit disable, data write mode (ndfdtr0),xxxxh Write to 207-206hex address: (ndfdtr1),xxxxh Write to 209-208hex address: (ndfdtr0),xxxxh Write to 20B-20Ahex address: (ndfdtr1),xxxxh Write to 20D-20Chex address: (ndfdtr0),xxxxh Write to 20F-20Ehex address: The write operation is repeated four times to write 2112 bytes.
Page 266 Read (including ECC data read) Reading valid data ; ***** Read valid data***** (ndfmcr0),5008h ; CE1 enable (ndfmcr0),50A8h ; WE enable, CLE enable (ndfdtr0),0000h (ndfmcr0),50C8h ; ALE enable (ndfdtr0),00xxh (ndfmcr0),50A8h ; WE enable, CLE enable (ndfdtr0),0030h Wait set up time (from Busy to Ready) 1.
Page 267 ID Read The ID read routine is as follows: (ndfmcr0),50A8h ; WE enable, CLE enable (ndfdtr0),0090h (ndfmcr0),50C8h ; ALE enable, CLE disable (ndfdtr0),0000h (ndfmcr0),5008h ; WE disable, CLE disable xxxx,(ndfdtr0) xxxx,(ndfdtr1) ; Write ID read command ; Write 00 ; Read 1'st ID maker code ;...
Page 268 3.11.7 An Example of Connections with NAND Flash TMP92CZ26A 100K Ω NDCLE NDALE NDRE NDWE 2K Ω NDR/B D[15:0] Note 1: A reset sets the NDRE Note 2: The pull-up resistor value for the NDR/B pin must be set appropriately according to the NAND Flash memory to be used and the capacity of the board (typical: 2 KΩ).
Page 269 3.12 8 Bit Timer (TMRA) The TMP92CZ26A features 8 channel (TMRA0 to TMRA7) built-in 8-bit timers. These timers are paired into 4 modules: TMRA01, TMRA23, TMRA45 and TMRA67. Each module consists of 2 channels and can operate in any of the following 4 operating modes. •...
Page 270 TMP92CZ26A 3.12.1 Block Diagram Figure 3.12.1 TMRA01 Block Diagram 92CZ26A-267...
Page 271 TMP92CZ26A Figure 3.12.2 TMRA23 Block Diagram 92CZ26A-268...
Page 272 TMP92CZ26A Figure 3.12.3 TMRA45 Block Diagram 92CZ26A-269...
Page 273 TMP92CZ26A Figure 3.12.4 TMRA67 Block Diagram 92CZ26A-270...
Page 274 3.12.2 Operation of Each Circuit (1) Prescaler A 9-bit prescaler generates the input clock to TMRA01.The clock φT0 is selected using the prescaler clock selection register SYSCR0<PRCK>. The prescaler operation can be controlled using TA01RUN<TA0PRUN> in the timer control register. Setting <TA0PRUN> to 1 starts the count; setting <TA0PRUN> to 0 clears the prescaler to 0 and stops operation.
Page 275 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes active. If the value set in the timer register is 00H, the signal goes active when the up counter overflows.
Page 276 (4) Comparator (CP0, CP1) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to 0 and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time.
Page 277 3.12.3 SFR Bit symbol TA0RDE TA01RUN Read/Write (1100H) After Reset Function Double buffer 0: Disable 1: Enable TA0REG double buffer control Disable Enable Note: The values of bits 4 to 6 of TA01RUN are “1” when read. Bit symbol TA2RDE TA23RUN Read/Write (1108H)
Page 278 Bit symbol TA4RDE TA45RUN Read/Write (1110H) After Reset Function Double buffer 0: Disable 1: Enable TA4REG double buffer control Disable Enable Note: The values of bits 4 to 6 of TA45RUN are “1” when read. Bit symbol TA6RDE TA67RUN (1118H) Read/Write After Reset Function...
Page 279 TA01MOD Bit symbol TA01M1 TA01M0 (1104H) Read/Write After reset Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA0 input clock <TA0CLK1:0> TMRA1 input clock <TA1CLK1:0> PWM cycle selection <PWM01:00> TMRA01 operation mode selection <TA01MA1:0>...
Page 280 TA23MOD Bit symbol TA23M1 TA23M0 (110CH) Read/Write After reset Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA2 input clock <TA2CLK1:0> TMRA3 input clock <TA3CLK1:0> PWM cycle selection <PWM21:20> TMRA23 operation mode selection <TA23MA1:0>...
Page 281 TA45MOD Bit symbol TA45M1 TA45M0 (1114H) Read/Write After reset Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA4 input clock <TA4CLK1:0> TMRA5 input clock <TA5CLK1:0> PWM cycle selection <PWM41:40> TMRA45 operation mode selection <TA45MA1:0>...
Page 282 TA67MOD Bit symbol TA67M1 TA67M0 (111CH) Read/Write After reset Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA6 input clock <TA6CLK1:0> TMRA1 input clock <TA7CLK1:0> PWM cycle selection <PWM61:60> TMRA67 operation mode selection <TA67MA1:0>...
Page 283 TA1FFCR Bit symbol (1105H) Read/Write After reset Function Read- modify- write instructions prohibited. Inversion signal for timer flip-flop 1 (TA1FF) (Don’t care except in 8-bit timer mode) TA1FFIS Inversion of TA1FF TA1FFIE Control of TA1FF <TA1FFC1:0> Note: The values of bits 4 to 6 of TA1FFCR are “1” when read. TMRA1 Flip-Flop Control Register TA1FFC1 00: Invert TA1FF...
Page 284 TA3FFCR Bit symbol (110DH) Read/Write After reset Read- modify- Function write instructions prohibited. Inversion signal for timer flip-flop 3 (TA3FF) (Don’t care except in 8-bit timer mode) TA3FFIS Inversion of TA3FF TA3FFIE Control of TA3FF <TA3FFC1:0> Note: The values of bits 4 to 6 of TA3FFCR are “1” when read. TMRA3 Flip-Flop Control Register TA3FFC1 00: Invert TA3FF...
Page 285 TA5FFCR Bit symbol (1115H) Read/Write After reset Function Read- modify- write instructions prohibited. Inversion signal for timer flip-flop 5 (TA5FF) (Don’t care except in 8-bit timer mode) TA5FFIS Inversion of TA5FF TA5FFIE Control of TA5FF <TA5FFC1:0> Note: The values of bits 4 to 6 of TA5FFCR are “1” when read. TMRA5 Flip-Flop Control Register TA5FFC1 00: Invert TA5FF...
Page 286 TA7FFCR Bit symbol (111DH) Read/Write After reset Function Read- modify- write instructions prohibited. Inversion signal for timer flip-flop 7 (TA7FF) (Don’t care except in 8-bit timer mode) TA7FFIS Inversion of TA7FF TA7FFIE Control of TA7FF <TA7FFC1:0> Note: The values of bits 4 to 6 of TA7FFCR are “1” when read. TMRA7 Flip-Flop Control Register TA7FFC1 00: Invert TA7FF...
Page 287 − TA0REG bit Symbol (1102H) Read/Write After reset − TA1REG bit Symbol (1103H) Read/Write After reset − TA2REG bit Symbol (110AH) Read/Write After reset − TA3REG bit Symbol (110BH) Read/Write After reset − TA4REG bit Symbol (1112H) Read/Write After reset −...
Page 288 3.12.4 Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. a. Generating interrupts at a fixed interval (Using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register respectively.
Page 289 Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 3.2μs square wave pulse from the TA1OUT pin at f use the following procedure to make the appropriate register settings.
Page 290 Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparator output (TMRA0 match) TMRA0 up counter (when TA0REG = 5) TMRA1 up counter (when TA1REG = 2) TMRA1 match output...
Page 291 The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up counter UC0 is not be cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match.
Page 292 In this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN<TA1RUN>...
Page 293 Example: To generate 1/4 duty 31.25 kHz pulses (at f 32 μs * Clock state Clcok gear : Prescaler of clock gear : 1/2 Calculate the value which should be set in the timer register. To obtain a frequency of 31.25 kHz, the pulse cycle t should be: t = 1/31.25kHz = 32 μs φT1 = 0.16 μs (at 50 MHz);...
Page 294 (4) 8-bit PWM (Pulse width modulation) output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (Shared with PM1).
Page 295 In this mode the value of the register buffer will be shifted into TA0REG if 2 overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG Up counter = Q overflow TA0REG...
Page 296 Clock gear Prescaler of selection clock gear SYSCR1 SYSCR0 <GEAR2:0> <PRCK> φT1(x2) 000(x1) 001(x2) 1024/fc 0(x2) 010(x4) 2048/fc 011(x8) 4096/fc 100(x16) 8192/fc 1/fc 000(x1) 2048/fc 001(x2) 4096/fc 1(x8) 010(x4) 8192/fc 011(x8) 16384/fc 100(x16) 32768/fc (5) Settings for each mode Table 3.12.4 shows the SFR settings for each mode. Register Name <Bit Symbol>...
Page 297 3.13 16 bit timer / Event counter (TMRB) The TMP92CZ26A incorporates two multifunctional 16-bit timer/event counter (TMRB0, TMRB1) which have the following operation modes: • 16 bit interval timer mode • 16 bit event counter mode • 16 bit programmable pulse generation mode (PPG) Can be used following operation modes by capture function.
Page 298 TMP92CZ26A 3.13.1 Block diagram Figure 3.13.1 Block diagram of TMRB0 92CZ26A-295...
Page 299 TMP92CZ26A Figure 3.13.2 Block diagram of TMRB1 92CZ26A-296...
Page 300 3.13.2 Operation (1) Prescaler The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (φT0) selected by the register SYSCR0<PRCK> of clock gear. This prescaler can be started or stopped using TB0RUN<TB0RUN>. Counting starts when <TB0RUN> is set to “1”; the prescaler is cleared to “0” and stops operation when <TB0RUN> is cleared to “0”.
Page 301 (3) Timer registers (TB0RG0H/L, TB0RG1H/L) These two 16-bit registers are used to set the interval time. When the value in the up counter UC10 matches the value set in this timer register, the comparator match detect signal will go active. Setting data for both upper and lower timer registers is needed.
Page 302 TB0RG0H/L and the register buffer 10 both have the same memory addresses (1188H and 1189H) allocated to them. If <TB0RDE> = “0”, the value is written to both the timer register and the register buffer 10. If <TB0RDE> = “1”, the value is written to the register buffer 10 only.
Page 303 (4) Capture registers (TB0CP0H/L, TB0CP1H/L) These 16-bit registers are used to latch the values in the up counter (UC10). Data in the capture registers should be read all 16 bits. For example, using a 2-byte data load instruction or two 1-byte data load instructions. The least significant byte is read first, followed by the most significant byte.
Page 304 (6) Comparators (CP10, CP11) CP10 and CP11 are 16-bit comparators which compare the value in the up counter UC10 with the value set in TB0RG0H/L or TB0RG1H/L respectively, in order to detect a match. If a match is detected, the comparator generates an interrupt (INTTB00 or INTTB01 respectively).
Page 305 3.13.3 SFR Bit symbol TB0RDE TB0RUN Read/Write (1180H) After Reset Double Always buffer write “0” Function 0: disable 1: enable Count operation <TB0PRUN>, <TB0RUN> Note: The 1, 4 and 5 of TB0RUN are read as “1” value. Bit symbol TB1RDE TB1RUN (1190H) Read/Write...
Page 306 − TB0MOD Bit symbol (1182H) Read/Write After Reset Prohibit Function Always write “0”. read- modify- write TMRB0 source clock <TB0CLK1:0> Control clearing for up counter (UC10) <TB0CLE> Capture/interrupt timing <TB0CPM1:0> Software capture <TB0CP0I> TMRB0 Mode Register − TB0CP0I TB0CPM1 TB0CPM0 Capture timing Software 00:Disable...
Page 307 − TB1MOD Bit symbol (1192H) Read/Write After Reset Prohibit Function Always write “0”. read- modify- write TMRB1 source clock <TB1CLK1:0> Control clearing for up counter (UC12) <TB1CLE> Capture/interrupt timing <TB1CPM1:0> Software capture <TB1CP0I> TMRB1 Mode Register − TB1CP0I TB1CPM1 TB1CPM0 Capture timing Software 00:Disable...
Page 308 − TB0FFCR Bit symbol (1183H) Read/Write After Reset Function Prohibit Always write “11” read- modify- write *Always read as “11”. Timer flip-flop control(TB0FF0) <TB0FF0C1:0> TB0FF0 control Inverted when UC10 value matches the valued in TB0RG0H/L <TB0E0T1> TB0FF0 control Inverted when UC10 value matches the valued in TB0RG1H/L <TB0E1T1>...
Page 309 − TB1FFCR Bit symbol (1193H) Read/Write After Reset Function Prohibit Always write “11” read- modify- write *Always read as “11”. Timer flip-flop control(TB1FF0) <TB1FF0C1:0> TB1FF0 control Inverted when UC12 value matches the valued in TB1RG0H/L <TB1E0T1> TB1FF0 control Inverted when UC12 value matches the valued in TB1RG1H/L <TB1E1T1>...
Page 310 − TB0RG0L bit Symbol (1188H) Read/Write After reset − TB0RG0H bit Symbol (1189H) Read/Write After reset − TB0RG1L bit Symbol (118AH) Read/Write After reset − TB0RG1H bit Symbol (118BH) Read/Write After reset − TB1RG0L bit Symbol (1198H) Read/Write After reset −...
Page 311 3.13.4 Operation in Each Mode (1) 16 bit timer mode Generating interrupts at fixed intervals In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The interval time is set in the timer register TB0RG1H/L. ← TB0RUN –...
Page 312 (3) 16-bit programmable pulse generation (PPG) output mode Square wave pulses can be generated at any frequency and duty ratio. The output pulse may be either low active or high active. The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is to be enabled by the match of the up counter UC10 with timer register TB0RG0H/L or TB0RG1H/L and to be output to TB0OUT0.
Page 313 The following block diagram illustrates this mode. Selector TB0IN0 φT1 φT4 φT16 16-bit comparator Selector TB0RG0H/L TB0RG0-WR Register buffer 0 TB0RUN<TB0RDE> Figure 3.13.11 Block Diagram of 16-Bit Mode The following example shows how to set 16-bit PPG output mode: ← TB0RUN ←...
Page 314 (4) Application examples of capture function Used capture function, they can be applied in many ways, for example; One-shot pulse output from external trigger pulse Frequency measurement Pulse width measurement One-shot pulse output from external trigger pulse Set the up counter UC10 in free-running mode with the internal input clock, input the external trigger pulse from TB0IN0 pin, and load the value of up counter into capture register TB0CP0H/L at the rising edge of the TB0IN0 pin.
Page 315 Example: To output 2ms one-shot pulse with 3ms delay to the external trigger pulse to TB0IN0pin Main setting ← X TB0MOD ← X TB0FFCR ← PPFC – – – – ← X INTE56 ← X INTETB0 ← TB0RUN – – Setting in INT6 routine ←...
Page 316 Count clock (Prescaler output clock ) TB0IN0 iput (External trigger pulse) Match with TB0RG1H/L Timer output pin TB0OUT0 Enable inversioncaused by loading to TB0CP0H/L Figure 3.13.13 One-shot Pulse Output (without delay) Frequency measurement The frequency of the external clock can be measured in this mode. The clock is input through the TB0IN0 pin, and its frequency is measured by the 8 bit timers TMRA01 and the 16 bit timer/event counter (TMRB0).
Page 317 Pulse width measurement This mode allows measuring the H level width of an external pulse. While keeping the 16 bit timer/event counter counting (free-running) with the internal clock input, the external pulse is input through the TB0IN0 pin. Then the capture function is used to load the UC10 values into TB0CP0H/L and TB0CP1H/L at the rising edge and falling edge of the external trigger pulse respectively.
Page 318 3.14 Serial Channels (SIO) TMP92CZ26A includes 1 serial I/O channel (SIO0). For both channels either UART mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected. And, SIO0 includes data modulator that supports the IrDA 1.0 infrared data communication specification.
Page 319 3.14.1 Block Diagram Prescaler φT0 4 8 16 32 φT2 φT8 φT32 Serial clock generation circuit BR0CR<BR0CK1:0> BR0CR <BR0S3:0> φT0 φT2 φT8 φT32 BR0CR <BR0ADDE> Baud rate generator SCLK0 I/O interface mode SCLK0 Receive counter (UART only ÷ 16) RXDCLK SC0MOD0 Receive <RXE>...
Page 320 3.14.2 Operation of Each Circuit (1) Prescaler There is a 6-bit prescaler for generating a clock to SIO0. The prescaler can be run by selecting the baud rate generator as the serial transfer clock. Table 3.14.1 shows prescaler clock resolution into the baud rate generator. Table 3.14.1 Prescaler Clock Resolution to Baud Rate Generator Clock gear SYSCR1...
Page 321 (2) Baud rate generator The baud rate generator is the circuit which generates transmission/receiving clock and determines the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is generated by the 6-bit prescaler which is shared by the timers.
Page 322 • Integer divider (N divider) For example, when the source clock frequency (f clock is φT2, the frequency divider N (BR0CR<BR0S3:0>) = 8, and BR0CR<BR0ADDE> = 0, the baud rate in UART Mode is as follows: *Clock state System clock Prescaler clock ÷...
Page 323 Table 3.14.2 Transfer Rate Selection (When baud rate generator is used and BR0CR<BR0ADDE> = 0) [MHz] Frequency Divider N 7.3728 ↑ ↑ ↑ ↑ ↑ 9.8304 ↑ ↑ ↑ ↑ ↑ 44.2368 ↑ 58.9824 ↑ ↑ ↑ ↑ ↑ ↑ 73.728 ↑...
Page 324 (3) Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • In I/O Interface Mode In SCLK Output Mode with the setting SC0CR<IOC> = 0, the basic clock is generated by dividing the output of the baud rate generator by 2, as described previously.
Page 325 (6) The Receiving Buffers To prevent Overrun errors, the Receiving Buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in Receiving Buffer 1 (which is a shift register). When 7 or 8 bits of data have been stored in Receiving Buffer 1, the stored data is transferred to Receiving Buffer 2 (SC0BUF);...
Page 326 TMP92CZ26A (8) Transmission controller • In I/O Interface Mode In SCLK Output Mode with the setting SC0CR<IOC> = 0, the data in the Transmission Buffer is output one bit at a time to the TXD0 pin on the rising edge or falling of the shift clock which is output on the SCLK0 pin, according to the SC0CR<SCLKS>...
Page 327 Handshake function Serial Channels 0 has a one frame; thus, Overrun errors can be avoided. The handshake functions is enabled or disabled by the SC0MOD <CTSE> setting. When the transmission is halted until the Interrupt is generated, it requests the next data send to the CPU. The next data is written in the Transmission Buffer and data sending is halted.
Page 328 (9) Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU form the least significant bit (LSB) in order. When all the bits are shifted out, the transmission buffer becomes empty and generates an INTTX0 interrupt.
Page 329 Parity error <PERR> The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is compared with the parity bit received via the RXD pin. If they are not equal, a parity error is generated. Note: The parity error flag is cleared every time it is read. However, if a parity error is detected w¥twice in succession and the parity error flag is read between the two parity errors, it may seem as if the flag had not been cleared.
Page 330 (12) Timing generation In UART Mode Receiving Mode (Note) Interrupt timing Center of last bit (bit 8) Framing error timing Center of stop bit Parity error timing Overrun error timing Center of last bit (bit 8) Note1: In 9-Bit and 8-Bit + Parity Modes, interrupts coincide with the ninth bit pulse. Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to be transferred) to allow checking for a framing error.
Page 331 3.14.3 SFR Bit symbol SC0MOD0 Read/Write (1202H) After Reset Transfer Hand shake data bit 8 0: CTS 1: CTS Function Figure 3.14.6 Serial Mode Control Register (channel 0, SC0MOD0) CTSE Receive Wake up Serial Transmission function function Mode 00: I/O interface Mode disable 0: Receive 0: disable...
Page 332 bit Symbol EVEN SC0CR Read/Write (1201H) After Reset Undefined Received Parity Prohibit data bit 8 0: odd to Read 1: even modify Function Write Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction.
Page 333 − Bit symbol BR0ADDE BR0CR Read/Write (1203H) After Reset +(16−K)/16 Always write “0” division 0: Disable Function 1: Enable +(16−K)/16 division enable Disable Enable bit Symbol Read/Write BR0ADD After reset (1204H) Function Sets baud rate generator frequency divisor BR0CR<BR0ADDE> = 1 BR0CR 0000(N = 16) <BR0S3:0>...
Page 334 SC0BUF (1200H) Note: Prohibit read modify write for SC0BUF. Figure 3.14.9 Serial Transmission/Receiving Buffer Registers (channel 0, SC0BUF) Bit symbol I2S0 SC0MOD1 (1205H) Read/Write After Reset IDLE2 Function 0: Stop 1: Run Figure 3.14.10 Serial Mode Control Register 1 (channel 0, SC0MOD1) FDPX0 duplex 0: half...
Page 335 Operation in each mode 3.14.4 (1) Mode 0 (I/O Interface Mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK output mode to output synchronous clock SCLK and SCLK input mode to input external synchronous clock SCLK.
Page 336 Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes the data to the Transmission Buffer. When all data is output, INTES0 <ITX0C> will be set to generate the INTTX0 interrupt. Timing to write transmisison data SCLK0 output...
Page 337 Receiving In SCLK Output Mode the synchronous clock is output on the SCLK0 pin and the data is shifted to Receiving Buffer 1. This is initiated when the Receive Interrupt flag INTES0<IRX0C> is cleared as the received data is read. When 8-bit data is received, the data is transferred to Receiving Buffer 2 (SC0BUF) following the timing shown below and INTES0<IRX0C>...
Page 338 Transmission and Receiving (Full Duplex Mode) When Full Duplex Mode is used, set the Receive Interrupt Level to 0 and set enable the level of transmit interrupt(1 to 6). Ensure that the program which transmits the interrupt reads the receiving buffer before setting the next transmit data. The following is an example of this: Example: Channel 0, SCLK output...
Page 339 (2) Mode 1 (7-bit UART Mode) 7-Bit UART Mode is selected by setting the Serial Channel Mode Register SC0MOD0<SM1:0> field to 01. In this mode a parity bit can be added. Use of a parity bit is enabled or disabled by the setting of the Serial Channel Control Register SC0CR<PE>...
Page 340 Main routine ← X P9CR ← − − P9FC ← − − SC0MOD0 ← − SC0CR ← 0 BR0CR ← X INTES0 Interrupt routine ← SC0CR AND 00011100 ≠ 0 then ERROR if A ← SC0BUF X: Don't care, −: No change (4) Mode 3 (9-Bit UART Mode) 9-Bit UART Mode is selected by setting SC0MOD0<SM1:0>...
Page 341 Protocol Select 9-Bit UART Mode on the master and slave controllers. Set the SC0MOD0<WU> bit on each slave controller to 1 to enable data receiving. The master controller transmits data one frame at a time. Each frame includes an 8-bit select code which identifies a slave controller.
Page 342 Setting example: To link two slave controllers serially with the master controller using the internal clock f as the transfer clock. Master • Setting the master controller Main routine ← X X X X X − 0 1 P9CR ← − − X X X − X 1 P9FC ←...
Page 343 3.14.5 Support for IrDA SIO0 includes support for the IrDA 1.0 infrared data communication specification. Figure 3.14.8 shows the block diagram. Transmisison IR modulator data SIO0 Modem Receive IR demodulator data TMP92CZ26A Figure 3.14.18 Block Diagram (1) Modulation of the transmission data When the transmit data is 0, the modem outputs 1 to TXD0 pin with either 3/16 or 1/16 times for width of baud-rate.
Page 344 (3) Data format The data format is fixed as follows: • Data length: • Parity bits: • Stop bits: (4) SFR Figure 3.14.21 shows the control register SIRCR. Set the data SIRCR during SIO0 is stopping. The following example describes how to set this register: 1) SIO setting ↓...
Page 345 (5) Notes 1. Baud rate for IrDA When IrDA is operated, set 01 to SC0MOD0<SC1:0> to generate baud-rate. The setting except above (TA0TRG, f 2. The pulse width for transmission The IrDA 1.0 specification is defined in Table 3.14.3. Table 3.14.3 Baud rate and pulse width specifications Rate Tolerance Baud Rate Modulation...
Page 346 Bit symbol PLSEL RXSEL SIRCR (1207H) Read/Write After reset Select Receive transmit pulse width 0: “H” pulse Function 0: 3/16 1: “L” pulse 1: 1/16 TXEN RXEN SIRWD3 Transmit Receive Select receive pulse width Set effective pulse width for equal or more than 2x × data 0: disable 0: disable...
Page 347 3.15 Serial Bus Interface (SBI) The TMP92CZ26A has a 1-channel serial bus interface which an I supports only I C bus mode (Multi master). The serial bus interface is connected to an external device through PV6 (SDA) and PV7 (SCL) in the I C bus mode.
Page 348 3.15.2 Serial Bus Interface (SBI) Control The following registers are used to control the serial bus interface and monitor the operation status. Serial bus interface control register 0 (SBICR0) Serial bus interface control register 1 (SBICR1) Serial bus interface control register 2 (SBICR2) Serial bus interface data buffer register (SBIDBR) C bus address register (I2CAR) Serial bus interface status register (SBISR)
Page 349 3.15.4 I C Bus Mode Control Register The following registers are used to control and monitor the operation status when using the serial bus interface (SBI) in the I Bit symbol SBIEN SBICR0 (1247H) Read/Write After Reset Function Always read “0”. Prohibit Read- operation...
Page 350 Bit symbol SBICR1 (1240H) Read/Write After Reset Prohibit Function Number of transferred bits Read- (Note 1) modify- write Note1: For the frequency of the SCL line clock, see 3.15.5 (3) Serial clock. Note2: The initial data of SCK0 is “0”, the initialdata of SWRMON is “1” if SBI operation is enable (SBICR0<SBIEN>=“1”).
Page 351 SBICR2 Bit symbol (1243H) Read/Write After reset Prohibit Function Master/Slave Transmitter Read- selection /Receiver modify- 0:Slave selection write 1:Master 0:Receiver 1:Transmitter Note 1: Reading this register functions as SBISR register. Note 2: Switch a mode to port mode after confirming that the bus is free. Switch a mode between I high-level.
Page 352 SBISR Bit symbol (1243H) Read/Write After reset Prohibit Function Master/ Transmitter/ Read-modif Slave status Receiver y-write monitor status 0:Slave monitor 1:Master 0:Receiver 1:Tranmitter Note1: Writing in this register functions as SBICR2. Note2: The initialdata SBISR<PIN> is “1” if SBI operation is enable (SBICR0<SBIEN>=“1”). If SBI operation is disable (SBICR0<SBIEN>=“0”), the initialdata of SBISR<PIN>...
Page 353 − SBIBR0 Bit symbol (1244H) Read/Write Prohibit After reset Read-modify Function Always -write read “0” SBIDBR Bit symbol (1241H) Read/Write Prohibit After reset Read-modify -write Note1: When writing transmitted data, start from the MSB (bit 7).Receiving data is placed from LSB(bit0). Note2: SBIDBR can’t be read the written data because of it has buffer for writing and buffer for reading individually.Therefore Read modify write instruction (e.g.“BIT”...
Page 354 3.15.5 Control in I C Bus Mode Acknowledge Mode Specification When slave address is matched or detecting GENERAL CALL, and set the SBICR1<ACK> to “1”, TMP92CZ26A operates in the acknowledge mode. The TMP92CZ26A generates an additional clock pulse for an Acknowledge signal when operating in Master Mode.
Page 355 b. Clock synchronization In the I C bus mode, in order to wired-AND a bus, a master device which pulls down a clock line to low-level, in the first place, invalidate a clock pulse of another master device which generates a high-level clock pulse. The master device with a high-level clock pulse needs to detect the situation and implement the following procedure.
Page 356 Transmitter/Receiver selection Set the SBICR2<TRX> to “1” for operating the TMP92CZ26A as a transmitter. Clear the <TRX> to “0” for operation as a receiver. In Slave Mode, Data with an addressing format is transferred A slave address with the same value that an I2CAR A GENERAL CALL is received (all 8-bit data are “0”...
Page 357 Interrupt service requests and interrupt cancellation When a serial bus interface interrupt request (INTSBI) occurs, the SBICR2 <PIN> is cleared to “0”. During the time that the SBICR2<PIN> is “0”, the SCL line is pulled down to the Low level. The <PIN>...
Page 358 lost and SBISR<AL> is set to “1”. When SBISR<AL> is set to “1”, SBISR<MST, TRX> are cleared to “00” and the mode is switched to Slave Receiver Mode. Thus, clock output is stopped in data transfer after setting <AL>=“1”. SBISR<AL> is cleared to “0” when data is written to or read from SBIDBR or when data is written to SBICR2.
Page 359 (14) Software Reset function The software Reset function is used to initialize the SBI circuit, when SBI is rocked by external noises, etc. An internal Reset signal pulse can be generated by setting SBICR2<SWRST1:0> to “10” and “01”. This initializes the SBI circuit internally. All command registers and status registers are initialized as well.
Page 360 3.15.6 Data Transfer in I C Bus Mode (1) Device initialization Set the SBICR1<ACK, SCK2:0>, Set SBIBR1 to “1” and clear bits 7 to 5 and 3 in the SBICR1 to “0”. Set a slave address <SA6:0> and the <ALS> (<ALS> = “0” when an addressing format) to the I2CAR.
Page 361 b. Slave Mode In the Slave Mode, the start condition and the slave address are received. After the start condition is received from the master device, while eight clocks are output from the SCL pin, the slave address and the direction bit that are output from the master device are received.
Page 362 (3) 1-word Data Transfer Check the <MST> by the INTSBI interrupt process after the 1-word data transfer is completed, and determine whether the mode is a master or slave. a. If <MST> = “1” (Master Mode) Check the <TRX> and determine whether the mode is a transmitter or receiver.
Page 363 When the <TRX> is “0” (Receiver mode) When the next transmitted data is other than 8 bits, set <BC2:0> <ACK> and read the received data from SBIDBR to release the SCL line (data which is read immediately after a slave address is sent is undefined). After the data is read, <PIN>...
Page 364 Example: In case receive data N times INTSBI interrupt (After transmitting data) 7 6 5 4 3 2 1 0 ← X X X X X X X X SBICR1 ← SBIDBR Reg. End of interrupt INTSBI interrupt (Receive data of 1st to (N−2) th) 7 6 5 4 3 2 1 0 ←...
Page 365 b. If <MST> = 0 (Slave Mode) In the slave mode the TMP92CZ26A operates either in normal slave mode or in slave mode after losing arbitration. In the slave mode, an INTSBI interrupt request occurs when the TMP92CZ26A receives a slave address or a GENERAL CALL from the master device, or when a GENERAL CALL is received and data transfer is complete, or after matching received address.
Page 366 <TRX> <AL> <AAS> <AD0> Table 3.15.2 Operation in the slave mode Conditions The TMP92CZ26A loses arbitration when transmitting a slave address and receives a slave address for which the value of the direction bit sent from another master is “1”. In Salve Receiver Mode, the TMP92CZ26A receives a slave address for which the value of the direction bit...
Page 367 (4) Stop condition generation When SBISR<BB> = “1”, the sequence for generating a stop condition start by writing “1” to SBICR2<MST, TRX, PIN> and “0” to SBICR2<BB>. Do not modify the contents of SBICR2<MST, TRX, PIN, BB> until a stop condition has been generated on the bus.
Page 368 (5) Restart Restart is used during data transfer between a master device and a slave device to change the data transfer direction. The following description explains how to restart when the TMP92CZ26A is in Master Mode. Clear SBICR2<MST, TRX, and BB> to 0 and set SBICR2<PIN> to 1 to release the bus.
Page 369 3.16 USB Controller 3.16.1 Outline This USB controller (UDC) is designed for various serial links to construct USB system. The outline is as follows: (1) Compliant with USB rev1.1 (2) Full-speed: 12 Mbps (Not supported low-speed (1.5 Mbps)) (3) Auto bus enumeration with 384-byte descriptor RAM (4) Supported 3 kinds of transfer type: Control, interrupt and bulk Endpoint 0: Endpoint 1:...
Page 370 3.16.1.1 System Configuration The USB controller (UDC) is consisted of following 3 blocks. 900/H1 CPU I/F UDC core block (DPLL, SIE, IFM and PWM), request controller, descriptor RAM and 4 endpoint FIFO USB transceiver About above “1.” is explained at 3.16.2, and “2.” is 3.16.3. Descriptor RAM 384 bytes UDC core...
Page 371 3.16.1.2 Example USB host USB host Connector Connector VBUS cable If using USB controller in TMP92CZ26A, above setting is needed. 1) Pull-up of D ・ In the USB standard, in Full Speed connection, D And this pull-up is needed ON/OFF control by S/W. Recommendation value: R1=1.5kΩ...
Page 372 3.16.2 900/H1 CPU I/F The 900/H1 CPU I/F is a bridge between 900/H1 CPU and UDC and it mainly works following operations. • INTUSB (interrupt from UDC) generation • A bridge for SFR • USB clock control (48 MHz) 3.16.2.1 SFRs The 900/H1 CPU I/F have following SFRs to control UDC and USB transceiver.
Page 373 3.16.2.2 USBCR1 Register This register is used to set USB clock enables, transceiver enable etc. bit Symbol TRNS_USE USBCR1 (07F8H) Read/Write After reset Function • TRNS_USE • WAKEUP Current_Config<REMOTE WAKEUP>. and “0” to <WAKEUP> after checking by this, remote-wakeup-function will be started.
Page 374 3.16.2.3 USBINTFRn, MRn Register These SFRs control to generate INTUSB (only one interrupt to CPU) because the UDC outputs 23 interrupt source. The USBINTMRn are mask registers and the USBINTFRn are flag registers. In the INTUSB routine, execute operations according to generated interrupt source after checking USBINTFRn.
Page 375 bit Symbol INT_URST_STR USBINTFR1 (07F0H) Read/Write Prohibit After reset to read Function When read 0: Not generate interrupt modify write Note: Above interrupts can release Halt state from IDLE2 and IDLE1 mode. (STOP mode can not be released) *Those 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode. Therefore, the system of low power dissipation can be built.
Page 376 bit Symbol EP1_FULL_A USBINTFR2 (07F1H) Read/Write After reset Prohibit to read Function modify write Note: Above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode can not be released.) bit Symbol USBINTFR3 EP3_FULL_A (07F2H) Read/Write After reset Prohibit to read Function...
Page 377 bit Symbol INT_SETUP USBINTFR4 (07F3H) Read/Write After reset Prohibit to read Function When read modify write Note: Above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode can not be released.) • • • INT_EP0 INT_STAS INT_STASN 0: Not generate interrupt 1: Generate interrupt INT_SETUP (Bit7)
Page 378 • INT_STASN (Bit4) This is a flag for INT_STASN (change host status stage - interrupt). This is set to “1” when the USB host change to status stage at the Control read transfer type. This interrupt is needed if data length is less than wLength (specified by the host).
Page 379 bit Symbol MSK_URST_STR USBINTMR1 (07F4H) Read/Write After reset Function • • • • • • MSK_URST_END MSK_SUS MSK_RESUME 0: Be not masked 1: Be masked MSK_URST_STR (Bit7) This is a mask register for USBINTFR1<INT_URST_STR>. MSK_URST_END (Bit6) This is a mask register for USBINTFR1<INT_URST_END>. MSK_SUS (Bit5) This is a mask register for USBINTFR1<INT_SUS>.
Page 380 bit Symbol USBINTMR2 EP1_MSK_FA (07F5H) Read/Write After reset Function • bit Symbol EP3_MSK_FA USBINTMR3 (07F6H) Read/Write After reset Function 0: Be not masked 1: Be masked • EP1_MSK_EA EP1_MSK_FB EP1_MSK_EB 0: Be not masked 1: Be masked EP1/2_MSK_FA/FB/EA/EB This is a mask register for USBINTFR2<EPx_FULL_A/B> or <EPx_Empty_A/B>.
Page 381 bit Symbol MSK_SETUP USBINTMR4 (07F7H) Read/Write After reset Function • • • • • • • MSK_EP0 MSK_STAS MSK_STASN 0: Be not masked 1: Be masked MSK_SETUP (Bit7) This is a mask register for USBINTFR4<INT_SETUP>. MSK_EP0 (Bit6) This is a mask register for USBINTFR4<INT_EP0>. MSK_STAS (Bit5) This is a mask register for USBINTFR4<INT_STAS>.
Page 382 3.16.3 UDC CORE 3.16.3.1 SFRs The UDC CORE has following SFRs to control UDC and USB transceiver. FIFO Endpoint 0 to 3 FIFO register Device request bmRequestType wValue_L wIndex_L wLength_L Status Current_Config StandardRequest EPx_STATUS d) Setup EPx_BCS Standard Request Mode Descriptor RAM Control EPx_MODE...
Page 383 Figure 3.16.3 UDC CORE SFRs (1/3) Address Read/Write 0500H Descriptor RAM0 0501H Descriptor RAM1 0502H Descriptor RAM2 0503H Descriptor RAM3 067DH Descriptor RAM381 067EH Descriptor RAM382 067FH Descriptor RAM383 0780H ENDPOINT0 0781H ENDPOINT1 0782H ENDPOINT2 0783H ENDPOINT3 *0784H ENDPOINT4 *0785H ENDPOINT5 *0786H ENDPOINT6...
Page 384 Figure 3.16.4 UDC CORE SFRs (2/3) Address Read/Write 07A9H EP1_SIZE_H_A 07AAH EP2_SIZE_H_A 07ABH EP3_SIZE_H_A *07ACH EP4_SIZE_H_A *07ADH EP5_SIZE_H_A *07AEH EP6_SIZE_H_A *07AFH EP7_SIZE_H_A 07B1H EP1_SIZE_H_B 07B2H EP2_SIZE_H_B 07B3H EP3_SIZE_H_B *07B4H EP4_SIZE_H_B *07B5H EP5_SIZE_H_B *07B6H EP6_SIZE_H_B *07B7H EP7_SIZE_H_B 07C0H bmRequestType 07C1H bRequest 07C2H wValue_L 07C3H...
Page 385 Figure 3.16.5 UDC CORE SFRs (3/3) Address Read/Write 07E0H Port_Status 07E1H FRAME_L 07E2H FRAME_H 07E3H ADDRESS – *07E4H Reserved – *07E5H Reserved 07E6H USBREADY – *07E7H Reserved 07E8H Set Descriptor STALL Note: “*” is not used at TMP92CZ26A. 92CZ26A-382 TMP92CZ26A SFR Symbol...
Page 386 3.16.3.2 EPx_FIFO Register (x: 0 to 3) This register is prepared for each endpoint independently. This is the window register from or to FIFO RAM. In the auto bus enumeration, the request controller in UDC set mode, which is defined at endpoint descriptor for each endpoint automatically. By this, each endpoint is set to voluntary direction.
Page 387 3.16.3.3 bmRequestType Register This register shows the bmRequestType field of device request. bmRequestType bit Symbol DIRECTION (07C0H) Read/Write After reset DIRECTION (Bit7) REQ_TYPE [1:0] (Bit6 to bit5) RECEIPIENT [4:0] (Bit4 to bit0) 3.16.3.4 bRequest Register This register shows the bRequest field of device request. bRequest bit Symbol REQUEST7...
Page 388 3.16.3.5 wValue Register There are 2 registers; the wValue_L register and wValue_H register. wValue_L shows the lower-byte of wValue field of device request and wValue_H register shows upper byte. wValue_L bit Symbol VALUE_L7 (07C2H) Read/Write After reset wValue_H bit Symbol VALUE_H7 (07C3H) Read/Write...
Page 389 3.16.3.8 Setup Received Register This register informs for the UDC that an application program recognized INT_SETUP interrupt. SetupReceived bit Symbol (07C8H) Read/Write After reset If this register is accessed by an application program, the UDC release to disabling access to EP0’s FIFO RAM because the UDC recognized the device request is received. This is to protect data stored in EP0 in the time from continuous request has been asserted to an application program recognized INT_SETUP interrupt.
Page 390: Table Of Contents
3.16.3.10 Standard Request Register This register shows the standard request that is executing now. A bit which is set to “1” shows present executing request. Standard Recuest bit Symbol S_INTERFACE G_INTERFACE (07CAH) Read/Write After reset S_INTERFACE G_INTERFACE S_CONFIG G_CONFIG G_DESCRIPT S_FEATURE C_FEATURE G_STATUS...
Page 391 3.16.3.12 DATASET Register This register shows whether FIFO has data or not. The application program can be checked it by accessing this register that whether FIFO has data or not. In the receiving status, when valid data transfer from USB host finished, bit which correspond to applicable endpoint is set to “1”...
Page 392 Note1: In the receiving mode, if bits that A-packet and B-packet of applicable endpoint are “1”, read data that packet-number should be received, after checking DATASIZE<PACKET_ACTIVE>. Note2: In the transmitting mode, if the both A and B bits are not “1”, it means that there are space in FIFO. So, write data for payload or less to FIFO.
Page 393 3.16.3.13 EPx_STATUS Register (x: 0 to 7) These registers are status registers for each endpoint. The <SUSPEND> is common for all endpoint. bit Symbol EP0_STATUS (0790H) Read/Write After reset bit Symbol EP1_STATUS Read/Write (0791H) After reset bit Symbol EP2_STATUS (0792H) Read/Write After reset EP3_STATUS...
Page 394 STATUS [2:0] (Bit4 to bit2) 000: READY Receiving: Transmitting: 001: DATAIN 010: FULL 011: TX_ERR 100: RX_ERR 101: BUSY 110: STALL 111: INVALID These bits show status of endpoint of UDC. The status show whether transfer it or not, or show result of transfer.
Page 395 FIFO_DISABLE (Bit1) 0: FIFO enabled 1: FIFO disabled STAGE_ERROR (Bit0) 0: SUCCESS 1: ERROR This bit symbol shows FIFO status except EP0. If the FIFO is set to disabled, the UDC transmits NAK handshake forcibly for the all transfer. Disabled or enabled is set by COMMAND register.
Page 396 3.16.3.14 EPx_SIZE Register (x: 0 to 7) These registers have following function. In the receiving, showing data number for 1 packet which was received correctly. b) In the transmitting, it shows payload size. But it shows length value when short packet is transferred.
Page 397 bit Symbol EP1_SIZE_L_B Read/Write (07A1H) After reset bit Symbol EP2_SIZE_L_B Read/Write (07A2H) After reset EP3_SIZE_L_B bit Symbol (07A3H) Read/Write After reset EP4_SIZE_L_B bit Symbol (07A4H) Read/Write After reset bit Symbol EP5_SIZE_L_B (07A5H) Read/Write After reset bit Symbol EP6_SIZE_L_B Read/Write (07A6H) After reset bit Symbol EP7_SIZE_L_B...
Page 398 EP1_SIZE_H_A bit Symbol (07A9H) Read/Write After reset bit Symbol EP2_SIZE_H_A (07AAH) Read/Write After reset bit Symbol EP3_SIZE_H_A Read/Write (07ABH) After reset bit Symbol EP4_SIZE_H_A Read/Write (07ACH) After reset bit Symbol Read/Write EP5_SIZE_H_A (07ADH) After reset bit Symbol Read/Write EP6_SIZE_H_A After reset (07AEH) bit Symbol Read/Write...
Page 399 EP1_SIZE_H_B (07B1H) bit Symbol Read/Write After reset EP2_SIZE_H_B (07B2H) bit Symbol Read/Write After reset EP3_SIZE_H_B bit Symbol (07B3H) Read/Write After reset EP4_SIZE_H_B bit Symbol (07B4H) Read/Write After reset bit Symbol EP5_SIZE_H_B (07B5H) Read/Write After reset bit Symbol EP6_SIZE_H_B Read/Write (07B6H) After reset EP7_SIZE_H_B bit Symbol...
Page 400 3.16.3.15 FRAME Register This register shows frame number which is issued with SOF token from the host and is used for Isochronous transfer type. Each HIGH and LOW registers show upper and lower bits. − FRAME_L bit Symbol (07E1H) Read/Write After reset bit Symbol T[10]...
Page 401 3.16.3.17 EOP Register This register is used when a dataphase of control transfer type terminate or when a short packet is transmitting of bulk-IN, interrupt-IN. bit Symbol EP7_EOPB EP6_EOPB (07CFH) Read/Write After reset Note: EOP<EP7_EOPB, EP6_EOPB, EP5_EOPB, EP4_EOPB> registers are not used at TMP92CZ26A. In a dataphase of control transfer type, write “0”...
Page 402 3.16.3.18 Port Status Register This register is used when a request of printer class is received. In case of request of GET_PORT_STATUS, the UDC operates automatically by using this data. bit Symbol Port Status Reserved7 (07E0H) Read/Write After reset Note: TMP92CZ26A don’t use this register because of not support to printer-class. The data should be written before receiving request.
Page 403: Soft_Reset
3.16.3.20 Request Mode Register This register set answer for Class Request either answer automatically in Hardware or control in software. Each bit mean kind of request. When this register is set applicable bit to “0”, answer is executed automatically by hardware.
Page 404 3.16.3.21 COMMAND Register This register sets COMMAND at each endpoint. This register can be set selection of endpoint in bit6 to bit4 and kind of COMMAND in bit3 to bit0. COMMAND for endpoint that is supported is ignored. COMMAND bit Symbol (07D0H) Read/Write After reset...
Page 405 1000: FIFO_ENABLE This COMMAND set FIFO of applicable endpoint to enable (EP1 to EP3). If FIFO is set to disable by FIFO_DISABLE COMMAND, this command is used for release disable condition. If during receiving packet, this becomes valid from next token. If USB_RESET is detected from host and RESET COMMAND execute and transfer mode is set by using SET_CONFIG and SET_INTERFACE request, applicable endpoint become FIFO_ENABLE condition.
Page 406 3.16.3.22 INT_Control Register INT_STASN interrupt is disabled and enabled by value that is written to this register. This is initialized to disable by external reset. When setup packet is received, it becomes to disable. INT_Control bit Symbol (07D6H) Read/Write After reset In control read transfer, if host terminate dataphase in small data length (smaller than data length that is specified to wLength by host), device side and stage management cannot be synchronized.
Page 407 3.16.3.24 EPx_MODE Register (x: 1 to 3) This register sets transfer mode of endpoint (EP1 to EP3). If transaction of SET_CONFIG and SET_INTERFACE are set to software control, this control must use appointed config or interface. When it is setting mode, access this register.
Page 408 3.16.3.25 EPx_SINGLE Register This register sets mode of FIFO in each endpoint (SINGLE/DUAL). EPx_SINGLE1 bit Symbol EP3_SELECT EP2_SELECT EP1_SELECT (07D1H) Read/Write After reset Note: Endpoint 3 support only SINGLE mode at TMP92CZ26A. Bit number 0: No use 1: EP1_SINGLE 2: EP2_SINGLE 3: EP3_SINGLE 4: No use 5: EP1_SELECT...
Page 409 3.16.3.27 USBREADY Register This register informs finishing writing data to descriptor RAM on UDC. After assigned data to descriptor RAM, write “0” to bit0. bit Symbol USBREADY (07E6H) Read/Write After reset USBREADY (Bit0) 0: Writing to descriptor RAM was finished. 1: Writing to descriptor RAM is enable.
Page 410 3.16.3.28 Set Descriptor STALL Register This register sets whether returns STALL automatically in data stage or status stage for Set Descriptor Request. Set Descriptor STALL bit Symbol (07E8H) Read/Write After reset Bit0: S_D_STALL 0: Software control (Default) 1: Automatically STALL 3.16.3.29 Descriptor RAM Register This register is used for store descriptor to RAM.
Page 411 3.16.4 Descriptor RAM This area stores descriptor that is defined in USB. Device, Config, Interface, Endpoint and String descriptor must set to RAM by using following format. Device descriptor Config 1 descriptor (Interfaces, endpoints) Config 2 descriptor (Interfaces, ENDPOINT) String0 length String1 length String2 length String3 length...
Page 412 527H bmAttributes 528H wMaxPacketSize (L) 529H wMaxPacketSize (H) 52AH bInterval Description Device Descriptor USB Spec 1.00 IFC’s specify own Toshiba Release 1.00 Config Descriptor 78 bytes Bus powered-remote wakeup 98 mA Interface Descriptor AlternateSetting0 Endpoint Descriptor BULK 64 bytes 92CZ26A-409...
Page 413 Address Data Description Interface0 Descriptor AlternateSetting1 52BH bLength 52CH bDescriptorType 52DH bInterfaceNumber 52EH bAlternateSetting 52FH bNumEndpoints 530H bInterfaceClass 531H bInterfaceSubClass 532H bInterfaceProtocol 533H iInterface Endoint1 Descriptor 534H bLength 535H bDescriptorType 536H bEndpointAddress 537H bmAttributes 538H wMaxPacketSize (L) 539H wMaxPacketSize (H) 53AH bInterval Endpoint2 Descriptor...
Page 414 577H bString String Descriptor2 String Descriptor3 92CZ26A-411 TMP92CZ26A Description Endpoint Descriptor Interrupt 8 bytes 1 ms Length of String Descriptor0 Length of String Descriptor1 Length of String Descriptor2 Length of String Descriptor3 String Descriptor Language ID 0x0409 String Descriptor (Toshiba)
Page 415 3.16.5 Device Request 3.16.5.1 Standard request UDC support automatically answer in standard request. 1) GET_STATUS Request This request returns status that is appointed of receive side, automatically. bmRequestType bRequest 10000000B GET_STATUS 10000001B 10000010B Request to device returns following information according to priority of little endian.
Page 416 (2) CLEAR_FEATURE request This request clears or disables particular function. bmRequestType bRequest 00000000B CLEAR_ FEATURE 00000001B 00000010B • Reception side device Feature selector: 1 Feature selector: except 1 • Reception side interface STALL state • Reception side end point Feature selector: 0 Feature selector: except 0 STALL state Note: If it request to endpoint that is not exist, it stall.
Page 417 (4) SET_ADDRESS request This request set device address. Following request answer by using this device address. Answer of request is used present device address until status stage of this request finish normally. bmRequestType bRequest 00000000B SET_ADDRESS Device Address (5) GET_DESCRIPTOR request This request returns appointed descriptor.
Page 418 (6) SET_DESCRIPTOR request This request sets or enables particular function. bmRequestType bRequest 00000000B SET_ Descriptor Descriptor index Automatically answer of this request does not support. According to INT_SETUP interrupt, if receiving request was discerned as SET_DESCRIPTOR request, take back data after it confirmed EP0_DSET_A bit of DATASET register is “1”.
Page 419 (9) GET_INTERFACE request This request returns AlternateSetting value that is set by appointed interface. bmRequestType bRequest 10000001B GET_ INTERFACE If there is not appointed interface, it become to STALL state. (10) SET_INTERFACE request This request selects AlternateSetting in appointed interface. bmRequestType bRequest 00000001B...
Page 420 3.16.5.2 Printer Class Request UDC does not support “Automatic answer” of printer class request. Transaction for Class request is the same as vendor request; answering to INT_SETUP interrupt. 3.16.5.3 Vendor request (Class request) UDC doesn’t support “Automatic answer” of Vendor request. According to INT_SETUP interrupt, access register that device request is stored, and discern receiving request.
Page 421 (b) Control write/request There is no dataphase bmRequestType bRequest 010000xxB Vendor peculiar When INT_SETUP is received, judge contents of receiving request by bmRequestType, bRequest, wValue, wIndex, wLength registers. And execute transaction for each request. As application, access Setup_Received register after request was judged. And it must inform that INT_SETUP interrupt was recognized to UDC.
Page 422 Below is control flow in UDC watch from application. Start up Setting each EP mode in Set_Config (Interface) Enumeration Control RD transfer Get_Vendor_Request transaction EP0 bit = 1 EP0 bit = 0 Transmit Check judgement DATASET Total_Length register Total ≥ payload Total <...
Page 423 3.16.6 Transfer mode and Protocol Transaction UDC perform automatically in hardware as follows; • Receive packet • Judge address endpoint transfer mode • Error process • Confirm toggle bit CRC of data receiving packet • Generate including toggle bit CRC of data transmitting packet •...
Page 424 (2) Transfer mode UDC support transfer mode in FULL speed. • FULL speed device Control transfer type Interrupt transfer type Bulk transfer type Isochronous transfer type Following is explanation of UDC operation in each transfer mode. Explanation of data flow is explanation until FIFO. (a) Bulk transfer type Bulk transfer type warrants transferring no error between host and function by using detect error and retry.
Page 425 (a-1) Transmission bulk mode Below is transaction format of bulk transfer during transmitting. • Token: IN • Data: DATA0/DATA1, NAK, STALL • Handshake: ACK Control flow Below is control-flow when UDC receive IN token. Token packet is received and address endpoint number error is confirmed, and it checks whether conform applicable endpoint transfer mode with IN token.
Page 426 IDLE Receive IN token ConfirmToken packet • PID • Address • Endpoint • Transfer mode • Error Confirm Handshake answer • Confirm STATUS register (Status) • Confirm DATASET register Generate DATA PID • Attach DATA0/DATA1 • Confirm Datasize register Transmit data Attach CRC Wait ACK to host...
Page 427 (a-2) Receiving bulk mode Below is transaction format receiving bulk transfer type. It has to follow below. • Token: OUT • Data: DATA0/DATA1 • Handshake: ACK, NAK, STALL Control flow Below is control-flow when UDC receive IN token. Token packet is received and address endpoint number error is confirmed, and it checks whether conform applicable endpoint transfer mode with OUT token.
Page 428 IDLE Receive OUT token Confirm Token packet • PID • Address • Endpoint • Transfer mode • Error Confirm Status • Confirm STATUS register (status) • Confirm FIFO’s condition Generate DATA PID • DATA0/DATA1 • Time out • Toggle check Toggle error •...
Page 429 (b) Interrupt transfer type Interrupt transfer type use transaction format same with transmission bulk transfer. When transmission by using toggle bit, hardware setting and answer in UDC are same with transmission bulk transfer. Interrupt transfer can be transferred without using toggle bit. In this case, if ACK handshake from host is not received, toggle bit is renewed, and finish normally.
Page 430 (c) Control transfer type Control transfer type is configured in below three stages. • Setup stage • Data stage • Status stage Data stage is skipped sometimes. Each stage is configured in one or plural transaction. UDC executes each transaction while managing of three stages in hardware.
Page 431 Data packet is received. Device request of 8 bytes from SIE in UDC is transferred to below request register. • bmRequestType register • bmRequest register • wValue register • wIndex register • wLength register After last data was transferred, and compare counted CRC with transferred CRC.
Page 432 IDLE Receive SETUP token Confirm Token packet • PID • Address • Endpoint • Transfer mode • Error Confirm Status • Confirmation STATUS register (Status) Confirm DATA PID • DATA0 • Time out Receive data • Error • Confirm receving data number Transmit ACK Normal finish transaction...
Page 433 (c-2) Data stage Data stage is configured by one or plural transaction base on toggle sequence. Transaction is same with format transmission or receiving bulk transaction. However, below is difference. • Toggle bit start from “1” by SETUP stage. • It judges whether right or not by comparing IN and OUT token with direction bit of device request.
Page 434 If ACK handshake from host is received, • Set STATU to READY. • Assert INT_STATUS interrupt. It finishes normally by above transaction. If it is time out without receiving ACK from host, • Set STATUS register to TX_ERR and state return IDLE. And wait restring status stage.
Page 435 (c-4) Stage management UDC manages each stage of control transfer by hardware. Each stage is changed by receiving token from USB host, or CPU accesses register. Each stage in control transfer type has to process combination software. UDC detect following contents from 8-byte data in SETUP stage. (It contents is showed to following.) And, stage is managed by judging control transfer type.
Page 436 Stage change condition of control read transfer type Receive SETUP token from host • • • Receive IN token from host • • • • • • • Receive OUT token from host. • • These changing conditions are shown in Figure 3.16.10. SETUP DATA0 ACK INT_SETUP INT_ ENDPOINT0...
Page 437 Stage change condition of control write transfer type Receive SETUP token from host. • • • Receive OUT token from host. • • • • • • • Receive IN token from host. • • These changing conditions are shown in Figure 3.16.11. SETUP DATA0 ACK DATA1 INT_SETUP...
Page 438 Stage change condition of control write (no data stage) transfer type Receive SETUP token from host • • • Receive IN token from host • • • • • • • These change condition is Figure 3.16.12. SETUP DATA0 ACK INT_SETUP INT_ ENDPOINT0 INT_STATUS...
Page 439 (d) Isochronous transfer type Isochronous transfer type is guaranteed transfer by data number that is limited every each frame. However, this transfer don’t retry when error occurs. Therefore, Isochronous transfer type transfer only 2 phases (token, data) and it doesn’t use handshake phase.
Page 440 Below is transaction when SOF token from host is received. • Change the packet A’s FIFO from X Condition to Y Condition. And clear data. • Change the packet B from Y Condition to X Condition. • Set frame number to frame register. •...
Page 441 IDLE Receive IN token Confirm Token packet • PID • Address • Endpoint • Transfer mode • Error Confirm Status • Confirm STATUS register (status) Generate DATA PID • Attach DATA0 • Confirm DATASIZE register Receive SOF without transmitting data Transmit data Set LOST to FRAME register Error transaction...
Page 442 (d-2) Isochronous receiving mode Isochronous transfer type format in receiving is below transaction format. • Token: OUT • Data: DATA0 Control flow Isochronous transfer type is frame management. And data that is written to FIFO by OUT token is received to CPU in next frame. Below are two conditions in FIFO of Isochronous receiving mode transferring X.
Page 443 In renewed frame, Packet A’s FIFO interchange packet B’s FIFO, and transaction is used same flow. If SOF token is not received by error and so on, this data is lost because of frame is not renewed. Nothing problem in receiving PID and if frame data is received with CRC error, USB sets LOST to STATUS on FRAME register, and frame number is not renewed.
Page 444 IDLE Receive OUT token Confirm Token packet • PID • Address • Endpoint • Transfer mode • Error Confirm Status Confirming STATUS register (status) Confirm DATA PID • Time out • Error Receive SOF nothing transmitting data Receiving data • Error •...
Page 445 3.16.7 Bus Interface and Access to FIFO (1) CPU bus interface UDC prepares two types of FIFO access, single packet and dual packet. In single packet mode, FIFO capacity that is implemented by hardware is used as big FIFO. In dual packet mode, FIFO capacity that is divided into two is used as two FIFOs.
Page 446 (a) Single packet mode This is data sequence of single packet mode when CPU bus interface is used. Figure 3.16.15 is receiving sequence. Figure 3.16.16 is transmitting sequence. Main of this chapter is access to FIFO. Data sequence with USB host refer to chapter 5.
Page 447 Below is transmitting sequence in single packet mode. Wait transmission event DATASET = 0 DATASET = 1 Wait transmitting rest data Transmitting number > payload • WR of payload to applicable endpoint • Total = Total − payload If transmitting number reach to payload, applicable bit of DATASET register is set 1 If transmitting finish normally,...
Page 448 (b) Dual packet mode In dual packet mode, FIFO is divided into A and B packet, it is controlled according to priority in hardware. It can be performed at once, transmitting and receiving data to USB host and exchanges to external of UDC. When it reads out data from FIFO for receiving, confirm condition of two packets, and consider the order of priority.
Page 449 When it writes data to FIFO in transmitting, confirm condition of two packets, and consider the order of priority. When transfer data number is set, set to which packet A and packet B, judge by PACKET_ACTIVE bit. Packet that bit is set to 0 is bit that transfer now.
Page 450 (c) Issuance of NULL packet If transmitting NULL packet, by input L pulse from EPx_EOPB signal, data of 0 length is set to FIFO, and it can be transferred NULL packet to IN token. But if it set NULL data to FIFO, it is valid only case of SET signal is L level condition (case of FIFO is empty).
Page 451 3.16.8 USB Device answer USB controller (UDC) sets various register and initialization in UDC in detecting of hardware reset, detecting of USB bus reset, and enumeration answer. Below is explaining about each condition. (1) Condition in detect in bus reset. When UDC detects bus reset on USB signal line, it initializes internal register, and it prepares enumeration operation from USB host.
Page 452 ISO transfer mode Below is transfer condition of frame before one. Receiving SOF renews this. Initial Not transfer Finish normally Detect in error Transfer mode of except ISO transfer This is result previous transfer. When transfer finish, this is renewed. Initial Transfer finish normally Status stage finish...
Page 453 3.16.9 Power Management USB controller (UDC) can be switched from optional resume condition (turn on the power supply condition) to suspend (Suspension) condition, and it can be returned from suspends condition to turn on the power supply condition. This function can be set to low electricity consumption by operating CLK supplying for UDC.
Page 454 (4) Low power consumption by control of CLK input signal When UDC switches to suspend condition, it stops CLK and switches to low power consumption condition. But as system, this function enables besides low power consumption by stopping source of CLK that is supplied from external. CLK that supply USBINTFR1<INT_SUS>...
Page 455 3.16.10 Supplement (1) External access flow to USB communication Normally movement SETUP DATA0 ACK INT_SETUP INT_ ENDPOINT0 INT_STATUS REQUEST FLAG EP0 FIFO access Request access Setup Received access EOP register access Stage error SETUP DATA0 ACK INT_SETUP INT_ ENDPOINT0 INT_STATUS REQUEST FLAG EP0 FIFO access Request access...
Page 456 (2) Register beginning value Beginning Value Register Name OUTSIDE Reset bmRequestType 0x00 bRequest 0x00 wValue_L 0x00 wValue_H 0x00 wIndex_L 0x00 wIndex_H 0x00 wLength_L 0x00 wLength_H 0x00 Current_Config 0x00 Standard request 0x00 Request 0x00 DATASET 0x00 Port Status 0x18 Standard request mode 0x00 Request mode 0x00...
Page 457 TMP92CZ26A (3) USB control flow chart (a) Transaction for standard request (Outline flowchart (Example)) USB interrupt Call USBINT0 function Judge Interrupt SETUP ENDPOINT 0 STATUS STATUS NAK ENDPOINT 1 transaction transaction transaction transaction transaction 92CZ26A-454...
Page 458 (b) Condition change Turn on power supply Initialization transaction Normal finish/No transaction Waiting USB interrupt condition Transmit Request error/ Transaction error/ Transmit STALL Request transaction condition 92CZ26A-455 Receive USB token TMP92CZ26A...
Page 459 TMP92CZ26A (c) Device request and various request judgment Start Get request data Judge Request Standard request Class request Vendor request Error transaction * Error for not CLEAR_FEATURE * Error for not support support SET_FEATURE GET_STATUS SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION SET_INTERFACE GET_INTERFACE SYNCH_FRAME GET_DESCRIPTOR 92CZ26A-456...
Page 460 (c-1) CLEAR_FEATURE request transaction Start Is request right？ Judge Recipient Device Disable remote wakeup setting Finish transaction 92CZ26A-457 Endpoint Error transaction Clear stall setting TMP92CZ26A...
Page 461 (c-2) SET_FEATURE request transaction Start Is request right? Judge Recipient Device Enable remote wakeup setting Finish transaction 92CZ26A-458 TMP92CZ26A Endpoint Error transaction Set stall...
Page 462 (c-3) GET_STATUS request transaction Is request right? Judge Recipient Device Interface Set self power Set 0 x 0 0 data of supply information 2 bytes Finish transaction 92CZ26A-459 Start Endpoint Set stall information TMP92CZ26A Error transaction...
Page 463 (c-4) SET_CONFIGRATION request transaction Start Is request right？ Is EP0 stall？ Is assignment value valid？ Is state valid？ Set assignment configuration value Clear stall flag Finish transaction 92CZ26A-460 TMP92CZ26A Error transaction...
Page 464 (c-5) GET_CONFIGRATION request transaction Start Is request right? Is state valid? Set present configuraion value Finish transaction 92CZ26A-461 TMP92CZ26A Error transaction...
Page 465 (c-6) SET_INTERFACE request transaction Start Is request right? Is EP0 stall? Is assignment value valid? Is state valid? Set each endpoint to assignmented configuration value. Finish transaction 92CZ26A-462 TMP92CZ26A Error transaction...
Page 466 (c-7) SYNCH_FRAME request transaction Start Is request right? Is EP0 stall? Is assignment value valid? Is state valid? Set altrenate setting value to present transmitting data. Finish transaction 92CZ26A-463 Error transaction TMP92CZ26A...
Page 467 (c-8) SYNCH_FRAME request transaction Start Is request right? Finish transaction (c-9) SET_DESCRIPTOR request transaction Start Is request right? Finish transaction 92CZ26A-464 TMP92CZ26A Error transaction Error transaction...
Page 468 (c-10) GET_DESCRIPTOR request transaction Start Is request right? Is EP0 stall? Is assignment value valid? Is state valid? Config Device Set device Set config descriptor descriptor information. information. Write information to FIFO[EP0_fifowrite ( )] 92CZ26A-465 TMP92CZ26A String Error transaction Set string descriptor information.
Page 469 TMP92CZ26A (c-11) Data read transaction to FIFO by EP0 Start Is request right? Stage information = data stage Read data from FIFO STATUS_NAK interrupt disable STATUS_NAK interrupt enable Stage information = stataus stage Data read from FIFO All data number Finish transaction renew transfer address 92CZ26A-466...
Page 470 TMP92CZ26A (c-12) Data write transaction to FIFO by EP0 Start Is request right? Set transmitting size to SIZE register Stage information = data stage Write data to FIFO STATUS_NAK interrupt enable Is data number decided time of payload size? Set data size to SIZE register STATUS_ NAK interrupt disable Write data to FIFO Stage information = status stage...
Page 471 TMP92CZ26A (c-13) Beginning setting transaction of microcontroller Start Interrupt disable Set Stack point Set Various interrupt Clear vRAM UDC initialization[UDC_INIT] USB farm initialization[USB_INIT] Interrupt enable Main transaction[main ( )] (c-14) Begining setting transaction of UDC Start USBC reset transaction 92CZ26A-468...
Page 472 (c-15) Beginning transaction of USB farm changing number Start Renew stage information Renew current information Renew support information Invalid EP except EP0 Various flag Intialization (c-16) Set DEVICE_ID data to DEVICE_ID of UDC Start Set DEVICE_ID data to DEVICE_ID_RAM area. 92CZ26A-469 TMP92CZ26A...
Page 473 (c-17) Descriptor data set transaction (c-18) USB interrupt transaction Setup interrupt Endpoint 0 interrupt transaction [Proc_ ENDPOINT] [Proc_SETUPINT] Start Set descriptor data to DESC_RAM area. Start Read INT register Judge Interrupt Status_NAK interrupt Status_interrupt [Proc_STATUSNAKINT] [Proc_STATUSINT] Judge Request transaction [STATUS_judge] 92CZ26A-470 TMP92CZ26A Others...
Page 474 (c-19) Dummy function for not using maskable interrupts. • Transaction performs nothing, therefore outline flow is skipping. (c-20) Request judgment transaction. If transaction result is error, it puts STALL command. Start Is request right? (c-21) SETUP stage transaction Start Is request right? Stage information = SETUP stage Request transaction 92CZ26A-471...
Page 475 (c-22) Perform endpoint 0 transaction in except for SETUP stage. Start Judge Stage Data stage GET system request [EP0_fifowrite] SET system request [EP0_fiforead] (c-23) Status stage interrupt transaction Start Status stage? Normal finish transaction 92CZ26A-472 Status stage Others Finish normally Error transaction Error transaction TMP92CZ26A...
Page 476 TMP92CZ26A (c-24) STATUS_NAK interrupt transaction Start Data stage? Normal finish Error transaction transaction (c-25) This transaction is no transaction by USB transaction perform in interrupts. Start 92CZ26A-473...
Page 477 (c-26) Getting descriptor information (reration of standard request) Start Get device information on descriptor Is config within support? Get config information on descriptor Interface is within support in config present. Get device information on descriptor Increment count to next config information 92CZ26A-474 TMP92CZ26A...
Page 478 3.16.11 Points to Note and Restrictions Limitation of writing to COMMAND register in special timing When “STALL” command is issued, ENDPOINT status might be shift to “INVALID”. To avoid this problem, keep the below routine. BULK (IN/OUT) In case issue STALL command to endpoint in BULK transfer, be sure to issue STALL command after stop RD/WR accessing to endpoint;...
Page 479 When generating toggle error of device controller UDC operation If USB host fail to receive ACK transmitted from UDC in OUT transfer, USB host transmits the same data to UDC again. When the FIFO is available to receive, UDC detects toggle error because of detecting the same data(having the same toggle as the data which is received just before) and returns ACK.
Page 480 3.17 SPIC (SPI Controller) SPIC is a Serial Peripheral Interface Controller that supports only master mode. It can be connected to SD card, MMC (Multi Media Card) etc. in SPI mode. The features are as follows; 1) 32 byte –FIFO (Transmit / Receive) 2) Generate CRC7 and CRC16 (Transmit / Receive data) 3) Baud Rate: 20Mbps max 4) Connect several SD cards and MMC.
Page 481 3.17.1 Block diagram It shows block diagram and connection to SD card in Figure 3.17.1. SPIC (SPI Controller) Baud rate Generator 16bit 16bit 16bit 16bit 16bit 16bit INTSPI Note1: SPCLK, SPCS , SPDO and SPDI pins are set to input port (Port PR3, PR2, PR1, PR0) by reset. These signals are needed pull-up resister to fix voltage level, could you adjust resistance value for your final set.
Page 482 3.17.2 SFR SFR of SPIC are as follows.These area connected to CPU with 16 bit data bus. (1) SPIMD(SPI Mode setting register) SPIMD register is for operation mode or clock etc. bit Symbol SWRST SPIMD Read/Write (820H) After Reset Software SYSCK Prohibit to Reset...
Page 483 (c) <DOSTAT> Set the status of SPDO pin when data communication is not operating (after transmitting or during receiving). Please don't change the setting of this register when transmitting/receiving is in operation. (d) <TCPOL> Select the edge of synchronous clock. Please change the setting when <XEN>bit is “0”.
Page 484 (h) <SWRST> This bit is for Software reset of transmit/receive FIFO pointer. Write SPICT<TXE> to “0” at <XEN>="1", and stop transmitting. After that, by writing <SWRST> to “1”, the read/write pointer of transmit/receive FIFO are initialized. When writing SPICT<TXE> to “0”, stops transmission after the UNIT data in transmitting is transmitted.
Page 485 (2) SPICT(SPI Control Register) SPICT register is for data length or CRC etc. SPICT bit Symbol SPCS_B (822H) Read/Write After Reset /SPCS pin communication control 0: output “0” 0: disable 1: output “1” Function 1: enable bit Symbol CRC16_7_B CRCRX_TX_B CRCRESET_B (823H) Read/Write After Reset...
Page 486 The process that calculating CRC16 of transmits data and sending CRC next to transmit data is explained as follows. (1) Set SPICT <CRC16_7_B> to select CRC7 or CRC16 and <CRCRX_TX_B> to select calculating data. (2) To reset SPICR register, write “1” after write<CRCRESET_B> to "0". (3) Write transmit data to SPITD register, and wait for finish transmission all data.
Page 487 (d) <CEN> Select enable/disable of the pin for SD card or MMC. When the card isn’t inserted or no-power supply to DVcc, penetrated current is flowed because SPDI pin becomes floating. In addition, current is flowed to the card because SPCS , SPCLK and SPDO pin output “1”. This register can avoid these matters. If write <CEN>...
Page 488 (k) <RXE> In UNIT receive mode, receives only 1 UNIT data by writing “1”. When reading receive data register (SPIRD) with the condition “1”, receives one time additionally. In sequential mode, receiving is kept sequentially until FIFO becomes full by writing “1”.
Page 489 Difference points between UNIT transmission and Sequential transmission UNIT transmit mode can be selected by writing SPICT<TXMOD>= “0”. The transmit FIFO is invalid in UNIT transmit mode. The UNIT transmit starts when writing UNIT data with the condition SPICT<TXE>= “1” or writing SPICT<TXE>= “1” after writing 1UNIT data in the transmit buffer.
Page 490 Difference points between UNIT receive and Sequential receive UNIT receive is the mode that receiving only 1 UNIT data. UNIT receive mode can be selected by writing SPICT<RXMOD>= “0”. The receive FIFO is invalid in the UNIT receive mode. By writing SPICT<RXE>= “1”, receives 1UNIT data, loads received data in receive data register (SPIRD) and then stop receiving.
Page 491 Transmit/Receive When transmitting or receiving, write <FDPXE>= “1” Writing <FDPXE>= “1” first, and SPICT<RXE>= “1” and keep waiting state for starting UNIT receiving. When writing SPICT<RXE>= “1”after <ALGNEN>= “1”, receiving does not start right away. This is because the data to transmit at the same time has not been prepared. Transmit/receive start when writing the data to (SPITD) register with the condition <TXE>= “1”.
Page 492 (3) Interrupt In INTC (interrupt controller), interrupt is divided roughly into 2 kinds; transmit interrupt (INTSPITX) and receive interrupt (INTSPIRX). Besides in this SPI circuit, there are 4 kinds of interrupts; 2 transmit interrupts 2 receive interrupts. ・ Transmit interrupt TEMP (Empty interrupt of transmit FIFO) and TEND (End interrupt of transmit).
Page 493 (3-1) SPIST (SPI Status Register) SPIST shows 4 statuses. SPIST bit Symbol (824H) Read/Write After reset Function bit Symbol (825H) Read/Write After reset Function (a) <TEMP> For UNIT transmission, it is cleared to “0” when valid data exists in transmit register (SPITD).
Page 494 (3-2) SPIIE(SPI Interrupt Enable Register) SPIIE register is for enable 4 interrupts. SPIIE bit Symbol (82CH) Read/Write After Reset Function bit Symbol (82DH) Read/Write After Reset Function (a) <TEMPIE> Set enable/disable of TEMP interrupt. (b)<RFULIE> Set enable/disable of RFUL interrupt. (c)<TENDIE>...
Page 495 (4) SPICR (SPI CRC Register) CRC result of Transmit/Receive data is set to SPICR register. SPICR bit Symbol CRCD7 CRCD6 (826H) Read/Write After Reset Function bit Symbol CRCD15 CRCD14 (827H) Read/Write After Reset Function (a) <CRCD15:0> The result which is calculated according to the setting; SPICT<CRC16_7_b>, <CRCRX_TX_B>...
Page 496 (5) SPITD (SPI Transmit Data Register) SPITD0, SPITD1 registers are for writing transmitted data. bit Symbol TXD7 TXD6 SPITD0 (830H) Read/Write After reset Function bit Symbol TXD15 TXD14 (831H) Read/Write After reset Function bit Symbol TXD7 TXD6 SPITD1 (832H) Read/Write After reset Function bit Symbol...
Page 497 (6) SPIRD (SPI Receive Data Register) SPIRD0, SPIRD1 registers are for reading received data. SPIRD0 bit Symbol RXD7 (834H) Read/Write After reset Function bit Symbol RXD15 RXD14 (835H) Read/Write After reset Function SPIRD1 bit Symbol RXD7 (836H) Read/Write After reset Function bit Symbol RXD15...
Page 498 • Note of FIFO buffer There are following notes in this SPIC. 1) Transmit ・ Data is overwritten if write data with condition transmit FIFO buffer is FULL. Interrupt and transmission are not executed normally because write-pointer in FIFO becomes abnormal condition. Therefore, manage number of writing by using software. ・...
Page 499 3.18 I S (Inter-IC Sound) The TMP92CZ26A incorporates serial output circuitry that is compliant with the I This function enables the TMP92CZ26A to be used for digital audio systems by connecting an LSI for audio output such as a DA converter. The I S unit has the following features: Item...
Page 500 3.18.1 Block Diagram The I S unit contains two channels: channel 0 and channel 1. Each channel can be controlled and made to output independently. Figure 3.18.1 shows a block diagram for I I2S0CTL <CLKS0> 8-bit Counter I2S0C <CK07:00> Clock Generator 32bit 64-byte FIFO0 (2 bytes×32)
Page 501 3.18.2 SFRs The I S unit is provided with the following registers. These registers are connected to the CPU via a 32-bit data bus. The transmission buffers I2S0BUF and I2S1BUF must be accessed using 4-byte load instructions. I2S0CTL bit Symbol TXE0 (1808H) Read/Write...
Page 502 bit Symbol I2S1CTL TXE1 (1818H) Read/Write After reset Transmission Function 0: Stop 1: Start bit Symbol CLKS1 Read/Write (1819H) After reset Source clock Function 0: f 1: f bit Symbol CK17 I2S1C (181AH) Read/Write After reset Function (181BH) Bit symbol Read/Write After reset Function...
Page 503 3.18.3 Description of Operation (1) Settings the transfer clock generator and Word Select signal In the I S unit, the clock frequencies for the I2SnCKO and I2SnWS signals are generated using the system clock (f by a prescaler and a dedicated clock generator to set the transfer clock and sampling frequency.
Page 504 I2SnWS I2SnCKO I2S format I2SnDO Stereo Valid data Monaural Valid Data Left justify I2SnDO Stereo Valid Data Monaural Valid Data Right justify I2SnDO Stereo Monaural Right Data Valid Data Valid Data Figure 3.18.4 Output Format 92CZ26A-501 TMP92CZ26A Left Data Valid Data Valid Data Valid Data...
Page 505 (2) Setting example for the clock generator (8-bit counter/6-bit counter) The clock generator generates the reference clock for setting the data transfer speed and sampling frequency. bit Symbol CK07 I2S0C Read/Write (180AH) After reset Function Bit symbol (180BH) Read/Write After reset Function •...
Page 506 Note 1: The value to be set in I2SnC<WSn5:0> must be 16 or larger (18 or larger for I2S transfer) when the data length is 8 bits and 32 or larger (34 or larger for I2S transfer) when the data length is 16 bits. Note 2: It is recommended that the value to be set in I2SnC<WSn5:0>...
Page 507 The following shows how written data is output under various conditions. When I2SnCTL<WLVLn> = 0 I2SnBUF register Output order MSB-first 16 bits 2’nd Data LSB-first 16 bits MSB-first 8 bits 4’th Data LSB-first 8 bits MSB-first 16 bits 1’st Data LSB-first 16 bits MSB-first 8 bits 2’nd Data...
Page 508 3.18.4 Detailed Description of Operation (1) Connection example Figure 3.18.5 shows an example of connections between the TMP92CZ26A and an external LSI (DA converter) using channel 0. TMP92CZ26A (Transmit) PF2/I2S0WS PF0/I2SCKO PF1/I2SDO Note: After reset, PF0 to PF2 are placed in a high-impedance state. Connect each pin with a pull-up or pull-down resistor as necessary.
Page 509 FIFO write <TXE> I2SnWS pin I2SnCKO pin I2SnDO pin INTI2Sn I2SnWS pin 400kHz I2SnCKO pin I2SnDO pin Bit15 Bit14 Figure 3.18.6 Timing Diagrams (I2S FMT/Stereo/16bit/MSB first) (3) Considerations for using the I 1) INTI2Sn generation timing Every 4bytes data trance from FIFO buffer to shift register per one time. An INTI2Sn interrupt is generated under two conditions.
Page 510 immediately. At the same time, the read and write pointers of the FIFO, the data in the output shift register and the clock generator are all cleared. (However, when I2SnCTL<CNTEn>=1, the clock generator is not cleared. To clear the clock generator, I2SnCTL<CNTEn>...
Page 511 3.19 LCD Controller (LCDC) The TMP92CZ26A incorporates an LCD controller (LCDC) for controlling an LCD driver LSI (LCD module). This LCDC supports display sizes from 64 × 64 to 640 × 480 dots for monochrome, grayscale, and 4096-color display and from 64 × 64 to 320 × 320 dots for color display using 65536 or more colors.
Page 512 3.19.1 LCDC Features according to LCD Driver Type Table 3.19.1 LCDC Features according to LCD Driver Type (This table assumes the connection with a TOSHIBA-made LCD driver.) LCD Driver Display colors 256/4096/65536/262144/16777216 colors For 65536 colors or less Rows (Commons):...
Page 513 3.19.2 SFRs bit Symbol RAMTYPE1 LCDMODE0 Read/Write (0280H) After reset Display RAM 00: Internal RAM 01: External SRAM 10: SDRAM Function 11: Reserved Note: When SDRAM is used as the LCDC’s display RAM, it can only be accessed by “burst 1-clock access”. bit Symbol LDC2 LCDMODE1...
Page 514 bit Symbol PIPE LCDCTL0 (0285H) Read/Write After reset function 0:Disable 1:Enable Function Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of <LCP0OC> bit. bit Symbol LCP0P LCDCTL1 Read/Write (0286H) After reset LCP0 phase Function 0: Rising...
Page 515 bit Symbol LCDHSP (028AH) Read/Write After reset Function bit Symbol LH15 (028BH) Read/Write After reset Function bit Symbol LVP7 LCDVSP Read/Write (028CH) After reset Function bit Symbol (028DH) Read/Write After reset Function bit Symbol LCDPRVSP Read/Write (028EH) After reset Function LCD LHSYNC Pulse Register LHSYNC period (bits 7–0) LH14...
Page 516 bit Symbol LCDHSDLY (028FH) Read/Write After reset Function bit Symbol LCDLDDLY (0290H) Read/Write After reset Data output timing 0: Sync with Function LLOAD 1: 1 clock later than LLOAD bit Symbol LCDO0DLY (0291H) Read/Write After reset Function bit Symbol LCDO1DLY (0292H) Read/Write After reset...
Page 517 bit Symbol HSW7 LCDHSW (0294H) Read/Write After reset Function bit Symbol LDW7 LCDLDW (0295H) Read/Write After reset Function bit Symbol O0W7 LCDHO0W (0296H) Read/Write After reset Function bit Symbol O1W7 LCDHO1W (0297H) Read/Write After reset Function bit Symbol O2W7 LCDHO2W Read/Write (0298H) After reset...
Page 518 bit Symbol LMSA7 LSAML (02A0H) Read/Write After reset Function bit Symbol LMSA15 LSAMM (02A1H) Read/Write After reset Function bit Symbol LMSA23 LSAMH Read/Write (02A2H) After reset Function Note: When assigned internal RAM as VRAM, A1 signal cannot be used. Every 4bytes setting is needed. LSSA7 bit Symbol LSASL...
Page 519 bit Symbol SAHX7 LSAHX (02A8H) Read/Write After reset Function bit Symbol (02A9H) Read/Write After reset Function bit Symbol SAHY7 LSAHY (02AAH) Read/Write After reset Function bit Symbol (02ABH) Read/Write After reset Function bit Symbol SAS7 LSASS (02ACH) Read/Write After reset Function bit Symbol (02ADH)
Page 520 3.19.3 Description of Operation 3.19.3.1 Outline After the required settings such as the operation mode, display data memory address, color mode, and LCD size are specified, the start register is set to start the LCDC operation. The LCDC issues a bus request to the CPU. When the bus is granted, the LCDC reads data of the display size from the display RAM, stores the data in the FIFO buffer in the LCDC, and then returns the bus to the CPU.
Page 521 3.19.3.3 Basic Operation The following diagram shows the basic timings of the waveforms generated by the LCDC and adjustable elements. The adjustable elements for each signal include enable time, phase, and delay time. The signals used and their connections and settings vary with the LCD driver type (STN/TFT) and specifications to be used.
Page 522 3.19.3.4 Reference Clock LCP0 LCP0 is used as the reference clock for all the signals in the LCDC. This section explains how to set the frequency (period) of the LCP0 signal. The LCP0 clock speed (LD bus transfer speed) is determined by selecting TFT or STN and setting LCDMODE0<SCPW1:0>...
Page 523 LCP0 Setting Range Table Conditions Display size (color) Display size (monochrome/grayscale) : up to 640 × 480 Note: This table shows the range of LCP0 settings that can be made under the conditions shown above. If the CPU clock speed, display size, or refresh rate is changed, the LCP0 range also changes. Display RAM Internal RAM Display Mode...
Page 524 Example 1: When f = 10 MHz, STN mode, LCDMODE0<SCPW1:0> = 01 Internal reference clock LCP0 = f LCP0 period = 1 / 1.25 [MHz] = 0.8 [μS] Example 2: when f = 60 MHz, TFT mode, LCDMODE0<SCPW1:0> = 11 Internal reference clock LCP0 = f LCP0 period = 1 / 3.75 [MHz] = 266 [nS] bit Symbol...
Page 525 LCDCTL0 <LCP0OC> is used to control the output timing of the LCP0 signal. When <LCP0OC>=0, the LCP0 signal is always output. When <LCP0OC>=1, the LCP0 signal is output only when valid data is output. LCP0 signal LCP0OC=1 LCP0 signal LCP0OC=0 bit Symbol PIPE LCDCTL0...
Page 526 3.19.3.5 Refresh Rate The period of the horizontal synchronization signal LHSYNC is defined as the product of the value set in LCDHSP<LH15:0> and the LCP0 clock period. The value to be set in LCDHSP<LH15:0> is obtained as follows: Segment size + number of dummy clocks Monochrome/grayscale : (Segment size / 8) + number of dummy clocks Color LHSYNC [s: period] = LCP0 [s: period] ×...
Page 527 • Insertion of dummy clocks Reference LHSYNC (Delay=0) LVSYNC LHSYNC (with delay) LCP0 LD23-0 Horizontal Front Porch The above is a conceptual diagram showing the data (LD23-0), shift clock (LCP0), horizontal synchronization signal (LHSYNC), and vertical synchronization signal (LVSYNC) on the LCD panel. The front porch and back porch as shown above should be taken into consideration in setting LCDHSP<LH15:0>...
Page 528 • Setting method The front dummy LHSYNC (vertical front porch) not accompanied by valid data in the total of LHSYNC period in the LVSYNC period is defined by the value set in LCDPRVSP<PLV6:0>. Front dummy LHSYNC (vertical front porch) = <PLV6:0> The back dummy LHSYNC (vertical back porch) is defined as follows: (<LVP9:0>...
Page 529 3.19.3.6 Signal Settings Signal Name LCP0 signal LVSYNC signal LHSYNC signal LGOEn signal FR signal LLOAD signal LLOAD signal LCP0 signal LD23-LD0 signal LDINV signal The above diagram shows the typical timings of the signals controlled by the LCDC. This section explains how to control each of these signals. Valid LHSYNC Front dummy LHSYNC (Common size)
Page 530 1. LVSYNC Signal The period of the vertical synchronization signal LVSYNC indicates the time for each screen update (refresh rate). The LVSYNC period is defined as an integral multiple of the period of the horizontal synchronization signal LHSYNC. The LVSYNC period is calculated as the product of the value set in LCDVSP<LV 9:0> and the LHSYNC period.
Page 531 2. LHSYNC Signal The period of the horizontal synchronization signal LHSYNC corresponds to one line of display. The LHSYNC period is defined as an integral multiple of the reference clock signal LCP0. The LHSYNC period is defined as the product of the value set in LCDHSP<LH15:0 > and the LCP0 clock period.
Page 532 The enable width of the LHSYNC signal is set using LCDHSW<HSW8:0>. It can be specified in a range of 1 to 512 pulses of the LCP0 clock. The enable width is represented by the following equation: Enable width = <HSW8:0> + 1 Thus, when LCDHSW<HSW8:0>...
Page 533 As shown in the diagram below, delay time of 0 to 127 pulses of the LCP0 clock can be inserted in the LHSYNC signal. Delay time = <HSD6:0> Signal Name LCP0 signal LVSYNC signal Reference LHSYNC (with 0 delay) LHSYNC signal Delay control 1 bit Symbol LCDHSDLY...
Page 534 3. LLOAD Signal The LLOAD signal is used to control the timing for the LCD driver to receive display data. The period of the LLOAD signal synchronizes to one line of display. It is defined as an integral multiple of the reference clock LCP0. Front dummy LHSYNC (Vertical front porch) LVSYNC signal...
Page 535 The number of pulses in the front dummy LHSYNC (vertical front porch) is specified by LCDPRVSP<PLV6:0>. This delay time can be set in a range of 0 to 127 pulses of the LCP0 clock. Front dummy LHSYNC = <PLV6:0> LCDPRVSP bit Symbol (028EH) Read/Write...
Page 536 The enable width of the LLOAD signal is specified using LCDLDW<LDW9:0>. It can be set in a range of 0 to 1024 pulses of the LCP0 clock. The actual enable width is determined depending on the LCDLDDLY<PDT> setting, as shown below. Enable width = <LDW9:0>...
Page 537 As shown in the diagram below, delay time of 0 to 127 pulses of the LCP0 clock can be inserted in the LLOAD signal. Delay time = <LDD6:0> Signal Name LCP0 signal LLVSYNC signal LHSYNC signal (Internal reference signal) LLOAD signal Delay control Note: The delay time for the LLOAD signal is controlled based on LCDLDDLY<PDT>=1.
Page 538 4. LGOE0 to LGOE2 Signals The LCDC has three signals (LGOE0 to LGOE2) that can be controlled like the LHSYNC signal. For these signals, the enable width, delay time, and phase timing can be adjusted as shown below. Signal Name LCP0 LGOE0 signal LGOE1 signal...
Page 539 Signal Name LCP0 signal LVSYNC signal LHSYNC signal (Internal reference signal) LGOE0 signal Delay control LCDO0DLY bit Symbol (0291H) Read/Write After reset Function LCDO1DLY bit Symbol (0292H) Read/Write After reset Function LCDO2DLY bit Symbol (0293H) Read/Write After reset Function OE0D6 OE0D5 OE0D4 OE0D3...
Page 540 LGOEnP=0 LGOEnP=1 LCDCTL2 bit Symbol LGOE2P (0287H) Read/Write After reset LGOE2 LGOE1 phase phase Function 0: Rising 0: Rising 1: Falling 1: Falling LGOEn signal (Phase control) LCD Control 2 Register LGOE1P LGOE0P LGOE0 phase 0: Rising 1: Falling 92CZ26A-537 TMP92CZ26A...
Page 541 5. LFR Signal The LFR (frame) signal is used to control the direction of bias the LCD driver applies on liquid crystal cells. With small screens in monochrome mode, the polarity of the LFR signal is normally inverted in synchronization with each screen display. With large screens or when grayscale or color mode is used, the polarity is inverted at shorter intervals to adjust the display quality.
Page 542 When LCDCTL0<FRMON>=1 and LCDCTL0<DLS>=1, frame output is inverted at intervals set in LCDDVM0<FML3:0> and the LFR signal is inverted at intervals of “LCP0 × M”. The “M” value is specified in LCDDVM0<FMP7:4>. When <DLS>="1" LFR signal synchronous with front edge of LHSYNC signal. So, prohibit to set <FREDGE>=1, always need to set <FREDGE>=0.
Page 543 LCDCTL0 bit Symbol PIPE (0285H) Read/Write After reset Segment function 0:Disable 0: Normal 1:Enable 1: Always Function Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of <LCP0OC> bit. bit Symbol FMP3 LCDDVM0 Read/Write (0283H) After reset...
Page 544 6. LD Bus The data to be transferred to the LCD driver is output via a dedicated bus (LD23 to LD0). The output format can be selected according to the input method of the LCD driver to be used. The LCDC reads data of the size corresponding to the specified LCD size from the display RAM and transfers it to the external LCD driver via the data bus pin dedicated to the LCD.
Page 545 • Memory Map Image and Data Output in Each Display Mode STN monochrome (1-pixel display data = 1-bit memory data) Display Memory Address 0 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LD Bus Output 8-bit type 0 →...
Page 546 STN 16-grayscale (1-pixel display data = 4-bit memory data) Display Memory Address 0 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 LD Bus Output...
Page 547 STN 64-grayscale (1-pixel display data = 6-bit memory data) Display Memory Address 0 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Address 8...
Page 548 STN 256-color (1-pixel display data = 8-bit memory data (R: 3 bits, G: 3 bits, B: 2 bits)) Display Memory Address 0 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 LD Bus Output...
Page 549 STN 4096-color (12 bpp: R: 4 bits, G: 4 bits, B: 4 bits) Display Memory Address 0 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 LD Bus Output...
Page 550 TFT 256-color (1-pixel display data = 8-bit memory data (R: 3 bits, G: 3 bits, B: 2 bits) Display Memory Address 0 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 12bit (TFT)
Page 551 TFT 4096-color (1-pixel display data = 12-bit memory data (R: 4 bits, G: 4 bits, B: 4 bits) Display Memory Address 0 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 12-bit TFT...
Page 552 TFT 65536-color (16 bpp: R: 5 bits, G: 6 bits, B: 5 bits) Display Memory Address 0 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 16-bit TFT...
Page 553 TFT 262144-/16777216-color (24 bpp: R: 8 bits, G: 8 bits, B: 8 bits) Display Memory Address 0 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 24-bit TFT...
Page 554 7. LDIV Signal The <LDINV> and <AUTOINV> bits of the LCDMODE1 register are used to control the LDIV signal as well as data output. The LDIV signal indicates the inversion of all the LD bus signals. When LCDMODE1<LDINV>=1, all display data is forcefully inverted and the LDIV signal is also driven high.
Page 555 3.19.4 Interrupt Function The LCDC has two types of interrupts. One is generated synchronous with the LLOAD signal and the other is generated synchronous with the LLOAD signal that is output immediately after the LVSYNC signal. LCDMODE1<INTMODE> is used to switch between these two types of interrupts. LVSYNC LHSYNC LLOAD...
Page 556 3.19.5 Special Functions 3.19.5.1 PIP (Picture in Picture) Function The TMP92CZ26A includes a PIP (Picture in Picture) function that allows a different screen to be displayed over the screen currently being displayed on the LCD. The PIP function manages the address space of display memory by dividing it into “main screen”...
Page 557 The table below shows the HOT point locations that can be specified. *VRAM Access Monochrome display 16bit 32bit 4-grayscale display 16bit 32bit 16-grayscale display 16bit 32bit 64-grayscale display 16bit 32bit 256-color display 16bit 32bit 4K-color display 16bit 32bit 64K-color display 16bit 32bit 16bit...
Page 558 LSAML bit Symbol LMSA7 (02A0H) Read/Write After reset Function LSAMM bit Symbol LMSA15 (02A1H) Read/Write After reset Function LSAMH bit Symbol LMSA23 (02A2H) Read/Write After reset Function LSASL bit Symbol LSSA7 (02A4H) Read/Write After reset Function LSASM bit Symbol LSSA15 (02A5H) Read/Write After reset...
Page 559 LSAHX bit Symbol SAH7 (02A8H) Read/Write After reset Function (02A9H) bit Symbol Read/Write After reset Function LSAHY bit Symbol SAHY7 (02AAH) Read/Write After reset Function (02ABH) bit Symbol Read/Write After reset Function Note: The HOT point should be set in units of the specified number of dots, which is determined by the display color mode and display RAM access data bus width.
Page 560 LSACS bit Symbol SAC7 (02AEH) Read/Write After reset Function (02AFH) bit Symbol Read/Write After reset Function Note: The common size should be set in units of 1 line. LCD Sub Area Display Common Size Register SAC6 SAC5 SAC4 SAC3 LCD sub area common size (7-0) LCD sub area common size (8) 92CZ26A-557 TMP92CZ26A...
Page 561 3.19.5.2 Display Data Rotation Function When display RAM data is output to the LCD driver (LCDD), the data output direction can be automatically rotated by hardware to meet the specifications of the LCDD (or LCD module) to be used. Table 3.19.2 Operation Conditions Item Display size Color mode...
Page 562 the need to rewrite the display RAM data. 2. 90-Degree Rotation Function Display RAM Image (QVGA 320×240) QVGA (320×240) The display RAM image above shows typical data of QVGA size (320 segments × 240 commons: landscape type). If the LCDD to be used is of landscape type, the data can be written to the LCDD without any problem.
Page 563 3. Setting Method The <LDC2:0> bits in the LCDMODE1 register are used to set the display data rotation function. bit Symbol LDC2 LCDMODE1 (0281H) Read/Write After reset Data rotation function (Supported for 64K-color: 16 bps only) 000: Normal Function 001: Horizontal flip 101: Reserved 010: Vertical flip 110: Reserved 011: Horizontal and vertical flip Note: The <LDC2:0>...
Page 564 3.19.5.3 Considerations for Using the LCDC 1． If the operation mode is changed while the LCDC is operating, a maximum of one frame may not be displayed properly. Although this degree of disturbance does not normally pose any problem (e.g. no response on LCD, display not visible to human eyes), the actual operation largely depends on the conditions such as the LCD driver, LCD panel, and frame frequency to be used.
Page 565 3.19.6 Setting Example • T6C13B TM P92CZ26 (240-row Driver) TEST Di7-Di0 DUAL VCCL/R, V0L/R, V1L/R, V4L/R, V5L/R LVSYNC LCP0 LHSYNC port LD7∼ LD0 Note: The LCD drive power for LCD display must be supplied from an external circuit. Figure 3.19.11 STN-Type LCD Driver Connection Example CO M001 240COM ×...
Page 566 • JB T 6L78-AS (162-gate D riv e r) 92C Z26 V D D VD D U /D T E ST 1 V SS T E ST 2 V SS LG O E 2-0 O E3-1 LVS YN C LC P 0 LLO A D LF R LH SY N C...
Page 567 3.20 Touch Screen Interface (TSI) The TMP92CZ26A has an interface for 4-terminal resistor network touch-screen. This interface supports two procedures: an X/Y position measurement and touch detection. Each procedure is performed by setting the TSI control register (TSICR0 and TSICR1) and using an internal AD converter.
Page 568 3.20.2 Touch Screen Interface (TSI) Control Register bit Symbol TSI7 INGE TSICR0 Read/Write (01F0H) After reset 0: Disable Input gate 1: Enable control of Function Port 96,97 0: Enable 1: Disable PXD (internal pull-down resistor) ON/OFF setting PXEN < > <TSI7>...
Page 569 3.20.3 Touch detection procedure A Touch detection procedure shows procedure until a pen is touched by the screen and it is detected. By touching, TSI generates interrupt (INT4) and this procedure will terminate. After an X/Y position measuring procedure is terminated, return to this procedure and wait for next touch. When touch is waiting, set SPY-switch to ON, and set other 3 switches (SMY, SPX and SMX) to OFF.
Page 570 P96/INT4 pin Reset the counter for de-bounce time INT4 INT4 is generated by matching counter and specified de-bounce time. Figure 3.20.4 Timing diagram of de-bounce circuit Start the counter for de-bounce time de-bounce time de-bounce time INT4 isn’t generated by matching counter and specified de-bounce time because of it is an edge-type interrupt.
Page 571 3.20.4 X/Y position measuring procedure In the INT4 routine, execute an X/Y position measuring procedure like below. <X position measurement> At first, set both SPX, SMX-switches to ON, and set SPY, SMY-switches to OFF. By this setting, analog-voltage which shows the X-position will be inputted to PG3/MY/AN3 pin.
Page 572 3.20.5 Flow chart for TSI (1) Touch Detection Procedure Main Routine: TSICR0←98H TSICR1←XXH (voluntary) Execute Main Routine Following pages explain each circuit condition of (a), (b) and (c) in above flow chart. (2) X/Y Position Measurement Procedure Figure 3.20.6 Flow chart for TSI 92CZ26A-569 TMP92CZ26A INT4 Routine:...
Page 573 (a) Main routine (condition of waiting INT4 interrupt) (p9fc)<P96F>, <P97F>= “1” (inte34) (tsicr0)=98h TMP92CZ26A AVCC (PY/P97) Touch (PX/P96/INT4) Screen (MY/PG3) (MX/PG2) VREFH VREFL AVSS Set P96 to int4/PX, set P97 to PY Set interrupt level of INT4 Pull-down resistor on, SPY on, Interrupt-set<TWIEN> Enable interrupt PXD (typ.50kΩ) 92CZ26A-570...
Page 574 (b) X position measurement (Start AD conversion) (tsicr0)=c5h (admod1)=b0h (admod0)=08h TMP92CZ26A AVCC (PY/P97) Touch (PX/P96/INT4) Screen (MY/PG3) (MX/PG2) VREFH VREFL AVSS Set SMX, SPX to ON. Set the input gate of P97, P96 to OFF. Set to AN3. Start AD conversion. PXD (typ.50kΩ) 92CZ26A-571 TMP92CZ26A...
Page 575 (c) Y position measurement(Start AD conversion) (tsicr0)=cah (admod1)=a0h (admod0)=08h TMP92CZ26A AVCC (PY/P97) Touch (PX/P96/INT4) Screen (MY/PG3) (MX/PG2) VREFH VREFL AVSS Set SMX, SPX to ON. Set the input gate of P97, P96 to OFF. Set to AN2. Start AD conversion. PXD (typ.50kΩ) 92CZ26A-572 TMP92CZ26A...
Page 576 3.20.6 Note De-bounce circuit The system clock of CPU is used in de-bounce circuit. Therefore, de-bounce circuit is not operated when clock is not supplied to CPU (IDLE1, STOP mode or PCM mode). And, an interrupt which through the de-bounce circuit is not generated. When started from IDLE1, STOP or PCM mode by using TSI, set the de-bounce circuit to disable before a condition become to HALT or PCM mode.
Page 577 3.21 Real time clock (RTC) 3.21.1 Function description for RTC 1) Clock function (hour, minute, second) 2) Calendar function (month and day, day of the week, and leap year) 3) 24 or 12-hour (AM/PM) clock function 4) +/- 30 second adjustment function (by software) 5) Alarm function (Alarm output) 6) Alarm interrupt generate 3.21.2...
Page 578 3.21.3 Control registers Table 3.21.1 PAGE 0 (Timer function) registers Symbol Address Bit7 Bit6 SECR 1320H 40 sec MINR 1321H 40 min HOURR 1322H 20 hours/ DAYR 1323H DATER 1324H Day 20 MONTHR 1325H YEARR 1326H Year 80 Year 40 Year 20 PAGER 1327H Interrupt enable...
Page 579 3.21.4 Detailed explanation of control register RTC is not initialized by reset. Therefore, all registers must be initialized at the beginning of the program. (1) Second column register (for PAGE0 only) SECR Bit symbol (1320H) Read/Write After reset Function "0" is read. Undefined 40 sec.
Page 580 (2) Minute column register (for PAGE0/1) MINR Bit symbol (1321H) Read/Write After reset Function "0" is read. Undefined 40 min, 20 min, 10 min, column column column Note: Do not set the data other than showing above. 92CZ26A-577 TMP92CZ26A 8 min, 4 min, 2 min, column...
Page 581 (3) Hour column register (for PAGE0/1) In case of 24-hour clock mode (MONTHR<MO0>= “1”) HOURR Bit symbol (1322H) Read/Write After reset Function "0" is read. In case of 24-hour clock mode (MONTHR<MO0>= “0”) HOURR Bit symbol (1322H) Read/Write After reset Function "0"...
Page 582 (4) Day of the week column register (for PAGE0/1) DAYR Bit symbol (1323H) Read/Write After reset Function (5) 日桁レジスタ (PAGE0/1) DATER Bit symbol (1324H) Read/Write After reset Function "0" is read. "0" is read. Day 20 Day 10 Day 8 Note1: Do not set the data other than showing above.
Page 583 (6) Month column register (for PAGE0 only) MONTHR Bit symbol (1325H) Read/Write After reset Function "0" is read. (7) Select 24-hour clock or 12-hour clock (for PAGE1 only) MONTHR Bit symbol (1325H) Read/Write After reset Function 10 months 8 months Note: Do not set the data other than showing above.
Page 584 (8) Year column register (for PAGE0 only) YEARR Bit symbol (1326H) Read/Write After reset Function 80 Years Note: Do not set the data other than showing above. (9) Leap-year register (for PAGE1 only) YEARR Bit symbol (1326H) Read/Write After reset Function Undefined 40 Years...
Page 585 (10) PAGE register (for PAGE0/1) PAGER Bit symbol INTENA (1327H) Read/Write After reset Read-modify Function (Note) write Interrupt instruction 1: Enable 0: Disable prohibited Note: Pleas keep the setting order below and don’t set same time. (Set difference time to Clock/Alarm setting and interrupt setting) (Example) Clock setting/Alarm setting (pager), 0ch (pager), 8ch...
Page 586 3.21.5 Operational description (1) Reading timer data There is the case, which reads wrong data when carry of the inside counter happens during the operation which clock data reads. Therefore please read two times with the following way for reading correct data. Figure 3.21.2 Flowchart of timer data read Start PAGER<PAGE>...
Page 587 (2) Timing of INTRTC and Clock data When time is read by interrupt, read clock data within 0.5s(s) after generating interrupt. This is because count up of clock data occurs by rising edge of 1Hz pulse cycle. ALARM INTRTC 1s counter (Internal signal) 1s count UP (Internal signal)
Page 588 (3) Writing timer data When there is carry on the way of write operation, expecting data can not be wrote exactly. Therefore, in order to write in data exactly please follow the below way. Resetting a divider In RTC inside, there are 15-stage dividers, which generates 1Hz clock from 32,768 KHz.
Page 589 Disabling the timer Carry of a timer is prohibited when write “0” to PAGER<ENATMR> and can prevent malfunction by 1s Carry hold circuit. During a timer prohibited, 1s Carry hold circuit holds one sec. carry signal, which is generated from divider. After becoming timer enable state, output the carry signal to timer and revise time and continue operation.
Page 590 3.21.6 Explanation of the interrupt signal and alarm signal Can use alarm function by setting of register of PAGE1 and output either of three signals from ALARM pin as follows by write “1” to PAGER<PAGE>. INTRTC outputs 1shot pulse when the falling edge is detected. RTC is not initializes by RESET. Therefore, when clock or alarm function is used, clear interrupt request flag in INTC (interrupt controller).
Page 591 (2) When output clock of 1Hz RTC outputs clock of 1Hz to RESTR<DIS1HZ>= “0”, <DIS16HZ>= “1”. And RTC generates INTRC interrupt by falling edge of the clock. (3) When output clock of 16Hz RTC outputs clock of 16Hz to RESTR<DIS1HZ>= “1”, <DIS16HZ>= “0”. And RTC generates INTRC interrupt by falling edge of the clock.
Page 592 3.22 Melody / Alarm generator (MLD) TMP92CZ26A contains melody function and alarm function, both of which are output from the MLDALM pin. Five kind of fixed cycles interrupt is generate by using 15bit counter, which is used for alarm generator. Features are as follows.
Page 593 3.22.1 Block Diagram [Melody Generator] MELFH <MELON> Stop and Clear Low-speed clock 15bit conter (UC1) 4096 Hz 8bit counter MELALMC<FC1:0> Alarm wave form ALM register [Alarm Generator] Internal data bus Internal data bus MELFH, MELFL register Invert Comparator (CP0) Clear 12bit counter (UC0) Edge detectior...
Page 594 3.22.2 Control registers bit Symbol (1330H) Read/Write After reset Function MELALMC bit Symbol (1331H) Read/Write After reset Free-run counter control 00: Hold Function 01: Restart 10: Clear 11: Clear & Start Note1: MELALMC<FC1> is read always “0”. Note2: When setting MELALMC register except <FC1:0> during the free-run counter is running, <FC1:0> is kept “01”. MELFL bit Symbol (1332H)
Page 595 3.22.3 Operational Description 3.22.3.1 Melody generator The Melody function generates signals of any frequency (4Hz-5461Hz) based on low-speed clock (32.768KHz) and outputs the signals from the MLDALM pin. By connecting a loud speaker outside, Melody tone can easily sound. (Operation) At first, MELALMC<MELALM>...
Page 596 3.22.3.2 Alarm generator The Alarm function generates eight kinds of alarm waveform having a modulation frequency 4096Hz determined by the low-speed clock (32.768 KHz). And this waveform is reversible by setting a value to a register. By connecting a loud speaker outside, Alarm tone can easily sound. Five kind of fixed cycles (1Hz, 2Hz, 64Hz, 512Hz, 8192Hz) interrupt be generate by using a counter which is used for alarm generator.
Page 597 Example: Waveform of alarm pattern for each setting value: not invert) AL1 pattern (Continuous output) AL2 pattern (8 times/1 sec) 31.25 ms AL3 pattern (once) AL4 pattern (Twice/1 sec) 62.5 ms AL5 pattern (3 times/1 sec) 62.5 ms AL6 pattern (1 times) 62.5 ms AL7 pattern...
Page 598 3.23 Analog-Digital Converter (ADC) This LSI has a 6-channel, multiplexed-input, 10-bit successive-approximation Analog-Digital converter (ADC). Figure 3.23.1 shows a block diagram of the AD converter. The 6-analog input channels (AN0-AN5) can be used as general-purpose inputs. Note1: Ensure that the AD converter has halted before executing HALT instruction to place the TMP92CZ26A in IDLE2, IDLE1, STOP or PCM mode to reduce power consumption current.
Page 599: Control Register
3.23.1 Control register The AD converter has 6-mode control registers (ADMOD0, ADMOD1, ADMOD2, ADMOD3, ADMOD4 and ADMOD5) and 6-conversion result high/low register pairs (ADREG0H/L ∼ ADREG5H/L). The results of high-priority AD conversion are stored in the ADREGSPH/L. Figure 3.23.2 to Figure 3.23.11 show the registers available in the AD converter. AD Mode Control Register 0 (Normal conversion control) bit Symbol ADMOD0...
Page 600 AD Mode Control Register 1 (Normal conversion control) bit Symbol DACON ADMOD1 Read/Write (12B9H) After reset Analog input channel select VREF application control Function ADCH2 ADCH1 ADCH0 Latency 0: No Wait 1:Start after reading conversion result store Register of last channel Analog input channel select <SCAN>...
Page 601 AD Mode Control Register 2 (High-priority conversion control) bit Symbol HEOS ADMOD2 (12BAH) Read/Write After reset High-priority High-priority Function AD conversion AD conversion sequence BUSY Flag FLAG 0: During 0:Stop conversion 1:During sequence or before starting 1: Complete conversion sequence AD Mode Control Register 3 (High-priority conversion control) −...
Page 602 AD Mode Control Register 4 (AD Monitor function control) bit Symbol CMEN1 ADMOD4 (12BCH) Read/Write After reset AD Monitor Function function1 0: Disable 1: Enable Note: When AD monitor function interrupts generate, it is cleared automatically and it is set to disable condition.
Page 603 bit Symbol ADR01 ADREG0L (12A0H) Read/Write After reset Function Store Lower 2 bits of AN0 AD conversion result bit Symbol ADR09 ADREG0H (12A1H) Read/Write After reset Function bit Symbol ADR11 ADREG1L (12A2H) Read/Write After reset Function Store Lower 2 bits of AN1 AD conversion result bit Symbol...
Page 604 bit Symbol ADR21 ADREG2L (12A4H) Read/Write After reset Function Store Lower 2 bits of AN2 AD conversion result bit Symbol ADR29 ADREG2H (12A5H) Read/Write After reset Function bit Symbol ADR31 ADREG3L (12A6H) Read/Write After reset Function Store Lower 2 bits of AN3 AD conversion result bit Symbol...
Page 605 ADREG4L bit Symbol ADR41 (12A8H) Read/Write After reset Function Store Lower 2 bits of AN4 AD conversion result bit Symbol ADR49 ADREG4H (12A9H) Read/Write After reset Function bit Symbol ADR51 ADREG5L (12AAH) Read/Write After reset Function Store Lower 2 bits of AN5 AD conversion result bit Symbol...
Page 606 High-priority AD Conversion Result Register SP Low bit Symbol ADRSP1 ADREGSPL (12B0H) Read/Write After reset Function Store Lower 2 bits of an AD conversion result High-priority AD Conversion Result Register SP High bit Symbol ADRSP9 ADREGSPH (12B1H) Read/Write After reset Function Channel X conversion result •...
Page 607 AD Conversion Result Compare Criterion Register 0 Low bit Symbol ADR21 ADCM0REGL (12B4H) Read/Write After reset Function Store Lower 2 bits of an AD conversion result compare criterion AD Conversion Result Compare Criterion Register 0 High bit Symbol ADR29 ADCM0REGH (12B5H) Read/Write After reset...
Page 608 AD Conversion Clock Setting Register bit Symbol ADCCLK (12BFH) Read/Write After reset Function Note1: AD conversion is executed at the clock frequency selected in the above register. To assure conversion accuracy, however, the conversion clock frequency must not exceed 12MHz MHz.
Page 609 3.23.2 Operation 3.23.2.1 Analog Reference Voltages The VREFH and VREFL pins provide the analog reference voltages for the ADC. 3.23.2.2 Analog Input Channel(s) selection The Analog input channels used for AD conversion are selected as follows: Normal AD conversion • Analog Input Channel Fixed mode (ADMOD1<SCAN> = “0”) Setting ADMOD1<ADCH2:0>...
Page 610 3.23.2.3 Starting an AD Conversion The ADC supports two types of AD conversion: normal AD conversion and high-priority AD conversion. The ADC initiates a normal AD conversion by software when the ADMOD0<ADS> is set to “1”. It initiates a high-priority AD conversion by software when the ADMOD2<HADS>...
Page 611 3.23.2.4 AD Conversion Modes and AD Conversion-End Interrupts The ADC supports the following four conversion modes. For a normal AD conversion, ADMOD0<1:0> select one of the four conversion modes. For a high-priority AD conversion, the ADC only supports Channel Fixed Single Conversion mode. a.
Page 612 If ADMOD1<ITM> is set to “1”, the ADC generates an interrupt after every four conversions. The results of conversions are sequentially stored in the ADREG0H/L to ADREG3H/L registers, in that order. The ADMOD0<EOS> is set to “1” when the ADC stores the results in the ADREG3H/L. The next conversion results are again stored in the ADREG0, and so on.
Page 613 Interrupt Generation Timing and Flag Setting in Each AD Conversion Mode Interrupt Conversion mode Generation Timing Channel Fixed After a Single Conversion conversion Mode Channel Fixed After every Repeat conversion Conversion Mode After every four conversions Channel Scan After a scan Single Conversion conversion Mode...
Page 614 3.23.2.5 High-Priority Conversion Mode The ADC can perform a high-priority AD conversion while it is performing a normal AD conversion sequence. A high-priority AD conversion can be started at software by setting the ADMOD2<HADS> to “1”. It is also triggered by a hardware trigger if so enabled using ADMOD2<HTSEL1:0>.
Page 615 3.23.2.8 Storing and Reading the AD Conversion Result Conversion results are stored into AD conversion result high/low register (ADREG0H/L to ADREG5H/L). In Channel Fixed Repeat Conversion mode, conversion results are stored into the ADREG0H/L to ADREG3H/L sequentially. In other modes, the AD conversion result of channel AN0, AN1, AN2, AN3, AN4, and stored ADREG4H/L, and ADREG5H/L respectively.
Page 616 Table 3.23.1 Relationships between Analog Input Channels and AD Conversion Result Registers Analog Input Channel (Port G) Note: For detect a overrun error thoroughly, read the AD conversion result register high at first and read the AD conversion result register low at second. If OVRn=”0” and ADRnRF=”1”, a correct conversion result was obtained.
Page 617 Setting example: Convert the analog input voltage on the AN3 pin and write the result to memory address 2800H using the AD interrupt(INTAD) processing routine. Main routine ← 1 − − INTEAD ← 1 ADMOD1 ← X ADMOD0 Interrupt routine processing example ←...
Page 618 3.24 Watchdog Timer (Runaway detection timer) The TMP92CZ26A contains a watchdog timer of runaway detecting. The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that the CPU has started to malfunction (runaway) due to causes such as noise. When the watchdog timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of the malfunction.
Page 619 3.24.2 Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD<WDTP1:0> has elapsed. The watchdog timer must be cleared “0” in software before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway occurs) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
Page 620 3.24.3 Control Registers The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode registers (WDMOD) Setting the detection time for the watchdog timer in <WDTP1:0> This 2-bit register is used for setting the watchdog timer interrupt time used when detecting runaway.
Page 621 WDMOD Bit symbol WDTE (1300H) Read/Write After reset Function WDT control 1: Enable Figure 3.24.4 Watchdog Timer Mode Register WDCR Bit symbol (1301H) Read/Write After reset Read -modify Function B1H: WDT disable code -write 4EH: WDT clear code instruction is prohibited Figure 3.24.5 Watchdog Timer Control Register WDTP1...
Page 622 3.25 Power Management Circuit (PMC) The TMP92CZ26A incorporates a power management circuit (PMC) for managing power supply in standby state as protective measures against leak current in fine-process products. The following six power supply rails are available. ･Analog power supply ･3V-A, 3V-B digital I/O power supply ･1.5V-A digital internal power supply ･1.5V-B digital internal power supply...
Page 623 3.25.1 SFR bit symbol PCM_ON PMCCTL Read/Write (02F0H) After system reset After hot Data reset retained Power Cut Mode Function 0: Disable 1: Enable Note: After wake-up interruption, internal wake-up timer count setting register value:<WUTM1:0>, and after about 77us, external PWE terminal change from low level to high level. Additionally after more about 92us, internal reset signal will be released.
Page 624 3.25.2 Detailed Description of Operation This section explains the procedures for entering and exiting the Power Cut Mode. • Entering the Power Cut Mode When to enter the Power Cut Mode, the CPU needs to be operating in the internal RAM. Low frequency clock (XT) must be enable condition.
Page 625 1. Prepare to shift Power Cut Mode (1) Set the warm-up time: PMCCTL<WUTM1:0> After wake-up interruption, internal wake-up timer count setting register value:<WUTM1:0>, and after about 77us, external PWE terminal change from low level to high level. Additionally after more about 92us, internal reset signal will be released.
Page 626 • Exiting the Power Cut Mode The Power Cut Mode can be exited by external or internal interruption. (It inhibits to exit the Power Cut Mode by reset when DVCC1A is cut off. Reset must be asserted after supplying power to DVCC1A and waiting for its voltage to fully stabilize.) The interrupts that can be used to exit the Power Cut Mode are RTC interrupt, INT0 to INT7 (TSI interrupt) and INTKEY interrupt.
Page 627 3.25.3 Detailed Description of Timing 1. A maximum of 3 clocks (92 μs) are needed for entering PCM. CPU state transition Normal PMCCTL<PCM_ON> PWE pin INTRTC INT0-7, INTKEY Internal HOT_RESET Port state Internal HOT_RESET assert to dead circuit only. (DVCC1A &DVCC1C circuit) If it is set PMCCTL<PCM_ON>=“1”, shift the Power Cut Mode, however, it spends 3-clock times maximum (around 92μS) to shift from normal mode to Power Cut Mode.
Page 628 SW en SW en TMP92CZ26A AVCC DVCC-1C DVCC-1A Other Logic High_OSC AVSS DVSS-1C DVSS-COM Figure3.25.2 Example External Circuitry for Using the PMC Figure3.25.2 shows an example of external circuitry for using the PMC. In normal mode, the power management pin (PWE) outputs “1” and power is supplied to all the blocks in the TMP92CZ26A.
Page 629 3.25.4 Notes of Power sequence • Power ON/Power OFF Sequence (Initial Power ON/Complete Power OFF) In the power ON sequence (initial power ON), power must be supplied to internal circuits first and then to external circuits, as shown below. In the power OFF sequence (complete power OFF), power must be turned off from external circuits so that internal circuits are turned off last.
Page 630 3.25.5 Setting Example Condition: Wake-up trigger=INT4(TSI) 002000h (syscr0),40h (wdmod),0b100h (admod0),0000h (admod2),0000h (admod4),0000h (lcdctl0),00h (pmfc),80h (p9fc),40h (inte34),50h (tsicr1),00h (pllcr0), 00h (pllcr1), 00h (pmcctl),00h (pmcctl),80h ; After Wake-up 046000h (pmcctl),00h Enable low frequency clock Disable WDT Disable AD converter Disable DMA operation Set PM7 port to PWE function Set INT4 and set level Disable de-bounce circuit...
Page 631 3.26 Multiply and Accumulate Calculation Unit (MAC) The TMP92CZ26A includes a multiply-accumulate unit (MAC) capable of 32-bit × 32-bit + 64-bit arithmetic operations at high speed. The MAC has the following features: ・One-cycle execution for all MAC operations (excluding register access time) ・Three operation modes : 1) 64-bit + 32-bit ×...
Page 632: Data Registers
3.26.1.2 Data Registers The data registers are arranged as shown below. Bits<63:56> Bits<55:48> Multiplier A Register Multiplier B Register Register (1BEFH) (1BEEH) Note 1: After reset, all the registers are cleared to “0”. Note 2: Read-modify-write instructions can be used on all the registers. Note 3: All the registers can be accessed in long word, word, or byte units.
Page 633 3.26.2 Description of Operation Calculation mode The MAC has the following three types of calculation mode. The calculation mode to be used is specified in MACCR<MOPMD1:0>. MACCR<MSMD> is used to select unsigned or signed mode. The operation of each calculation mode is explained below. (a) 64 + 32 ×...
Page 634 (d) Sign mode Both multiply-accumulate and multiply-subtract operations can be executed in unsigned or signed mode. In signed mode, the MACMA, MACMB, and MACOR registers become signed registers, and the most significant bit is treated as the sign bit and the data set in each register is treated as a two’s complement value.
Page 635 3.26.3 Operation Examples (1) Unsigned multiply-accumulate operation The following shows a setting example for calculating “33333333 + 11111111 × 22222222”: (MACCR), 0x08 xde, 0x00000000 xhl, 0x33333333 xix, 0x11111111 xiy, 0x22222222 (MACORL), xhl (MACORH), xde (MACMA), xix (MACMB), xiy xhl, (MACORL) 7, (MACCR) nz, ERROR xde, (MACORH)
Page 636: Debug Mode
3.27 Debug Mode The TMP92CZ26A includes a debug support unit (DSU) for enabling on-board debugging. The DSU has 9 debug pins for interfacing with an external emulator via a DSU connector to be mounted on the target board and a DSU connecting cable. For details about debugging, please refer to the instruction manual of the emulation pod to be used.
Page 637 (3) Limitations in debug mode Debug mode has the following limitations: 1) Target reset While debugging is being performed, the system reset ( (microcontroller) must not be used to reset the controller and microcontroller. Instead, reset should be performed from the controller. (For details, please refer to the instruction manual of the emulation pod to be used.) * If reset from the microcontroller by the and internal RAM data in the CPU, including not only programs but also breakpoint...
Page 638 2) Pins In debug mode, a total of 9 pins (PZ0 to PZ7 in Port Z and PU7 in Port U) are used to connect the TMP92CZ26A with an emulator via a DSU probe for communicating with the controller. For this reason, these 9 pins cannot be debugged. Therefore, if the port control register of each pin is changed in debug mode, the register contents are changed but the function of each pin remains the same.
Page 639 Bit Symbol (00A4H) Read/Write After reset Bit Symbol PU7C PUCR (00A6H) Read/Write After reset Function Bit Symbol PU7F PUFC Read/Write (00A7H) After reset Function PU7D Bit Symbol PUDR (009CH) Read/Write After reset Function Note: Although it is possible to write to shaded bits, writing to these bits has no effect (the DSU communication function is given a higher priority).
Page 640 3) Boot function In this LSI, we support boot function, however, this boot function is not available in debug mode. (It is inhibit to set 4) PMC function In debug mode, the PMC function for cutting off the power supply to internal circuitry and reducing standby current is not also available.
Page 641 5) Data bus occupancy The TMP92CZ26A includes three controllers (LCD controller, SDRAM controller and DMAC) that function as bus masters apart from the CPU. Therefore, it is necessary to estimate the bus occupancy time of each bus master and control each function accordingly to ensure proper operation of each function.
Page 642 LHSYNC LCP0 LD-bus LCD DMA operation 1 HDMA operation 1 (Worst case) Steal operation (Worst case) LCD DMA operation 2 HDMA operation 2 Figure 3.27.2 Example of Data Bus Occupancy Timing in Debug Mode Figure 3.27.2 shows an example of data bus occupancy timing in debug mode. If the steal program issues a wait request immediately before the DMA operation for the LCD (LCD DMA operation 1) and HDMA (HDMA operation 1) are asserted, these operations must wait until the steal program is finished before they can be performed.
Page 643: Maximum Ratings
Electrical Characteristics (Tentative) 4.1 Maximum Ratings Symbol DVCC3A DVCC3B DVCC1A Power Supply Voltage DVCC1B DVCC1C AVCC V IN Input Voltage Output Current (1pin) Output Current (1pin) Σ IOL Output Current (total) Σ IOH Output Current (total) Power Dissipation (Ta = 85°C) T SOLDER Soldering Temperature (10s) T STG...
Page 644: Dc Electrical Characteristics
4.2 DC Electrical Characteristics Symbol Parameter General I/O DVCC Power Supply Voltage (DVCC=AVCC) (DVSSCOM=AVSS=0V) DVCC Internal Power A DVCC Internal Power B DVCC High CLK oscillator and PLL Power Input Low Voltage for D0 to D7 P10 to P17 (D8 to 15), P60 to P67 P71 to P76, P90 VIL0 PC4 to PC7, PF0 to PF5...
Page 645 Symbol Parameter Input High Voltage for D0 to D7 P10 to P17 (D8 to 15), P60 to P67 P71 to P76, P90 VIH0 PC4 to PC7, PF0 to PF5 PG0 to PG5, PJ5 to PJ6 PN0 to PN7, PP1 to PP2 PR0 to PR3, PT0 to PT7 PU0 to PU7, PX5, PX7 Input High Voltage for...
Page 646 Symbol Parameter Output Low Voltage1 P90 to P92, PC0 to PC3, PC7 PF0 to PF5, PK1 to PK7 VOL1 PM1 to PM2, PM7 PN0 to PN7, PP1 to PP7 PV0 to PV7, PW0 to PW7, PX5, PX7 Output Low Voltage2 VOL2 Except VOL1 output pin Output High Voltage1...
Page 647 Symbol Parameter NORMAL (note2) IDLE2 NORMAL (note2) IDLE2 IDLE1 Power Cut Mode (WITH PMC function ) STOP Note1 : Typical values are value that when Ta = 25°C and Vcc = 3.3 V unless otherwise noted. Note2 : ICC measurement conditions (NORMAL, SLOW): All functions are operational;...
Page 648 AC Characteristics The Following all AC regulation is the measurement result in following condition, if unless otherwise noted. AC measuring condition Clock of top column in above table shows system clock frequency, and “T” shows system • clock period [ns]. Output level: High = 0.7×3AV •...
Page 649: Write Cycle
Write cycle Parameter D0 ~ D15 valid 16-1 → xx rising at 0 waits D0 ~ D15 valid 16-2 → xx rising at 2 waits/4 waits 17-1 xx low width at 0 waits xx low width at 2 waits/4 waits 17-2 18 A0 ~ A23 valid →...
Page 650 (1) Read cycle (0 waits) SDCLK WAIT A0~A23 D0~D15 SRxxB SRWR Note1: The phase relation between X1 input signal and the other signals is undefined. Note2: The above timing chart show an example of basic bus pins timing can be adjusted by memory controller timing adjust function. 92CZ26A-647 Data input timing.
Page 651 (2) Write cycle (0 waits) SDCLK WAIT A0~A23 WRxx D0~D15 SRxxB SRWR Note1: The phase relation between X1 input signal and the other signals is undefined. Note2: The above timing chart show an example of basic bus pins timing can be adjusted by memory controller timing adjust function. 92CZ26A-648 Data output timing.
Page 652 (3) Read cycle (1 wait) SDCLK WAIT A0~A23 D0~D15 (4) Write cycle (1 wait) SDCLK WAIT A0~A23 WRxx D0~D15 Data input Data output 92CZ26A-649 TMP92CZ26A...
Page 653 Page ROM Read Cycle 4.3.2 (1) 3-2-2-2 mode Parameter 1 System clock period ( = T) → D0 ~ D15 input 2 A0, A1 → D0 ~ D15 input 3 A2 ~ A23 → D0 ~ D15 input falling 5 A0 ~ A23 Invalid → D0 ~ D15 hold →...
Page 654 4.3.3 SDRAM controller AC Characteristics Parameter Ref/Active to ref/active <STRC[2:0]>=000 command period <STRC[2:0]>=110 Active to precharge <STRC[2:0]>=000 command period <STRC[2:0]>=110 Active to read/write <STRCD>=0 command delay time <STRCD>=1 Precharge to active <STRP>=0 command period <STRP>=1 Active to active <STRC[2:0]>=000 command period <STRC[2:0]>=110 <STWR>=0 6 Write recovery time...
Page 655 (1) SDRAM read timing (1Word length read mode, <SPRE>=1) SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE A0~A9 A11~A15 D0~D15 Column 92CZ26A-652 TMP92CZ26A Data input...
Page 656 (2) SDRAM write timing (Single write mode, <SPRE>=1) SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE A0~A9 A11~A15 D0~D15 Column Data output 92CZ26A-653 TMP92CZ26A...
Page 657 (3) SDRAM burst read timing (Start burst cycle) SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE A0~A9 A11~A15 D0~D15 92CZ26A-654 TMP92CZ26A Column Data Data input Data input input...
Page 658 (4) SDRAM burst read timing (End burst timing) SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE A0~A9 Column A11~A15 D0~D15 Data input Data input 92CZ26A-655 TMP92CZ26A...
Page 659 (5) SDRAM initializes timing SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE A0~A9 A11~A15 92CZ26A-656 TMP92CZ26A...
Page 660 (6) SDRAM refreshes timing SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE (7) SDRAM self refresh timing SDCLK SDCKE SDxxDQM SDCS SDRAS SDCAS SDWE 92CZ26A-657 TMP92CZ26A...
Page 661 4.3.4 NAND Flash Controller AC Characteristics No. Symbol Parameter Access cycle low level width NDRE data access time NDRE Read data hold time low level width NDWE Write data setup time Write data hold time AC measuring condition Note1: The “n” in “Variable” means wait-number which is set to NDFMCR0<SPLW1:0>, and “m” means number which is set to NDFMCR0<SPHW1:0>.
Page 662 4.3.5 Serial channel timing (1) SCLK input mode (I/O interface mode) Parameter Symbol SCLK cycle Output data → SCLK rising/ falling SCLK rising/ falling → Output data hold SCLK rising/ falling → Input data hold SCLK rising/ falling → Input data valid Input data valid →...
Page 663: Interrupt Operation
4.3.6 Timer input pulse (TA0IN, TA2IN, TB0IN0, TB1IN0) Parameter Symbol Clock cycle Low level pulse width High level pulse width 4.3.7 Interrupt Operation Parameter Symbol INT0~INT7 low width INT0~INT7 high width 4.3.8 USB Timing (Full-speed) = 3.3 ± 0.3 V/f Parameter Symbol D + , D −...
Page 664: Lcd Controller
4.3.9 LCD Controller Parameter Symbol LCP0 clock period LCP0 high width (Include phase inversion) LCP0 low width (Include phase inversion) Data valid → LCP0 falling (Include phase inversion) LCP0 falling → Data hold (Include phase inversion) Signal delay from LCP0 basic changing point (Include phase inversion) LCP0...
Page 665 4.3.10 S Timing Parameter Symbol I2SCKO clock period I2SCKO high width I2SCKO low width I2SDO, I2SWS setup time I2SDO, I2SWS hold time I2SCKO I2SDO I2SWS Note: The Maximum operation frequency of I2SCKO in I2S circuit is 10MHz. Don’t set I2SCKO to value more than 10MHz. AC measuring condition •...
Page 666 4.3.11 SPI Controller Parameter Symbol SPCLK frequency ( = 1/S) SPCLK rising time SPCLK falling time SPCLK low width SPCLK high width Output data valid → SPCLK rising SPCLK rising/ falling → Output data hold Input data valid → SPCLK rising/ falling SPCLK rising/ falling →...
Page 667: Ad Conversion Characteristics
AD Conversion Characteristics Parameter Symbol Analog reference voltage ( + ) VREFH Analog reference voltage ( − ) VREFL AD converter power supply AVCC voltage AD converter ground AVSS Analog input voltage AVIN Analog current analog IREFON reference voltage IREFOFF Total error (Quantize error of ±...
Page 668 Table of Special function registers (SFRs) The SFRs include the I/O ports and peripheral control registers allocated to the 8-Kbyte address space from 000000H to 001FF0H. (1) I/O Port (2) Interrupt control (3) Memory controller (4) TSI(Touch screen I/F) (5) SDRAM controller (6) LCD controller (7) PMC (8) USB controller...
Page 669 Table 5.1 I/O Register Address Map [1] Port (1/2) Address Name Address 0000H 0010H P4 3H P4FC 4H P1 4H P5 6H P1CR 7H P1FC 7H P5FC 8H P6 AH P6CR BH P6FC CH P7 EH P7CR FH P7FC Address Name Address 0040H PG...
Page 670 [1] Port (2/2) Address Name Address 0080H 0090H PGDR 1H P1DR 3H PJDR 4H P4DR 4H PKDR 5H P5DR 5H PLDR 6H P6DR 6H PMDR 7H P7DR 7H PNDR 8H P8DR 8H PPDR 9H P9DR 9H PRDR AH PADR AH PZDR BH PTDR CH PCDR CH PUDR...
Page 671 [2] INTC Address Name Address 00D0H INTE12 00E0H INTESBIADM 1H INTE34 1H INTESPI 2H INTE56 2H Reserved 3H INTE7 3H INTEUSB 4H INTETA01 4H Reserved 5H INTETA23 5H INTEALM 6H INTETA45 6H Reserved 7H INTETA67 8H INTETB0 8H INTERTC 9H INTETB1 9H INTEKEY AH INTELCD BH INTES0...
Page 672 [5] SDRAMC Address Name 0250H SDACR 1H SDCISR 2H SDRCR 3H SDCMM SDBLS [6] LCDC Address Name Address 0280H LCDMODE0 0290H LCDHSDLY 1H LCDMODE1 1H LCDO0DLY 2H LCDO1DLY 3H LCDDVM0 3H LCDO2DLY 4H LCDSIZE 4H LCDHSW 5H LCDCTL0 5H LCDLDW 6H LCDCTL1 6H LCDHO0W 7H LCDCTL2...
Page 673 [8] USBC (1/2) Address Name Address 0500H Descriptor 0780H ENDPOINT0 1H ENDPOINT1 067FH (384 byte) 2H ENDPOINT2 3H ENDPOINT3 9H EP1_MODE AH EP2_MODE BH EP3_MODE Address Name 07B0H 1H EP1_SIZE_H_B 2H EP2_SIZE_H_B 3H EP3_SIZE_H_B Note: Do not access no allocated name address. Name Address Name...
Page 674 [8] USBC (2/2) Address Name 07E0H Port Status 1H FRAME_L 2H FRAME_H 3H ADDRESS 6H USBREADY 8H Set Descriptor STALL Note: Do not access no allocated name address. Address Name 07F0H USBINTFR1 1H USBINTFR2 2H USBINTFR3 3H USBINTFR4 4H USBINTMR1 5H USBINTMR2 6H USBINTMR3 7H USBINTMR4...
Page 675 [9] SPIC Address Name Address 0820H SPIMD 0830H SPITD0 1H SPIMD 1H SPITD0 2H SPICT 2H SPITD1 3H SPICT 3H SPITD1 4H SPIST 4H SPIRD0 5H SPIST 5H SPIRD0 6H SPICR 6H SPIRD1 7H SPICR 7H SPIRD1 CH SPIIE DH SPIIE [10] MMU Address Name...
Page 676 [11] NAND-Flash controller Address Name Address 08C0H NDFMCR0 08D0H NDRSCA0 1H NDFMCR0 2H NDFMCR1 3H NDFMCR1 4H NDECCRD0 5H NDECCRD0 6H NDECCRD1 7H NDECCRD1 8H NDECCRD2 9H NDECCRD2 AH NDECCRD3 BH NDECCRD3 CH NDECCRD4 DH NDECCRD4 Name Address 1FF0H NDFDTR0 1H NDRSCA0 1H NDFDTR0 2H NDRSCD0...
Page 677 [12] DMAC Address Name Address 0900H HDMAS0 0910H HDMAS1 1H HDMAS0 1H HDMAS1 2H HDMAS0 2H HDMAS1 4H HDMAD0 4H HDMAD1 5H HDMAD0 5H HDMAD1 6H HDMAD0 6H HDMAD1 8H HDMACA0 8H HDMACA1 9H HDMACA0 9H HDMACA1 AH HDMACB0 AH HDMACB1 BH HDMACB0 BH HDMACB1 CH HDMAM0...
Page 678 [13] CGEAR, PLL [14] 8-bit timer Address Name Address 10E0H SYSCR0 1100H TA01RUN 1H SYSCR1 2H SYSCR2 2H TA0REG 3H EMCCR0 3H TA1REG 4H EMCCR1 4H TA01MOD 5H EMCCR2 5H TA1FFCR 6H Reserved 8H PLLCR0 8H TA23RUN 9H PLLCR1 AH TA2REG BH TA3REG CH TA23MOD DH TA3FFCR...
Page 679 [18] 10-bit ADC Address Name Address 12A0H ADREG0L 12B0H ADREGSPL 1H ADREG0H 1H ADREGSPH 2H ADREG1L 2H Reserved 3H ADREG1H 3H Reserved 4H ADREG2L 4H ADCM0REGL 5H ADREG2H 5H ADCM0REGH 6H ADREG3L 6H ADCM1REGL 7H ADREG3H 7H ADCM1REGH 8H ADREG4L 8H ADMOD0 9H ADREG4H 9H ADMOD1...
Page 680 [22] I Address Name Address 1800H I2S0BUF 1810H I2S1BUF 8H I2S0CTL 8H I2S1CTL 9H I2S0CTL 9H I2S1CTL AH I2S0C AH I2S1C BH I2S0C BH I2S1C Note: Do not access no allocated name address. [23] MAC Name Address Name 1BE0H MACMA 1H MACMA 2H MACMA 3H MACMA...
Page 681 (1) I/O ports (1/11) Symbol Name Address PORT1 0004H PORT4 0010H PORT5 0014H PORT6 0018H PORT7 001CH PORT8 0020H PORT9 0024H Data from external port PORTA 0028H PORTC 0030H PORTF 003CH PORTG 0040H PORTJ 004CH PORTK 0050H PORTL 0054H PORTM 0058H PORTN 005CH...
Page 682 (1) I/O ports (2/11) Symbol Name Address PORTR 0064H PORTT 00A0H PORTU 00A4H PORTV 00A8H Data from external port (Output latch register is cleared to “0”) PORTW 00ACH PORTX 00B0H PORTZ 0068H Data from external port (Output latch register is cleared to “0”) Data from external port (Output latch register is cleared to “0”) Data from external port (Output latch register is cleared to “0”) Data from external port...
Page 683 (1) I/O ports (3/11) Symbol Name Address P17C PORT1 0006H P1CR control (Prohibit register RMW) PORT1 0007H P1FC function (Prohibit register RMW) P47F PORT4 0013H P4FC function (Prohibit register RMW) P57F PORT5 0017H P5FC function (Prohibit register RMW) P67C PORT6 001AH P6CR control...
Page 684 (1) I/O ports (4/11) Symbol Name Address P87F PORT8 0023H 0: Port P8FC function (Prohibit 1: <P87F2> register RMW) P87F2 PORT8 0021H CSXB P8FC2 function (Prohibit ND1CE fegister2 RMW) PORT9 0026H P9CR control (Prohibit register RMW) PORT9 0027H P9FC function (Prohibit register RMW)
Page 685 (1) I/O ports (5/11) Symbol Name Address PA7F PORTA 002BH PAFC function (Prohibit register RMW) PC7C PORTC 0032H 0: Input control (Prohibit PCCR register 1: Output RMW) KO output (Open -drain) PC7F PORTC 0033H 0: Port PCFC function (Prohibit 1:KO register RMW) output...
Page 686 (1) I/O ports (6/11) Symbol Name Address 0043H PORTG PGFC function (Prohibit register RMW) 004EH PORTJ PJCR control (Prohibit register RMW) PF7F 004FH PORTJ PJFC function (Prohibit 0: Port register RMW) 1: SDCKE PK7F 0053H PORTK PKFC function (Prohibit register RMW) 0: Port 1: LGOE2...
Page 687 (1) I/O ports (7/11) Symbol Name Address PN7C 005EH PORTN PNCR control (Prohibit register RMW) PN7F 005FH PORTN PNFC function (Prohibit register RMW) 0062H PORTP PPCR control (Prohibit register RMW) PP7F 0063H PORTP 0: Port PPFC function (Prohibit register RMW) TB1OUT0 0066H PORTR...
Page 688 (1) I/O ports (8/11) Symbol Name Address PU7C PORTU 00A6H PUCR control (Prohibit register RMW) PU7F PORTU 00A7H PUFC function (Prohibit 0: Port register RMW) 1: LD23 PV7C PORTV 00AAH PVCR control (Prohibit register RMW) 0: Input 1: Output PV7F PORTV 00ABH PVFC...
Page 689 (1) I/O ports (9/11) Symbol Name Address P17D PORT1 P1DR drive 0081H register P27D PORT2 P2DR drive 0082H register P37D PORT3 P3DR drive 0083H register P47D PORT4 P4DR drive 0084H register P57D PORT5 P5DR drive 0085H register P67D PORT6 P6DR drive 0086H register...
Page 690 (1) I/O ports (10/11) Symbol Name Address PORTG PGDR drive 0090H register PJ7D PORTJ PJDR drive 0093H register PK7D PORTK PKDR 0094H drive register PL7D PORTL PLDR drive 0095H register PM7D PORTM PMDR drive 0096H register PN7D PORTN PNDR drive 0097H register PP7D...
Page 691 (1) I/O ports (11/11) Symbol Name Address PW7D PORTW PWDR drive 009EH register PX7D PORTX PXDR 009FH drive register PZ7D PORTZ drive PZDR 009AH register PW6D PW5D PW4D Input/Output buffer drive register for standby mode PX5D PX4D Input/Output buffer drive register for standby mode PZ6D PZ5D...
Page 692 (2) Interrupt control (1/4) Symbol Name Address INTE0 INT0 enable 00F0H INT1 & INT2 INTE12 00D0H enable INT3 & INT4 INTE34 00D1H enable INT5 & INT6 INTE56 00D2H enable INT7 INTE7 00D3H enable INTTA0 & ITA1C INTETA01 INTTA1 00D4H enable INTTA2 &...
Page 693 (2) Interrupt control (2/4) Symbol Name Address INTUSB INTEUSB 00E3H enable INTALM INTEALM 00E5H enable INTRTC INTERTC 00E8H enable INTKEY INTEKEY 00E9H enable INTLCD INTELCD 00EAH enable INTI2S0 & II2S1C INTEI2S01 INTI2S1 00EBH enable INTRSC & IRSCC INTENDFC INTRDY 00ECH enable INTP0 INTEP0...
Page 694 (2) Interrupt control (3/4) Symbol Name Address INTTC0/INTDMA0 & INTETC01 INTTC1/INTDMA1 00F1H /INTEDMA01 enable INTTC2/INTDMA2 & INTETC23 INTTC3/INTDMA3 00F2H /INTEDMA23 enable INTTC4/INTDMA4 & INTETC45 INTTC5/INTDMA5 00F3H /INTEDMA45 enable INTTC6 & INTTC7 INTETC67 00F4H enable 00F5H SIMC interrupt mode (Prohibit control RMW) 00F6H Interrupt...
Page 695 (2) Interrupt control (4/4) Symbol Name Address DMA0 DMA0V start 0100H vector DMA1 DMA1V start 0101H vector DMA2 DMA2V start 0102H vector DMA3 DMA3V start 0103H vector DMA4 DMA4V start 0104H vector DMA5 DMA5V start 0105H vector DMA6 DMA6V start 0106H vector DMA7...
Page 696 (3) Memory controller (1/4) Symbol Name Address B0WW3 Write waits BLOCK0 0001: 0 CS/WAIT 0140H 0101: 2 B0CSL control (Prohibit 0111: 4 register RMW) 1001: 6 1011: 8 1101: 10 1111: 16 0011: 6 states + Others: Reserved BLOCK0 CS/WAIT 0141H CS select B0CSH...
Page 697 (3) Memory controller (2/4) Symbol Name Address B3WW3 Write waits BLOCK3 0001: 0 CS/WAIT 014CH 0101: 2 B3CSL control (Prohibit 0111: 4 register RMW) 1001: 6 1011: 8 1101: 10 1111: 16 0011: 6 states + Others: Reserved BLOCK3 CS/WAIT 014DH CS select B3CSH...
Page 698 (3) Memory controller (3/4) Symbol Name Address Memory M0V20 address MAMR0 0142H mask register 0 M0S23 Memory start MSAR0 0143H address register 0 M1V21 Memory address MAMR1 0146H mask register 1 M1S23 Memory start MSAR1 0147H address register 1 M2V22 Memory address MAMR2...
Page 699 (3) Memory controller (4/4) Symbol Name Address Page PMEMCR 0166H control register Adjust for Timing of CSTMGC 0168H control signal Adjust for Timing of 0169H WRTMGCRR control signal B1TCRS1 Adjust for Timing of Select delay time(TCRS) 016AH RDTMGCR0 control 00:0.5 signal 01:1.5 10:2.5...
Page 700 (4) TSI Symbol Name Address TSI7 0: Disable TSICR0 control 01F0H 1: Enable register0 DBC7 TSICR1 control 01F1H 0: Disable register1 1: Enable INGE PTST TWIEN Input gate Detection INT4 control of interrupt condition Port control 0: no 96,97 0: Disable touch 0: Enable 1: Enable...
Page 701 (5) SDRAM controller Symbol Name Address SRDS Read SDRAM data shift access SDACR 0250H function control 0: Disable register 1: Enable SDRAM Command Interval SDCISR 0251H Setting Register Always SDRAM write “0” refresh SDRCR 0252H control register SDRAM SDCMM command 0253H register SDRAM...
Page 702 (6) LCD controller (1/6) Symbol Name Address RAMTYPE1 RAMTYPE0 Display RAM 00: Internal RAM mode0 0280H 01: External SRAM MODE0 register 10: SDRAM 11: Reserved LDC2 Data rotation function (Supported for 64K-color: 16bps only) mode1 0281H MODE1 000: Normal register 001: Horizontal flip 010: Vertical flip 011: Horizontal &...
Page 703 (6) LCD controller (2/6) Symbol Name Address LCP0P LCP0 phase LCDCTL1 control1 0286H register 0:Rising 1:Falling LGOE2P LGOE2 LCDCTL2 control2 0287H phase register 0: Rising 1: Falling LHSYNC Pulse LCDHSP 028AH register LH15 LHSYNC LCDHSP Pulse 028BH register LVP7 LVSYNC LCDVSP Pulse 028CH...
Page 704 (6) LCD controller (3/6) Symbol Name Address LGOE0 Delay 0291H LCDO0DLY register LGOE1 Delay 0292H LCDO1DLY register LGOE2 Delay 0293H LCDO2DLY register HSW7 LHSYNC Width LCDHSW 0294H register LDW7 LLOAD LCDLDW width 0295H register O0W7 LGOE0 width 0296H LCDHO0W register O1W7 LGOE1 width...
Page 705 (6) LCD controller (4/6) Symbol Name Address Start LMSA7 address LSAML 02A0H register LCD main-L Start LMSA15 address LSAMM 02A1H register LCD main-M Start LMSA23 address LSAMH 02A2H register LCD main-H LSSA7 Start address LSASL 02A4H register LCD sub-L LSSA15 Start address LSASM...
Page 706 (7) PMC Symbol Name Address PCM_ON 02A0H After system reset Data After Hot reset retained PMCCTL Control Power Register Cut Mode 0: Disable 1: Enable 92CZ26A-703 TMP92CZ26A − WUTM1 WUTM0 Data Data − retained retained Always Warm-up time write “0” 00: 29 (15.625 ms) 01: 210 (31.25 ms) Always...
Page 707 (8) USB controller (1/6) Symbol Name Address Descriptor RAM 0 0500H Descriptor RAM0 register Descriptor RAM 1 0501H Descriptor RAM1 register Descriptor RAM 2 0502H Descriptor RAM2 register Descriptor RAM 3 0503H Descriptor RAM3 register Descriptor RAM 381 067DH Descriptor RAM381 register Descriptor RAM 382...
Page 708 (8) USB controller (2/6) Symbol Name Address Endpoint 0 status 0790H EP0_STATUS register Endpoint 1 0791H status EP1_STATUS register Endpoint 2 status 0792H EP2_STATUS register Endpoint 3 status 0793H EP3_STATUS register Endpoint 0 PKT_ACTIVE size 0798H EP0_SIZE_L_A register Low A Endpoint 0 PKT_ACTIVE size...
Page 709 (8) USB controller (3/6) Symbol Name Address Endpoint 1 size 07B1H EP1_SIZE_H_B register High B Endpoint 2 size 07B2H EP2_SIZE_H_B register High B Endpoint 0 size 07B3H EP3_SIZE_H_B register High B DIRECTION bmRequest- 07C0H bmRequestType Type register REQUEST7 bRequest 07C1H bRequest register wValue...
Page 710 (8) USB controller (4/6) Symbol Name Address SetupRecei- 07C8H SetupReceived ved register REMOTEWAKEUP Current_ 07C9H Current_Config Config register S_INTERFACE Standard- Request 07CAH Standard Request register Request 07CBH Request register EP3_DSET_B DATASET 1 07CCH DATASET1 register EP7_DSET_B DATASET 2 07CDH DATASET2 register USB state 07CEH...
Page 711 (8) USB controller (5/6) Symbol Name Address Reserved7 Port status 07E0H Port Status register Frame register 07E1H FRAME_L T[10] Frame 07E2H FRAME_H register H Address 07E3H ADDRESS register ready 07E6H USBREADY register Set- Set Descriptor Descriptor 07E8H STALL stall register INT_URST_STR INT_URST_END 07F0H interrupt...
Page 712 (8) USB controller (6/6) Symbol Name Address MSK_URST_STR MSK_URST_END interrupt 07F4H USBINTMR1 mask register 1 EP1_MSK_FA interrupt 07F5H USBINTMR2 mask register 2 EP3_MSK_FA interrupt 07F6H USBINTMR3 0: Be not masked mask 1: Be masked register 3 MSK_SETUP interrupt 07F7H USBINTMR4 mask register 4 TRNS_USE...
Page 713 SPIC (1/2) Symbol Name Address SWRST 0820H (Prohibit Software RMW) reset 0: don’t care 1: Reset SPI Mode SPIMD Setting LOOPBACK register 0821H LOOPBACK (Prohibit Test mode RMW) 0:disbale 1:enable communica 0822H tion control 0: disable 1: enable SPICT Control CRC16_7_B register CRC select...
Page 714 (9) SPIC (2/2) Symbol Name Address CRCD7 0826H SPICR CRCD15 register 0827H TXD7 0830H transmission SPITD0 data0 TXD15 register 0831H TXD7 0832H transmission SPITD1 data1 TXD15 register 0833H RXD7 0834H receive SPIRD0 data0 RXD15 register 0835H RXD7 0836H receive SPIRD1 data1 RXD15 register...
Page 715 (10) MMU (1/8) Symbol Name Address LOCALX register LOCALPX 0880H program LOCALX register LOCALX LOCALPX 0881H BANK program 0:disable 1:enable LOCALY register LOCALPY 0882H program LOCALY register LOCALPY 0883H LOCALY program BANK 0:disable 1:enable LOCALZ register LOCALPZ 0884H program LOCALZ register LOCALPZ 0885H...
Page 716 (10) MMU (2/8) Symbol Name Address LOCALX register LOCALLX 0888H Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.) LOCALX register LOCALX LOCALLX 0889H BANK 0:disable 1:enable LOCALY register LOCALLY 088AH LOCALY register LOCALLY 088BH LOCALY BANK 0:disable 1:enable...
Page 717 (10) MMU (3/8) Symbol Name Address LOCALX register LOCALRX 0890H read Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.) LOCALX register LOCALX LOCALRX 0891H BANK read 0:disable 1:enable LOCALY register LOCALRY 0892H read LOCALY register LOCALRY 0893H LOCALY...
Page 718 (10) MMU (4/8) Symbol Name Address LOCALX register LOCALWX 0898H write Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.) LOCALX register LOCALX LOCALWX 0899H BANK write 0:disable 1:enable LOCALY register LOCALWY 089AH write LOCALY register LOCALWY 089BH LOCALY...
Page 719 (10) MMU (5/8) Symbol Name Address LOCALX register 08A0H LOCALESX for DMA source Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.) LOCALX register LOCALX 08A1H LOCALESX for DMA BANK source 0:disable 1:enable LOCALY register 08A2H LOCALESY for DMA source...
Page 720 (10) MMU (6/8) Symbol Name Address LOCALX register 08A8H LOCALEDX for DMA destination Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.) LOCALX register LOCALX 08A9H LOCALEDX for DMA BANK destination 0:disable 1:enable LOCALY register 08AAH LOCALEDY for DMA destination...
Page 721 (10) MMU (7/8) Symbol Name Address LOCALX register 08B0H LOCALOSX for DMA source Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.) LOCALX register LOCALX 08B1H LOCALOSX for DMA BANK source 0:disable 1:enable LOCALY register 08B2H LOCALOSY for DMA source...
Page 722 (10) MMU (8/8) Symbol Name Address LOCALX register 08B8H LOCALODX for DMA destination Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.) LOCALX register 08B9H LOCALX LOCALODX for DMA BANK destination 0:disable 1:enable LOCALY register 08BAH LOCALODY for DMA destination...
Page 723 (11) NAND-Flash controller (1/4) Symbol Name Address 08C0H enable (Prohibit 0: Disable RMW) 1: Enable NANDF NDFMCR0 Control0 SPLW1 Register Strobe pulse width (Low width of 08C1H NDWE (Prohibit RMW) Inserted width = (f INTERDY Ready interrupt 08C2H NANDF 0: Disable NDFMCR1 Control1 1: Enable...
Page 724 (11) NAND-Flash controller (2/4) Symbol Name Address ECCD7 08C8H NANDF NDECCRD2 Code ECC ECCD15 Register2 08C9H ECCD7 08CAH NANDF NDECCRD3 Code ECC ECCD15 Register3 08CBH ECCD7 08CCH NANDF NDECCRD4 Code ECC ECCD15 Register4 08CDH ECCD6 ECCD5 ECCD4 NAND Flash ECC Register (7-0) ECCD14 ECCD13 ECCD12...
Page 725 (11) NAND-Flash controller (3/4) Symbol Name Address RS0A7 08D0H NANDF read solomon NDRSCA0 Result address Register0 08D1H RS0D7 NANDF read solomon NDRSCD0 08D2H Result data Register0 RS1A7 08D4H NANDF read solomon NDRSCA1 Result address Register1 08D5H RS1D7 NANDF read solomon NDRSCD1 08D6H Result data...
Page 726 (11) NAND-Flash controller (4/4) Symbol Name Address RS3A7 08DCH NANDF read solomon NDRSCA3 Result address Register3 08DDH NANDF RS2D7 read NDRSCD3 08DEH solomon Result data Register3 1FF0H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined NANDF Data NDFDTR0 Register0 1FF1H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 1FF2H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined...
Page 727 (12) DMAC (1/7) Symbol Name Address D0SA7 0900H D0SA15 source HDMAS0 0901H address Register0 D0SA23 0902H D0DA7 0904H D0DA15 destination HDMAD0 0905H address Register0 D0DA23 0906H D0CA7 0908H Transfer HDMACA0 count D0CA15 number A Register0 0909H D0CB7 090AH Transfer HDMACB0 count D0CB15 number B...
Page 728 (12) DMAC (2/7) Symbol Name Address D1SA7 0910H D1SA15 source HDMAS1 0911H address Register1 D1SA23 0912H D1DA7 0914H D1DA15 destination HDMAD1 0915H address Register1 D1DA23 0916H D1CA7 0918H Transfer HDMACA1 count D1CA15 number A Register1 0919H D1CB7 091AH Transfer HDMACB1 count D0CB15 number B...
Page 729 (12) DMAC (3/7) Symbol Name Address D2SA7 0920H D2SA15 source HDMAS2 0921H address Register2 D2SA23 0922H D2DA7 0924H D2DA15 destination HDMAD2 0925H address Register2 D2DA23 0926H D2CA7 0928H Transfer HDMACA2 count D2CA15 number A Register2 0929H D2CB7 092AH Transfer HDMACB2 count D2CB15 number B...
Page 730 (12) DMAC (4/7) Symbol Name Address D3SA7 0930H D3SA15 source HDMAS3 0931H address Register3 D3SA23 0932H D3DA7 0934H D3DA15 destination HDMAD3 0935H address Register3 D3DA23 0936H D3CA7 0938H Transfer HDMACA3 count D3CA15 number A Register3 0939H D3CB7 093AH Transfer HDMACB3 count D3CB15 number B...
Page 731 (12) DMAC (5/7) Symbol Name Address D4SA7 0940H D4SA15 source HDMAS4 0941H address Register4 D4SA23 0942H D4DA7 0944H D4DA15 destination HDMAD4 0945H address Register4 D4DA23 0946H D4CA7 0948H Transfer HDMACA4 count D4CA15 number A Register4 0949H D4CB7 094AH Transfer HDMACB4 count D4CB15 number B...
Page 732 (12) DMAC (6/7) Symbol Name Address D5SA7 0950H D5SA15 source HDMAS5 0951H address Register5 D5SA23 0952H D5DA7 0954H D5DA15 destination HDMAD5 0955H address Register5 D5DA23 0956H D5CA7 0958H Transfer HDMACA5 count D5CA15 number A Register5 0959H D5CB7 095AH Transfer HDMACB5 count D5CB15 number B...
Page 733 (12) DMAC (7/7) Symbol Name Address HDMAE enable 097EH Register DMATE HDMATR timer 097FH Timer Register operation 0: Disable 1: Enable DMAE5 DMAE4 DMAE3 DMA channel operation 0: Disable DMATR6 DMATR5 DMATR4 DMATR3 Maximum bus occupancy time setting The value to be set in <DMATR6:0> should be obtained by “Maximum bus occupancy time / (256/f “00H”...
Page 734 (13) Clock gear, PLL Symbol Name Address System clock SYSCR0 10E0H control register0 System clock SYSCR1 10E1H control register1 System clock Always SYSCR2 10E2H control write “0”. register2 PROTECT EMCCR0 control 10E3H Protect flag register0 0: OFF 1: ON EMCCR1 control 10E4H register1...
Page 735 (14) 8-bit timer (1/2) Symbol Name Address TA0RDE TMRA01 Double TA01RUN 1100H register buffer 0: Disable 1: Enable 1102H 8-bit timer TA0REG (Prohibit register 0 RMW) 1103H 8-bit timer TA1REG (Prohibit register 1 RMW) TA01M1 TMRA01 Operation mode TA01MOD MODE 1104H 00: 8-bit timer mode register...
Page 736 (14) 8-bit timer (1/2) Symbol Name Address TA4RDE TMRA45 Double TA45RUN 1110H register buffer 0: Disable 1: Enable 1112H 8-bit timer TA4REG (Prohibit register 4 RMW) 1113H 8-bit timer TA5REG (Prohibit register 5 RMW) TA45M1 TMRA45 Operation mode TA45MOD MODE 1114H 00: 8-bit timer mode register...
Page 737 (15) 16-bit timer (1/2) Symbol Name Address TB0RDE TMRB0 Double TB0RUN 1180H buffer register 0: disable 1: enable Always write “00”. TMRB0 1182H TB0MOD MODE (Prohibit register RMW) Always write “11”. TMRB0 1183H Flip-Flop TB0FFCR (Prohibit * Always read as “11”. control RMW) register...
Page 738 (15) 16-bit timer (2/2) Symbol Name Address TB1RDE TMRB1 Double TB1RUN 1190H buffer register 0: disable 1: enable Always write “00”. TMRB1 1192H TB1MOD MODE (Prohibit register RMW) Always write “11”. TMRB1 1193H Flip-Flop TB1FFCR (Prohibit * Always read as “11”. control RMW) register...
Page 739 (16) UART/Serial channels Symbol Name Address Serial 1200H channel 0 SC0BUF (Prohibit buffer RMW) register Undefined Serial 1201H channel 0 Received SC0CR (Prohibit control data bit8 RMW) register Serial Transfer channel 0 SC0MOD0 1202H data bit 8 mode 0 register Serial channel 0 Always...
Page 740 (17) SBI Symbol Name Address Serial bus 1240H interface SBICR1 (Prohibit Number of transfer bits control RMW) 000: 8 register 1 011: 3 110: 6 1241H buffer SBIDBR (Prohibit register RMW) I2C BUS 1242H I2CAR Address (Prohibit register RMW) Serial bus SBISR interface Master/...
Page 741 (18) AD converter (1/3) Symbol Name Address ADR01 conversion ADREG0L 12A0H result Store Lower 2 bits of register 0 low AN0 AD conversion ADR09 conversion ADREG0H 12A1H result register 0 high ADR11 conversion ADREG1L 12A2H result Store Lower 2 bits of register 1 low AN1 AD conversion ADR19...
Page 742 (18) AD converter (2/3) Symbol Name Address ADRSP1 High priority Conversion 12B0H ADREGSPL Register SP Store Lower 2 bits of an AD conversion result ADRSP9 High priority Conversion 12B1H ADREGSPH Register SP high ADR21 Conversion Result 12B4H ADCM0REGL Compare Store Lower 2 bits of an Criterion AD conversion result Register 0...
Page 743 (18) AD converter (3/3) Symbol Name Address Normal AD conversion AD mode end flag ADMOD0 control 12B8H 0:During register 0 conversion sequence or before starting 1:Complete conversion sequence DACON AD mode DAC and VREF ADMOD1 control 12B9H application control register 1 HEOS High-priority AD conversion...
Page 744 (19) Watchdog timer Symbol Name Address WDTE WDMOD mode 1300H control register 1: Enable 1301H WDCR control (Prohibit register RMW) WDTP1 WDTP0 Select detecting time 00: 2 01: 2 10: 2 11: 2 − − B1H: WDT disable code 4E: WDT clear code 92CZ26A-741 TMP92CZ26A −...
Page 745 (20) RTC (Real-Time Clock) Symbol Name Address Second SECR 1320H register “0” is read Minute MINR 1321H register “0” is read Hour HOURR 1322H register DAYR 1323H register Date DATER 1324H register 1325H PAGE0 Month MONTHR PAGE1 register 1326H PAGE0 80 years Year YEARR...
Page 746 (21) Melody/alarm generator Symbol Name Address Alarm- pattern 1330H register Melody/ Free run counter alarm MELALMC 1331H control control 00: Hold register 01: Restart 10: Clear 11: Clear and start Melody MELFL frequency 1332H L-register MELON Melody Melody counter MELFH 1333H frequency control...
Page 747 (22) I S (1/2) Symbol Name Address B015 B014 1800H Transmission I2S0BUF (Prohibit Buffer RMW) B031 B030 Register0 B115 B114 1810H Transmission I2S1BUF (Prohibit Buffer RMW) Register1 B131 B130 B013 B012 B011 B010 B009 B008 B007 Undefined Transmission buffer register (FIFO) 28 27 B028 B027...
Page 748 (22) I S (2/2) Symbol Name Address TXE0 Transmit 1808H 0: Stop 1: Start I2S0CTL Control CLKS0 Register0 Source 1809H clock 0: f 1: f CK07 180AH I2S0 Divider I2S0C Value Setting Register 180BH TXE1 Transmit 1818H 0: Stop 1: Start I2S1CTL Control CLKS1...
Page 749 (23) MAC (1/2) Symbol Name Address Data register MACMA_LL 1BE0H Multiplier A-LL MA15 Data register MACMA_LH 1BE1H Multiplier A-LH MA23 Data register MACMA_HL 1BE2H Multiplier A-HL MA31 Data register MACMA_HH 1BE3H Multiplier A-HH Data register MACMB_LL 1BE4H Multiplier B-LL MB15 Data register MACMB_LH...
Page 750 (23) MAC (2/2) Symbol Name Address OR39 Data register Multiply and 1BECH MACOR_HLL Accumulate -HLL OR47 Data register Multiply and 1BEDH MACOR_HLH Accumulate -HLH OR55 Data register Multiply and 1BEEH MACOR_HHL Accumulate -HHL OR63 Data register Multiply and 1BEFH MACOR_HHH Accumulate -HHH MOVF...
Page 751 TMP92CZ26A Package P-FBGA228-1515-0.80A5 TOP VIEW BOTTOM VIEW 92CZ26A-748...

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