Fujitsu FR Series Application Note
32-bit direct memory access
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- Application note (35 pages) ,
- Instruction manual (314 pages) ,
- Application note (29 pages)
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Summary of Contents for Fujitsu FR Series
- Page 1 Fujitsu Microelectronics Europe MCU-AN-300059-E-V11 Application Note FR FAMILY 32-BIT MICROCONTROLLER MB91460 DIRECT MEMORY ACCESS APPLICATION NOTE...
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Page 2: Revision History
DIRECT MEMORY ACCESS Revision History Revision History Date Issue 2008-04-22 First Version; MPi 2009-06-29 V1.1; MSt Completed chapter 2.4.3 DMA Transfer and Interrupts This document contains 29 pages. MCU-AN-300059-E-V11 - 2 - © Fujitsu Microelectronics Europe GmbH... -
Page 3: Warranty And Disclaimer
Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the customer’s use or the transport. -
Page 4: Table Of Contents
External Bus Request Arbitration (BRQ) ..........18 3 DMAC EXAMPLES ......................19 DMAC Example with External Bus................. 19 DMAC Example with UART ................... 25 4 ADDITIONAL INFORMATION ..................27 LIST OF FIGURES ......................28 MCU-AN-300059-E-V11 - 4 - © Fujitsu Microelectronics Europe GmbH... - Page 5 DIRECT MEMORY ACCESS Contents LIST OF TABLES ....................... 29 © Fujitsu Microelectronics Europe GmbH - 5 - MCU-AN-300059-E-V11...
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Page 6: Introduction
External input pin or built-in peripherals or software requests as DMAC transfer request sources • External Transfer requests available on DMAC channels 0 to 3 • DMA can be stopped by STOP request (supported by UART-Receive interrupt, in case of receive error) MCU-AN-300059-E-V11 - 6 - © Fujitsu Microelectronics Europe GmbH... -
Page 7: Direct Memory Access
Chapter 2 Direct Memory Access 2 Direct Memory Access THE BASIC FUNCTIONALITY OF THE DMAC 2.1 Block Diagram The below figure shows the block diagram of DMAC of FR Figure 2-1: Block Diagram of DMAC © Fujitsu Microelectronics Europe GmbH - 7 - MCU-AN-300059-E-V11... -
Page 8: Outline
End of DMA interrupts Application Application DMAC Interrupt Service Routine Application Figure 2-2: Single Transfer For a single transfer the DMA does not offer a real advantage against a standard interrupt. MCU-AN-300059-E-V11 - 8 - © Fujitsu Microelectronics Europe GmbH... -
Page 9: Multiple Transfers
DMA is engaged in the data transfer the CPU is either waiting for the DMA to finish the transfer or it is executing the code from the pre-fetch queue. © Fujitsu Microelectronics Europe GmbH - 9 -... -
Page 10: Registers
IS and EIS bits. Please refer the hardware manual for the transfer source selection. If all the bits of block size are 0, then the block size is 16 (times one transfer unit). MCU-AN-300059-E-V11 - 10 - © Fujitsu Microelectronics Europe GmbH... -
Page 11: Control/Status Registers B (Dmacb0-4)
EDIE End Interrupt Request disabled Enable Table 2-2: DMACBn Source and destination address register reload feature is only valid if the Transfer count register reload feature is enabled (DTCR = 1). © Fujitsu Microelectronics Europe GmbH - 11 - MCU-AN-300059-E-V11... -
Page 12: Transfer Source Address Setting Register (Dmasa0-4)
If one tries to read them while the ongoing transfer, the address before the transfer is read and if read after the transfer then the next access address is read. MCU-AN-300059-E-V11 - 12 - © Fujitsu Microelectronics Europe GmbH... -
Page 13: Dmac All-Channel Control Register (Dmacr)
Alternating priority (ch1 > ch0) DMAC operation on all channels 0,0,0,0 enabled DMAH3 … … DMA Halt 0,0,0,1 DMAC operation on all channels DMAH0 temporarily stopped 1,1,1,1 … Table 2-4: DMACR © Fujitsu Microelectronics Europe GmbH - 13 - MCU-AN-300059-E-V11... -
Page 14: Operation
7. Once the DTC[15:0] becomes 0, the transfer is stopped with DSS[1:0] of DMABA register gets set to B’11 indicating transfer ended normally. 8. If the reload is enabled then the DMAC waits for next transfer request. MCU-AN-300059-E-V11 - 14 - © Fujitsu Microelectronics Europe GmbH... -
Page 15: Burst Transfer
B’11 indicating transfer ended normally. 7. The peripheral interrupt, if any, which had initiated the transfer request, gets cleared by DMAC. 8. If the reload is enabled then the DMAC waits for next transfer request. © Fujitsu Microelectronics Europe GmbH - 15 - MCU-AN-300059-E-V11... -
Page 16: Transfer Type
In the meantime, the transfer request is retained internally. After the interrupt request is cleared, DMAC reissues a transfer request to the bus controller to acquire the right to use the bus and then restarts DMA transfer. MCU-AN-300059-E-V11 - 16 - © Fujitsu Microelectronics Europe GmbH... -
Page 17: External Transfer Requests
It should be noted that this pin shared with DEOP. The minimum width of the signal appearing at DEOTX pin should be 5 system clock cycles. Table 2-5: External Transfer Request © Fujitsu Microelectronics Europe GmbH - 17 - MCU-AN-300059-E-V11... -
Page 18: External Bus Request Arbitration (Brq)
Once BRQ is released the DMAC can use external bus. If the DMAC transfer through the external bus and BRQ is simultaneous then DMAC waits till the external device finishes transfer and then DMAC takes over. MCU-AN-300059-E-V11 - 18 - © Fujitsu Microelectronics Europe GmbH... -
Page 19: Dmac Examples
; Note: This feature is not supported by every device. Please check the data sheet. Following devices for example do not offer an external bus interface: MB91464A, MB91467C, MB91465K, MB91463N, MB91465X. ;======================================================================================= © Fujitsu Microelectronics Europe GmbH - 19 - MCU-AN-300059-E-V11... - Page 20 ; used (not set to ON in "Select Chip select") need not be set (setting ignored). ; NOTE: Just the upper 16-bit of the start address must be set, e.g. when using start ; address 0x00080000 set 0x0008. MCU-AN-300059-E-V11 - 20 - © Fujitsu Microelectronics Europe GmbH...
- Page 21 |||||||___________ BST1 bit ||||||____________ DBW0 bit, DBWx select data bus width |||||_____________ DBW1 bit ||||______________ ASZ0 bit, ASZx bits select address size of CS |||_______________ ASZ1 bit ||________________ ASZ2 bit |_________________ ASZ3 bit © Fujitsu Microelectronics Europe GmbH - 21 - MCU-AN-300059-E-V11...
- Page 22 DIRECT MEMORY ACCESS Chapter 3 DMAC Examples Main.c /* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ /* ELIGIBILITY FOR ANY PURPOSES.
- Page 23 // set err variable break; (1 == err) PDR16 = 0xAA; // Glow alternate LEDs connected at // Port16 to indicate error else PDR16 = 0xFF; // Glow all LEDs connected at Port16 © Fujitsu Microelectronics Europe GmbH - 23 - MCU-AN-300059-E-V11...
- Page 24 Please note, that the corresponding interrupt vector and level has to be defined in the vectors.c module of our standard template project. /* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ /* ELIGIBILITY FOR ANY PURPOSES.
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Page 25: Dmac Example With Uart
0xFF output to port 16. Main.c /* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ /* ELIGIBILITY FOR ANY PURPOSES. - Page 26 Please note, that the corresponding interrupt vector and level has to be defined in the vectors.c module of our standard template project. /* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ /* ELIGIBILITY FOR ANY PURPOSES.
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Page 27: Additional Information
DIRECT MEMORY ACCESS Chapter 4 Additional Information 4 Additional Information Information about FUJITSU Microcontrollers can be found on the following Internet page: http://mcu.emea.fujitsu.com/ The software examples related to this application note is: 91460_dma_uart0 91460_dma_extbus It can be found on the following Internet page: http://mcu.emea.fujitsu.com/mcu_product/mcu_all_software.htm... -
Page 28: List Of Figures
List of Figures List of Figures Figure 2-1: Block Diagram of DMAC ..................7 Figure 2-2: Single Transfer ....................8 Figure 2-3: Multiple Transfers ....................9 Figure 3-1: Setup ROM/RAM Area ..................19 MCU-AN-300059-E-V11 - 28 - © Fujitsu Microelectronics Europe GmbH... - Page 29 List of Tables List of Tables Table 2-1: DMACAn ....................... 10 Table 2-2: DMACBn ....................... 11 Table 2-3: DMACBn-II ......................12 Table 2-4: DMACR ......................... 13 Table 2-5: External Transfer Request .................. 17 © Fujitsu Microelectronics Europe GmbH - 29 - MCU-AN-300059-E-V11...