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Hitachi HD64411 Q2 User Manual
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Hitachi HD64411 Q2 User Manual

Hitachi HD64411 Q2 User Manual

Quick 2d graphics renderer
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HD64411 Q2
Quick 2D Graphics Renderer
User's Manual
SuperH RISC engine Peripheral LSI
ADE-602-120
Rev. 1.0
7/9/99
Hitachi, Ltd.

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Summary of Contents for Hitachi HD64411 Q2

  • Page 1 HD64411 Q2 Quick 2D Graphics Renderer User’s Manual SuperH RISC engine Peripheral LSI ADE-602-120 Rev. 1.0 7/9/99 Hitachi, Ltd.
  • Page 2 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document.
  • Page 3 The demand has thus arisen for a chip set combining a microcomputer with a rendering and display LSI. In response to this demand, Hitachi has developed the Q Series of graphics accelerators, offering high-speed rendering and display processing in a chip set that includes a SuperH family microcomputer.

  • Page 4: Table Of Contents

    Contents Section 1 Overview of Q2 (Quick 2D Graphics Renderer) ....... Q2 Overview....................Block Diagram....................Concepts ......................1.3.1 Simplicity (Optimization of System Configuration) ........1.3.2 Realtime Operation................1.3.3 Upgradability..................Summary of Functions..................Section 2 Pins ....................11 Pin Arrangement and Functions ................11 2.1.1 Overview of Pins ..................
  • Page 5 3.3.3 Color Data Formats................40 3.3.4 Display Functions................. 47 Initial States ....................56 3.4.1 Initial States ..................56 Reset State (when RESET is Driven Low)..........56 3.4.2 Section 4 Display List ..................59 Overview......................59 Command Fetching..................62 Basic Functions....................63 4.3.1 Rendering Coordinate Systems ..............
  • Page 6 5.3.2 Status Register (SR)................131 5.3.3 Status Register Clear Register (SRCR) ............. 134 5.3.4 Interrupt Enable Register (IER)..............135 5.3.5 Memory Mode Register (MEMR)............. 137 5.3.6 Display Mode Register (DSMR) .............. 138 5.3.7 Rendering Mode Register (REMR) ............142 5.3.8 Input Data Conversion Mode Register (IEMR)..........
  • Page 7 6.11 Note on Changing TV Synchronization Mode ............170 6.12 Note on POLYGON4A Source Reference Location..........171 Section 7 Electrical Characteristics ..............173 Absolute Maximum Ratings................173 Recommended Operating Conditions..............174 7.2.1 Recommended Operating Conditions............174 Electrical Characteristics Test Methods..............175 7.3.1 Timing Testing ..................

  • Page 8: Overview Of Q2 (Quick 2D Graphics Renderer)

    Section 1 Overview of Q2 (Quick 2D Graphics Renderer) 1 . 1 Q2 Overview The Q2 (Quick 2D Graphics Renderer) has been developed as the first product in the SuperH RISC engine graphics accelerator “Quick” series (Q series). The Q2 is a 2D graphics renderer LSI for minimum system configuration use, based on the concepts of simplicity, realtime operation, and upgradability.

  • Page 9: Block Diagram

    Quick 2D graphics renderer CLK0 CLK0 CLKi CPG0 CPG1 DCLK SYNC Display unit R: 6 Rendering unit RGB >> YCrCb G: 6 B: 6 Display buffer Rendering unit Address buffer unit Color palette control NTSC (22) 16 bits SuperH ∆YUV>>RGB (YCrCb: 8, 8/8 bits) Chip Digital video...
  • Page 10 • Display buffer unit Reads data to be displayed on the CRT from the display-side frame buffer, and outputs the display data in accordance with the display timing. • Color palette (6 bits per color, 64 gradation settings) When using 8 bits/pixel, performs conversion to display data of 256 colors out of 262,144, based on the color conversion table.

  • Page 11: Concepts

    1 . 3 Concepts 1 . 3 . 1 Simplicity (Optimization of System Configuration) Use of Unified Graphics Memory Architecture • Unified handling of image data (unified graphics memory (UGM) architecture) Data in various formats can be stored and managed in the same unified graphics memory (figure 1-3).

  • Page 12: Realtime Operation

    UGM (Unified Graphics Memory) Frame buffer 0 Frame buffer 1 Binary/multi-valued Binary work area source Display list The SuperH can access the UGM directly via the Q2 Figure 1-4 Unified System Bus Interface (UGM Directly Accessible by SuperH via Q2) 1 .

  • Page 13: Upgradability

    Drawing buffer Display buffer Double-buffer control Figure 1-5 Double-Buffering Architecture Support for EDO Page Mode DRAM: EDO page mode DRAM can be used for the UGM. This enables the Q2 to use burst access to the UGM and perform high-speed drawing. Use of Write-Only Drawing: Write-only drawing (a drawing method using only write operations) is used to improve drawing performance.
  • Page 14 Data base (coordinate vertices, etc.) 3-D algorithm (software) Drawing by Q2 Display list Drawn graphic Figure 1-6 Data Flow when Using a 3D Algorithm Drawing System Upgrading: The Q2 is available as a series—the Q Series—in the same way as the SuperH, enabling the user to select the most appropriate Q2 and SuperH models for his application.

  • Page 15: Summary Of Functions

    1 . 4 Summary of Functions Table 1-1 summarizes the functions of the Q2. Table 1-1 Summary of Q2 Functions I t e m Function/Performance Multiplication on: 33 MHz × 1, 16.5 MHz × Maximum Drawing system internal 2, 8.25 MHz × 4 clock operation (operating clock) frequency...
  • Page 16 Table 1-1 Summary of Q2 Functions (cont) I t e m Function/Performance Interface Command/data Performed by DMA transfer (single address) or by transfer SuperH YUV → RGB 16-bit input, 4:2:2 (8 bits each for Y, U, V) conversion 16-bit output (R: 5, G: 6, B: 5 bits) ∆YUV →...

  • Page 18: Section 2 Pins

    Section 2 Pins 2 . 1 Pin Arrangement and Functions 2 . 1 . 1 Overview of Pins Figure 2 shows an overview of the Q2’s pins. MODE0–2 DD0–DD17 CLK0 DCLK CSYNC CLK1 System control RESET FCLK HSYNC/EXHSYNC Display interface CAP0 VSYNC/EXVSYNC TEST...

  • Page 19: Pin Arrangement

    2 . 1 . 2 Pin Arrangement Figure 2-2 shows the pin arrangement of the Q2. DREQ FCLK VCC5 CLK1 CPUVCC1 GND8 MA11 CPUGND1 MA10 GND7 CPUGND2 VCC4 CPUVCC2 HD64411 CPUGND3 GND6 MUCAS (FP-144) MLCAS MRAS1 PLLGND MRAS0 CAP0 PLLVCC MD15 VCC3 MD14...

  • Page 20: Pin Functions

    2 . 1 . 3 Pin Functions Table 2-1 summarizes the functions of the Q2’s pins. Table 2-1 Pin Functions T y p e Symbol No. I / O Function N o t e s System MODE0 Input Operating mode pin 0 5 V input specification control MODE1...
  • Page 21 Table 2-1 Pin Functions (cont) T y p e Symbol No. I / O Function N o t e s Input CPU address 20 3V/5V-CPU I/F interface A21 Input CPU address 21 3V/5V-CPU I/F Input CPU address 22 3V/5V-CPU I/F Input/output CPU data 0 3V/5V-CPU I/F Input/output CPU data 1...
  • Page 22 Table 2-1 Pin Functions (cont) T y p e Symbol No. I / O Function N o t e s Display Output Display data output 0 5 V output specification interface DD1 Output Display data output 1 5 V output specification Output Display data output 2 5 V output specification...
  • Page 23 Table 2-1 Pin Functions (cont) T y p e Symbol Pin No. I / O Function N o t e s Output Memory address 0 5 V output specification interface MA1 Output Memory address 1 5 V output specification Output Memory address 2 5 V output specification Output...
  • Page 24 Table 2-1 Pin Functions (cont) T y p e Symbol Pin No. I / O Function N o t e s MD11 Input/output Memory data 11 5 V input/output specification interface MD12 Input/output Memory data 12 5 V input/output specification MD13 Input/output Memory data 13 5 V input/output specification...
  • Page 25 Table 2-1 Pin Functions (cont) T y p e Symbol No. I / O Function N o t e s Power GND1 Ground Buffer VSS supply GND3 Ground Buffer VSS GND5 Ground Buffer VSS GND6 Ground Buffer VSS GND8 Ground Buffer VSS GND9 Ground...

  • Page 26: Operating Mode Pins

    2 . 2 Operating Mode Pins These pins determine the Q2’s operating mode. The mode is fixed in a reset-startup. 1. MODE2 = L, MODE1 = L, MODE0 = L Normal operation state. Multiplication on. The external clock is duty-free. The internal operating clock has the same frequency as the external input clock.

  • Page 27: Cpu Interface Pins

    CK pin and the frequency of the clock input to the CLK0 pin. For examples of software wait specification, see the HD64411 Q2 Application Note. When an SH704X is used, a setting must be made to extend the CS assertion period. Byte access to registers...

  • Page 28: Cpu Reads

    2 . 3 . 2 CPU Reads A read operation is basically the same as a write operation. Reads are performed in word units. 2 . 3 . 3 DMA Writes The DMA controller can perform display list, binary source, and delta YUV data transfers using cycle stealing.

  • Page 29: Power Supply Pins

    2 . 4 Power Supply Pins 2 . 4 . 1 Normal Power Supply and PLL Power Supply The normal power supply and PLL power supply are connected to 5 V. CAP0 is the external capacitance pin for the multiplication circuit. Connect the specified capacitance to this pin (figure 2-3).

  • Page 30: Video Encoder Interface

    The Q2 allows EDO page mode DRAM to be used as the UGM. EDO page mode DRAMs can be used with the Q2 are the Hitachi HM51 (S) 4265 Series (4-Mbit capacity, 5 V supply voltage, 256k × 16 memory configuration), the Hitachi HM5118165 Series (16-Mbit capacity, 5 V supply voltage, 1 M ×...

  • Page 32: Unified Graphics Memory (Ugm) Display Functions

    Section 3 Unified Graphics Memory (UGM) Display Functions 3 . 1 Clocks There are two Q2 clocks, CLK0 and CLK1. The clock used as the base for the operating clock is input at the CLK0 pin, and the clock used as the base for the display dot clock (DCLK) is input at the CLK1 pin.

  • Page 33: Ugm (Unified Graphics Memory) Control

    The operating clock and display dot clock frequencies can be set to any values within the following range: (1) Operating clock frequency ≥ 2 × display dot clock frequency (2) Operating clock frequency = 2 × display dot clock frequency and the operating clock and display dot clock are synchronized Drawing operations can therefore be performed at maximum speed without being influenced by the characteristics of the display device.

  • Page 34: Memory Access

    Frame buffer 0 Frame buffer 1 Source patterns Display list Typical uses of UGM 4 GB CPU memory space Figure 3-2 Example of UGM Mapping onto CPU Memory Space 3 . 2 . 2 Memory Access The priority order for control of UGM access is as follows: 1.

  • Page 35: Memory Map

    performing the access. If this is not done, the Q2 will output waits continuously when the CPU accesses the UGM. • Access by software In access by software, the UGM is accessed as part of the main memory. In a write operation, no-wait access is possible if there is empty space in the Q2’s built-in 32- byte FIFO buffer.
  • Page 36 1 word H'00 H'00 H'00 H'01 H'FF H'FF H'FF .... Bit 0 Bit 1 Bit F Bit 0 Bit 0 Bit 1 Bit F 4096 bits Figure 3-3 Configuration of One Memory Unit (512 Bytes) (1) • 8 bits/pixel (multi-valued source, multi-valued destination) ..
  • Page 37 8 bits 32 dots 255 319 16 dots Multi-valued source area Work area Display list, binary source area Physical address Multi-valued source start address F0 start address F1 start address 20000H Work area start address 40000H Display list start address 44000H (F0, F1: Frame buffers) Display data...
  • Page 38 1023 Multi-valued source area Work area Display list, binary source area Physical address Multi-valued source start address F0 start address F1 start address 40000H Work area start address 80000H Display list start address 88000H (F0, F1: Frame buffers) Display data Work area (exclusive use of 32 lines) Multi-valued source/binary source/ display list selection...
  • Page 39 1023 Multi-valued source area Work area 1024 1088 Display list, binary source area Physical address Multi-valued source start address F0 start address F1 start address 80000H Work area start address 100000H Display list start address 110000H (F0, F1: Frame buffers) Display data Work area (exclusive use of 64 lines) Multi-valued source/binary source/...
  • Page 40 16 dots 16 bits 255 319 16 dots Multi-valued source area Single rendering buffer mode F0/(F1) Work area Display list, binary source area Physical address Source start address F0 start address (F1 start address Work area start address 40000H Display list start address 44000H 1023 255 319...
  • Page 41 1023 Multi-valued source area Work area 1024 1056 Display list, binary source area Physical address Source start address F0 start address F1 start address 100000H Work area start address 200000H Display list start address 210000H Display data Work area (exclusive use of 32 lines) Multi-valued source/binary source/ display list selection Display data/multi-valued source/...

  • Page 42: Display And Display Control

    3 . 3 Display and Display Control 3 . 3 . 1 Overview The Q2 has two screens, a drawing screen and a display screen, managed by means of rendering coordinates. Display is performed for both these screens in accordance with double-buffering control designated by the user.
  • Page 43 Auto Display Change Mode: In auto display change mode, display frame switching has priority. If drawing is in progress when the frame is switched, drawing is aborted midway through that display list. It is therefore essential for drawing to be finished before the arrival of a VSYNC synchronization pulse.
  • Page 44 Figure 3-10 Operation in Auto Rendering Mode...
  • Page 45 Manual Display Change Mode: In manual display change mode, display frame switching and the start of drawing are controlled by software. Display switching can be performed either by performing FB0/FB1 switching with an SYSR DC bit setting by software, or by setting the start address of FB0 or FB1 in the display start address register indicated by DBF in SR.
  • Page 46 Figure 3-11 Operation in Manual Display Change Mode...

  • Page 47: Color Data Formats

    3 . 3 . 3 Color Data Formats Input Color Data Configurations: Input color data configurations are shown below. 1. 16-bit data D15 to D0 1 word 2. 1-bit/pixel data D15 to D0 15 14 Pixel no. 1 word Note: The pixel number runs from 0 upward from the left to right side of the screen. 3.
  • Page 48 6. YUV data YUV data uses a 4:2:2 format. The U and V data is horizontally reduced data. D15 to D0 Image data (1st word) D15 to D0 Image data (2nd word) D15 to D0 Data flow Image data (3rd word) D15 to D0 Image data (4th word) D15 to D0...
  • Page 49 D15 to D0 Initial value (1st word) 1 word D15 to D0 Initial value (2nd word) 1 word D15 to D0 12 11 Data flow ∆U0 ∆Y0 ∆V0 ∆Y1 Image data (3rd word) 1 word D15 to D0 12 11 ∆U2 ∆Y2 ∆V2...
  • Page 50 Configurations of Data in UGM: The UGM data configuration is shown below. 1. 16-bit data D15 to D0 1 word 2. 1-bit/pixel data D15 to D0 15 14 Pixel no. 1 word Note: The pixel number runs from 0 upward from the left to right side of the screen. 3.
  • Page 51 1. RGB data a. When the frame buffer is 16 bits/pixel and a color palette is not used DD17 to DD0 12 11 R (5 bits) G (6 bits) B (5 bits) LSB MSB 18 bits b. When the frame buffer is 8 bits/pixel and a color palette is used DD17 to DD0 12 11 R (6 bits)
  • Page 52 DD17 to DD0 1716 Image data (1st word) Y0 (8 bits) Cb0 (8 bits) 18 bits CSEL DD17 to DD0 1716 Image data (2nd word) Y1 (8 bits) Cr0 (8 bits) Data flow 18 bits CSEL DD17 to DD0 1716 Image data (3rd word) Y2 (8 bits) Cb2 (8 bits)

  • Page 53: Display Functions

    Memory width (512 or 1024 dots) is specified by the MWX bit in the rendering mode register UGM source area Main memory Q2 internal registers Start address (ISAR) (a) ISAR: Image data transfer start ∆YUV or X size (IDSRX) address YUV data (b) IDSRX, Y: Image data size Y size...
  • Page 54 The display control registers settings depend on the scanning and synchronization systems used. The calculations shown in table 3-2 should therefore be carried out before making the display parameter register settings. Figure 3-14 shows the display timing. The display screen is defined by the variables shown in table 3-3.
  • Page 55 Table 3-2 Register Settings* Operating Mode Register N o . (Address) Register Name Bit Names Master Mode TV Sync Mode Display size register X (DSRX) xw-1 xw-1* Display size register Y (DSRY) yw-1 yw-1 Display Horizontal display hsw+xs-3 hsw+xs-8* windows start position register (DSWR-HDS) Horizontal display...
  • Page 56 CLK1 EXHSYNC DCLK (×1) hsw + xs DD17 to DD0 DCLK (×1/2 [A]) hsw + xs DD17 to DD0 DCLK (×1/2 [B]) hsw + xs DD17 to DD0 3. The setting for the lower limit of the HDS bits is: when CLKi = 2 × DCLK, HDS ≥ 64 × (DCLK/CLKi);...
  • Page 57 Screen Display: In the Q2, the DEN (display enable) bit in the system control register (SYSR) can be used to select whether or not display data is to be output to the screen. When display data is not output, the display off output register (DOOR) settings are displayed. The frame flag (FRM) and vertical blanking flag (VBK) in the status register indicate the position of the fall of the vertical sync signal (VSYNC) determined by the set value (VSP9–0) in the vertical sync position register (VSPR) regardless of the synchronization method.
  • Page 58 Non-interlace mode Interlace mode Raster scanned in odd field Raster scanned in even field Interlace sync & video mode Figure 3-15 Examples of Raster Scan Control Display...
  • Page 59 Synchronization Systems: The Q2 is provided with a TV sync function in addition to master mode to simplify synchronization with an external device. The TVM (TV sync mode) bits in the display register (DSMR) are used to select master mode or TV sync mode.
  • Page 60 TV (sync signal generator): master Clock HSYNC VSYNC (4FSC) Field signal Data Display MIXER EXHSYNC EXVSYNC CLK1 ODDF DCLK Q2: slave FCLK (FSC) SuperH Figure 3-16 Signal Flow in TV Sync Mode • Synchronization System Switching Mode This mode is used to switch to master mode if the external sync signal generator malfunctions during operation in TV sync mode.
  • Page 61 Table 3-4 Estimated Number of Refresh Cycles (for 1/60s Field) Sample Display Number of Refresh Cycles (Per Raster) 4 Mbit × 1 4 Mbit × 2 16 Mbit × 1 16 Mbit × 2 Screen Sizes Memory Size 320 × 240 —...
  • Page 62 Figure 3-17 Display Timing...

  • Page 63: Initial States

    3 . 4 Initial States 3 . 4 . 1 Initial States Initial states are undefined. Registers: undefined I/O pins: undefined Output pins: low/high output Reset State (when RESE T is Driven Low) 3 . 4 . 2 Registers: After a reset, the Q2’s internal registers are initialized as shown in table 3-5.
  • Page 64 Table 3-5 Initial Register Values after Reset...
  • Page 65 Pins: Table 3-6 shows the Q2 pin states after a reset. Table 3-6 Pin States After Reset D0–D15, VSYNC /EXVSYNC , I/O pins Input state HSYNC/EXHSYNC, ODDF Output state (low-level output) MD0–MD15 Output pins Low-level output DISP, CDE, DD0–DD17 DREQ , IRL , WAIT High-level output CSYNC, DCLK, FCLK, MA0–MA11, MWE, Low/high-level output...

  • Page 66: Display List

    Section 4 Display List 4 . 1 Overview The Q2 performs drawing on the basis of a group of drawing commands located in the UGM. This group of drawing commands is called a display list. Drawing commands comprise four-vertex surface drawing and line drawing commands which draw at rendering coordinates, and work surface drawing and work line drawing commands which draw at work coordinates.
  • Page 67 Table 4-1 Drawing Commands T y p e Command Name Function Four-vertex POLYGON4 Draws quadrilateral with four coordinates as apexes. surface drawing Quadrilateral paint Painting can be performed with source tiling and specified color POLYGON4A Four-vertex surface drawing with multi-valued source as transfer source POLYGON4B Four-vertex surface drawing with binary source as...
  • Page 68 Table 4-1 Drawing Commands (cont) T y p e Command Name Function Register setting MOVE Current pointer setting (absolute coordinate specification) RMOVE Current pointer setting (relative coordinate specification) LCOFS Local offset value setting (absolute coordinate specification) RLCOFS Local offset value setting (relative coordinate specification) SCLIP Sets rectangle with diagonal designated by origin and...

  • Page 69: Command Fetching

     Work coordinates (2-dimensional coordinate system) These are the coordinates for managing graphics used when rendering attribute work specification is performed. Work coordinates are managed by the Q2 so that there is a 1-to-1 correspondence for each rendering coordinate pixel. Clipping processing is also handled in the same way as for rendering coordinates.

  • Page 70: Basic Functions

    DLSAR Command sequence 1 JUMP Command sequence 2 Subroutine GOSUB (Subroutine depth is limited to one level) TRAP Figure 4-1 Display List Example 4 . 3 Basic Functions 4 . 3 . 1 Rendering Coordinate Systems The Q2 controls three 2-dimensional coordinate systems, for rendering coordinates, 8-bit/pixel or 16-bit/pixel (multi-valued) source coordinates, and work coordinates, and one 1-dimensional coordinate system, for 1-bit/pixel (binary) source coordinates.
  • Page 71 –1024 –1024 Minimum installation Maximum installation 1023 1023 Figure 4-2 Rendering Coordinates Multi-Valued Source Coordinates: The coordinate origin is specified by the multi-valued source area start address. The maximum coordinate system size is represented by 1024 × 1024 positive coordinates, as shown in figure 4-3, but the size depends on the installed memory capacity, screen size, and multi-valued source area start address.
  • Page 72 Binary Source Coordinates: The binary (1-bit/pixel) source coordinate system is mapped directly onto 1-dimensional memory space. Any area and location can be used, and this coordinate system can overlap display list space. However, the start address of a source figure is always a word address.
  • Page 73 –1024 –1024 Minimum installation Maximum installation 1023 1023 Figure 4-5 Work Coordinate System Relationship between Binary Work Coordinates and Addresses: Work coordinates are liner coordinates that start from the work area start address. Work coordinates comprise 2- dimensional coordinates reflected at each pixel (512 or 1024 pixels) specified by the MWX bit in the rendering mode register (REMR).

  • Page 74: Rendering Reference Data

    16 bits 16 bits 16 bits .... H'40000 H'40001 H'4001F ..H'40020 H'40021 H'4003F 1 line ..H'400EF H'400E1 H'400FF Equivalent to 32 work coordinate lines ..H'43FEF H'43FE1 H'43FFF Figure 4-7 Relationship between Binary Work Coordinates and Addresses 4 .
  • Page 75 Applicable Rendering result Source rendering area command POLYGON4A Transparent mode Multi-valued source data POLYGON4B Specified color data Transparent mode COLOR0 COLOR1 Transparent mode POLYGON4B COLOR1 Binary source data COLOR POLYGON4C Figure 4-8 Example of POLYGON4 Transfer Data Combinations Multi-Valued Source Data: Multi-valued source data is defined as multi-valued source coordinates (2-dimensional coordinates).
  • Page 76 Case where LH ← 8-bit data Figure 4-9 Multi-Valued Source Data Configuration Binary Source Data: Binary source data is arranged in linear fashion in the binary source area in the UGM, and is managed as 2-dimensional coordinates (binary source coordinates) by TDX and TDY in the POLYGON4B command.

  • Page 77: Rendering Attributes

    Binary Work Data: Binary work data is defined as binary work coordinates (2-dimensional coordinates). Work data is used to implement polygon painting. Polygon outline data is created with the FTRAP command, etc. and the created figure data is used to delineate the rendering figure. For example, if the POLYGON4C command is used jointly for work, the work area polygon can be drawn in the rendering area with the specified color value.
  • Page 78 Work Specification (WORK): When drawing is performed at rendering coordinates with POLYGON4 commands, the WORK bit can be used to select, on an individual drawing command basis, whether or not binary work data is to be referenced. When binary work data referencing is selected, drawing is performed if the work data for the pixel corresponding to the rendering coordinates is 1, but not if the work data is 0.
  • Page 79 CLIP bit = 1 (0, 0) CLIP bit = 0 System clipping area Designated user clipping area (359,239) Figure 4-13 Example of Clipping Specification Transparency Specification (TRNS): When color expansion of binary source data is performed, transparency or non-transparency can be selected on an individual drawing command basis with the TRNS bit.
  • Page 80 No style specification (STYL = 0) Enlarged by factor of 2 Style specification used (STYL = 1) Referenced twice Source data Drawing data Figure 4-14 Example of Source Style Specification Net Drawing Specification (NET): The NET bit can be used to select, on an individual drawing command basis, whether or not net drawing is to be performed.
  • Page 81 Even-number referencing with half drawing specification (HALF = 1, EOS = 0) Odd-number referencing with half drawing specification (HALF = 1, EOS = 1) Source data Drawing data Starting point Figure 4-15 Examples of Even/Odd Select Specifications...

  • Page 82: Drawing Commands

    4 . 4 Drawing Commands 4 . 4 . 1 POLYGON4A Function Performs any four-vertex drawing while referencing a multi-valued (8- or 16-bit/pixel) source. Command Format CODE DRAW MODE Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension : Fixed at 0...
  • Page 83 Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work × ∆ × × Draw Mode TRNS STYL CLIP Reserved HALF WORK Reserved Reserved × Fixed at Fixed at Fixed at Fixed at O : Can be used ∆...
  • Page 84 Example (TXS, TYS) (DX1, DY1) (DX2, DY2) No work specification (DX3, DY3) (DX4, DY4) Multi-valued source coordinates Rendering coordinates Work specification provided (DX1, DY1) (DX1, DY1) (DX2, DY2) (DX2, DY2) (DX3, DY3) (DX3, DY3) (DX4, DY4) (DX4, DY4) Work coordinates Rendering coordinates...

  • Page 85: Polygon4B

    4 . 4 . 2 POLYGON4B Function Performs any four-vertex drawing while referencing a binary (1-bit/pixel) source. Command Format CODE DRAW MODE SOURCE ADDRESS H SOURCE ADDRESS L Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension COLOR 0...
  • Page 86 Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work × ∆ × × Draw Mode TRNS STYL CLIP Reserved HALF WORK Reserved Reserved ◊ ◊ Fixed at Fixed at Fixed at Fixed at O : Can be used ∆...
  • Page 87 SOURCE ADDRESS (DX1, DY1) COLOR 0 (DX2, DY2) COLOR 1 Non-transparent (DX4, DY4) mode (TRNS = 0) (DX3, DY3) Rendering coordinates Transparent mode Binary source (TRNS = 1) coordinates (DX1, DY1) (DX2, DY2) COLOR 1 Binary source 0 data is transparent. (DX4, DY4) (DX3, DY3) Rendering coordinates...

  • Page 88: Polygon4C

    4 . 4 . 3 POLYGON4C Function Performs any four-vertex drawing with a monochrome specification. Command Format CODE DRAW MODE Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension COLOR 1. Code B'00010 2.
  • Page 89 3. Command Parameters DXn, DYn (n = 1 to 4): Rendering coordinates, work coordinates COLOR: 8 or 16-bit/pixel color specification Description Draws any quadrilateral in the rendering area in the single color specified by the COLOR parameter. When work referencing is selected as a rendering attribute (WORK = 1), transfer is performed while referencing work area data for the same coordinates as the rendering coordinates.

  • Page 90: Ftrap

    4 . 4 . 4 FTRAP Command Format CODE DRAW MODE Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension 1. Code B'01000 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color...
  • Page 91 Description Draws a polygon with n-1 vertices at work coordinates. The polygon is drawn by sequentially painting trapezoids, using binary EOR, with line segments (DX1, DY1) – (DX2, DY2), (DX2, DY2) – (DX3, DY3), ..., (DXn, DYn) – (DX1, DY1) specified by the parameters as the right-hand side, with X = DXL as the left-hand side, and with top and bottom bases parallel to the X-axis.

  • Page 92: Rftrap

    4 . 4 . 5 RFTRAP Command Format CODE DRAW MODE Sign extension 1. Code B'01001 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work × × × × × Draw Mode Reserved CLIP Reserved...
  • Page 93 Description Paints n trapezoids with X = DXL as the side, and line segments (XC, YC) – (XC + DX1, YC + DY1), (XC + DX1, YC + DY1) – (XC + DX1 + DX2, YC + DY1 + DY2), ..., (XC + ... + DXn –...

  • Page 94: Linew

    4 . 4 . 6 LINEW Command Format CODE DRAW MODE Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension 1. Code B'01010 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work...
  • Page 95 Description Performs binary drawing at work coordinates of a polygonal line from vertex 1 (DX1, DY1), through vertex 2 (DX2, DY2), .., vertex n – 1 (DXn – 1, DYn – 1), to vertex n (DXn, DYn). 0 drawing or 1 drawing is selected with the drawing mode EOS bit. Drawing is performed at work coordinates with 0 when EOS = 0, and at work coordinates with 1 when EOS = 1.

  • Page 96: Rlinew

    4 . 4 . 7 RLINEW Command Format CODE DRAW MODE 1. Code B'01011 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work × × × ∇ × Draw Mode Reserved CLIP Reserved Reserved Fixed at...
  • Page 97 Description Performs binary drawing at work coordinates of a polygonal line comprising line segments (XC, YC) – (XC + DX1, YC + DY1), (XC + DX1, YC + DY1) – (XC + DX1 + DX2, YC + DY1 + DY2), ..., (XC + ... + DXn – 1, YC + ... + DYn – 1) – (XC + ... + DXn –1 + DXn, YC + ... + DYn –...

  • Page 98: Line

    4 . 4 . 8 LINE Command Format CODE DRAW MODE LINE COLOR Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension 1. Code B'01100 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color...
  • Page 99 3. Command Parameters LINE COLOR0: 8 or 16-bit/pixel color specification n (n = 2 to 65,535): Number of vertices DXn (n = 2 to 65,535): Absolute coordinate DYn (n = 2 to 65,535): Absolute coordinate Description Draws a polygonal line from vertex 1 (DX1, DY1), through vertex 2 (DX2, DY2), .., vertex n – 1 (DXn –...

  • Page 100: Rline

    4 . 4 . 9 RLINE Command Format CODE DRAW MODE LINE COLOR 1. Code B'01101 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work × × × × Draw Mode Reserved CLIP Reserved Reserved...
  • Page 101 Description Draws a polygonal line comprising line segments (XC, YC) – (XC + DX1, YC + DY1), (XC + DX1, YC + DY1) – (XC + DX1 + DX2, YC + DY1 + DY2), ..., (XC + ... + DXn – 1, YC + ... + DYn –...

  • Page 102: 4 . 4 . 1 0 Pline

    4 . 4 . 1 0 PLINE Function Draws a polygonal line at rendering coordinates while referencing a binary source. Command Format CODE DRAW MODE LINE COLOR 0 LINE COLOR 1 SOURCE ADDRESS H SOURCE ADDRESS L Sign extension Sign extension Sign extension Sign extension Sign extension...
  • Page 103 Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work × × × × Draw Mode TRNS CLIP Reserved Reserved Reserved Reserved Fixed at Fixed at Fixed at Fixed at Fixed at Fixed at Fixed at O : Can be used ×...
  • Page 104 Example n = 3 (0, 0) 1100 1100 1100 1100 SOURCE ADDRESS (DX2, DY2) (DX3, DY3) (DX1, DY1) TRNS = 1 and STYL = 1 specified Rendering coordinates...

  • Page 105: 4 . 4 . 1 1 Rpline

    4 . 4 . 1 1 RPLINE Function Draws a polygonal line at rendering coordinates while referencing a binary source. Command Format CODE DRAW MODE LINE COLOR 0 LINE COLOR 1 SOURCE ADDRESS H SOURCE ADDRESS L : Fixed at 0 1.
  • Page 106 3. Command Parameters LINE COLOR0: 8 or 16-bit/pixel color specification LINE COLOR1: 8 or 16-bit/pixel color specification SOURCE ADDRESS H: 1-bit/pixel source start upper address SOURCE ADDRESS L: 1-bit/pixel source start lower address TDX: Source size n (n = 1 to 65,535): Number of vertices DXn, DYn (n = 1 to 65,535): Relative coordinates Description Draws a polygonal line comprising line segments (XC, YC) –...

  • Page 107: 4 . 4 . 1 2 Move

    4 . 4 . 1 2 MOVE Command Format CODE DRAW MODE Sign extension Sign extension 1. Code B'10000 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work × × × × ×...
  • Page 108 Example (0, 0) (XC, YC) Work coordinates Rendering coordinates...

  • Page 109: 4 . 4 . 1 3 Rmove

    4 . 4 . 1 3 RMOVE Command Format CODE DRAW MODE 1. Code B'10001 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work × × × × × × Draw Mode Reserved Fixed at Fixed at...
  • Page 110 Example (0, 0) Old (XC, YC) (XC, YC) (Old XC + XC, old YC + YC) Work coordinates Rendering coordinates...

  • Page 111: 4 . 4 . 1 4 Lcofs

    4 . 4 . 1 4 LCOFS Command Format CODE DRAW MODE Sign extension Sign extension 1. Code B'10010 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work × × × × ×...
  • Page 112 Example (0, 0) (XO1+DX2, YO1+DY2) LINE (XO1, YO1) (XO1+DX1, YO1+DY1) Work coordinates Rendering coordinates...

  • Page 113: 4 . 4 . 1 5 Rlcofs

    4 . 4 . 1 5 RLCOFS Command Format CODE DRAW MODE 1. Code B'10011 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work × × × × × × Draw Mode Reserved Fixed at Fixed at...
  • Page 114 Example (0, 0) (Old XO+XO+DX2, Old YO+YO+DY2) (Old XO, Old YO) LINE (Old XO+XO, Old YO+YO) (Old XO+XO+DX1, Old YO+YO+DY1) Work coordinates Rendering coordinates...

  • Page 115: 4 . 4 . 1 6 Uclip

    4 . 4 . 1 6 UCLIP Command Format CODE DRAW MODE XMIN YMIN XMAX YMAX : Fixed at 0 1. Code B'10101 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work ×...
  • Page 116 Example (0, 0) (XMIN, YMIN) (XMAX, YMAX) Work coordinates Rendering coordinates...

  • Page 117: 4 . 4 . 1 7 Sclip

    4 . 4 . 1 7 SCLIP Command Format CODE DRAW MODE XMAX YMAX : Fixed at 0 1. Code B'10111 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work × × ×...
  • Page 118 Example (0, 0) (XMAX, YMAX) Work coordinates Rendering coordinates...

  • Page 119: 4 . 4 . 1 8 Clrw

    4 . 4 . 1 8 CLRW Command Format CODE DRAW MODE Sign extension XMIN Sign extension YMIN XMAX Sign extension YMAX Sign extension 1. Code B'10100 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering...
  • Page 120 Example (0, 0) (XMIN, YMIN) (XMAX, YMAX) Work coordinates...

  • Page 121: 4 . 4 . 1 9 Jump

    4 . 4 . 1 9 JUMP Command Format CODE DRAW MODE JUMP ADDRESS H JUMP ADDRESS L : Fixed at 0 1. Code B'11000 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work ×...
  • Page 122 Example Display list area Drawing starts Register setting command Drawing command JUMP command Drawing command Drawing command...

  • Page 123: 4 . 4 . 2 0 Gosub

    4 . 4 . 2 0 GOSUB Command Format CODE DRAW MODE SUBROUTINE ADDRESS H SUBROUTINE ADDRESS L 1. Code B'11001 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work × × ×...
  • Page 124 Example Display list area Drawing starts Register setting command Drawing command GOSUB command Drawing command Drawing command Subroutine Drawing command RET command...

  • Page 125: 4 . 4 . 2 1 Ret

    4 . 4 . 2 1 RET Command Format CODE DRAW MODE 1. Code B'11011 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work × × × × × × Draw Mode Reserved Fixed at Fixed at...

  • Page 126: 4 . 4 . 2 2 Trap

    4 . 4 . 2 2 TRAP Command Format CODE DRAW MODE 1. Code B'11111 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work × × × × × × Draw Mode Reserved Fixed at Fixed at...
  • Page 127 Example Display list area Register setting Drawing starts command Drawing command . . . Drawing command Drawing TRA interrupt generated command If TRE = 1 at this time, an interrupt Interrupt is generated externally. command Drawing stops...

  • Page 128: 4 . 4 . 2 3 Nop3

    4 . 4 . 2 3 NOP3 Command Format CODE DRAW MODE DUMMY DUMMY 1. Code B'11110 2. Rendering Attributes Reference Data Drawing Destination Multi-Valued Binary Binary Specified Source Source Work Color Rendering Work × × × × × × Draw Mode Reserved Fixed at...

  • Page 130: Registers

    Section 5 Registers 5 . 1 Overview The Q2 has address-mapped registers mapped onto the address space (H'000 to H'2FF). These registers are divided into six groups—interface control registers, memory control registers, display control registers, rendering control registers, input data control registers, and color palette registers. Word access is used on all of these registers.

  • Page 131: Register Updating

    5 . 2 Register Updating External Updating: Writing to an address-mapped registers from the CPU is called external updating. If external updating is performed in the interval from the raster following the end of screen display until immediately before the rise of VSYNC, a register can be rewritten without causing display flicker.
  • Page 132 HSYNC VBK and FRM flags both set to 1 Only VBK flag set to 1 Display area External update interval Display area External update interval Figure 5-1 (b) External Update Interval (Interlace Mode and Interlace Sync & Video Mode) Internal Updating: Some address-mapped registers have an internal update function. The internal update function is provided to prevent display flicker when the CPU modifies address- mapped registers relating to display operations without being aware of the display timing.
  • Page 133 Table 5-7 Registers with Internal Update Function Interface Control Registers Address Bit with Internal A [ 1 0 : 1 ] Name Abbreviation Update Function System control register SYSR DEN (bit 13) Memory Control Registers Address Bit with Internal A [ 1 0 : 1 ] Name Abbreviation Update Function...

  • Page 134: Interface Control Registers

    5 . 3 Interface Control Registers The interface control registers comprise eight 16-bit registers related to overall Q2 control, mapped onto addresses (A10–A1) H'000 to H'007. 5 . 3 . 1 System Control Register (SYSR) Bit: SRES DRES — — —...
  • Page 135 Bit 13—Display Enable (DEN): These bits control starting and stopping of display synchronous operation.. Bit 14: Bit 13: D R E S D E N Description Display operation is started. The DRES bit cannot be cleared to 0 while the RESET pin is low. When using the Q2 from the initial state, make all control register settings before clearing the DRES bit to 0.
  • Page 136 Bit 9—Display Area Change (DC): Controls frame buffer switching in manual display change mode. Bit 9: Description Switching of the frame buffer for display is not performed in manual display change mode. (Initial value) Switching of the frame buffer for display is performed in manual display change mode. Switching is performed in frame units in non-interlace and interlace modes, and in field units in interlace sync &...
  • Page 137 Bits 5 and 4—DMA Mode (DMA1, DMA0): These bits specify DMA transfer. Use the DMA flag (DMF) in SR to check for the start and end of DMA mode. Bit 5: Bit 4: DMA1 DMA0 Description Normal mode is set. (Initial value) The mode for DMA transfer to memory (UGM) corresponding to CS0 is set.

  • Page 138: Status Register (Sr)

    5 . 3 . 2 Status Register (SR) Bit: — — — — Initial value: — — — — Read/Write: — — — — Note: * Value is retained. The status register (SR) is a 16-bit read-only register used to read the internal status of the Q2 from outside.
  • Page 139 Bit 13—DMA Flag (DMF): Flag that indicates that DMA transfer mode has been initiated and transfer has been completed. Bit 13: Description DMA transfer mode has not been initiated at all since DMF flag clearing by the DMCL bit in SRCR, or the next DMA transfer mode (bits DMA1 and DMA0 = 01 or 11 in SYSR) has been initiated and the remaining transfer count has not yet reached 0.
  • Page 140 Bit 10—Trap Flag (TRA): Flag that indicates the end of command execution. Bit 10: Description Indicates the interval from TRA flag clearing by the SRES bit in SYSR or the TRCL bit in SRCR until the end of execution of the next command. (Initial value) Command execution has ended, or the current command is not being executed.

  • Page 141: Status Register Clear Register (Srcr)

    5 . 3 . 3 Status Register Clear Register (SRCR) Bit: TVCL FRCL DMCL CECL VBCL TRCL CSCL — — — — — — — — — Initial value: — — — — — — — — — Read/Write: — —...

  • Page 142: Interrupt Enable Register (Ier)

    5 . 3 . 4 Interrupt Enable Register (IER) Bit: — — — — — — — — — Initial value: — — — — — — — — — Read/Write: — — — — — — — — — The interrupt enable register (IER) is a 16-bit readable/writable register that enables or disables interrupts by the corresponding flags in SR.
  • Page 143 Bit 13—DMA Flag Enable (DME): Enables or disables interrupts initiated by the DMF flag in SR. Bit 13: D M E Description Interrupts initiated by the DMF flag in SR are disabled. (Initial value) Interrupts initiated by the DMF flag in SR are enabled. When DMF·DME = 1, an IRL interrupt request is sent to the CPU.

  • Page 144: Memory Mode Register (Memr)

    Bit 9—Command Suspend Flag Enable (CSE): Enables or disables interrupts initiated by the CSF flag in SR. Bit 9: C S E Description Interrupts initiated by the CSF flag in SR are disabled. (Initial value) Interrupts initiated by the CSF flag in SR are enabled. When CSF·CSE = 1, an IRL interrupt request is sent to the CPU.

  • Page 145: Display Mode Register (Dsmr)

    Bits 3 and 2—Memory Address Mode (MEA1, MEA0): These bits select the number of row addresses for the memory used for the UGM. Bit 6: Bit 4: M E S 2 M E S 0 Description 9 row addresses 10 row addresses 11 row addresses 12 row addresses Bits 1 and 0—Reserved: Only 0 should be written to these bits.
  • Page 146 Bit 8—Dot Clock Mode (DOT): Specifies settings for the dot clock, the basic clock for the Q2’s display block. Bit 8: D O T Description The clock input from the CLK1 pin is used as the display dot clock. The frequency of the clock output from the DCLK pin is the same as that of CLK1. The frequency of the clock output from the FCLK pin is 1/2 that of CLK1.
  • Page 147 Bits 7 and 6—TV Sync Mode (TVM1, TVM0): These bits specify TV sync mode, in which synchronous operation is performed by means of HSYNC and VSYNC input from an external source, or master mode, in which HSYNC and VSYNC are output. Bit 7: Bit 6: T V M 1...
  • Page 148 Bits 3 to 0—Refresh Cycles (REF3 to REF0): These bits specify the number of cycles for which refreshing is performed within one raster in the display screen area. Bit 3: Bit 2: Bit 1: Bit 0: R E F 3 R E F 2 R E F 1 R E F 0...

  • Page 149: Rendering Mode Register (Remr)

    5 . 3 . 7 Rendering Mode Register (REMR) Bit: — — — — — — — — — — — — — — Initial value: — — — — — — — — — — — — — — Read/Write: —...
  • Page 150 GBM = 0 (8 bits/pixel), MWX = 0 (512 pixels) A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Y upper coordinate X upper coordinate Y lower coordinate X lower coordinate GBM = 0 (8 bits/pixel), MWX = 1 (1024 pixels) A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0...

  • Page 151: Input Data Conversion Mode Register (Iemr)

    5 . 3 . 8 Input Data Conversion Mode Register (IEMR) ÉrÉbÉg — — — YUV1 YUV0 — — — — — — — — — — — èâä˙íl — — — — — — — — — — — —...

  • Page 152: Memory Control Registers

    5 . 4 Memory Control Registers The memory control registers comprise eleven 16-bit registers related to the UGM (unified graphics memory) configuration, mapped onto addresses (A10–A1) H'008 to H'012. 5 . 4 . 1 Display Size Registers X and Y (DSRX, DSRY) Bit: DSRX —...

  • Page 153: Display Start Address Registers 0 And 1 (Dsar0, Dsar1)

    5 . 4 . 2 Display Start Address Registers 0 and 1 (DSAR0, DSAR1) Bit: DSAR0 — — — — — — — — — DSA0 (address A22–A16 setting) Initial value: — — — — — — — — — Read/Write: —...

  • Page 154: Display List Start Address Registers H And L (Dlsarh, Dlsarl)

    5 . 4 . 3 Display List Start Address Registers H and L (DLSARH, DLSARL) Bit: DLSARH — — — — — — — — — DLSAH (address A22–A16 setting) Initial value: — — — — — — — — —...

  • Page 155: Work Area Start Address Register (Wsar)

    5 . 4 . 5 Work Area Start Address Register (WSAR) Bit: — — — — — — — — — WSAH (address A22–A16 setting) — — Initial value: — — — — — — — Read/Write: — — — —...

  • Page 156: Dma Transfer Word Count Register (Dwawr)

    The upper bits (A22 to A16) of the start address are set in the DMASH field in DMASRH, and the lower bits (A15 to A1) in the DMASL field in DMASRL. If the value of these registers is modified during a series of DMA operations from the time bits DMA1 and DMA0 in SYSR are set to 10 by the CPU until they are cleared automatically by the Q2, operation will be unstable.

  • Page 157: Display Control Registers

    5 . 5 Display Control Registers The display control registers comprise twelve 16-bit registers for setting the display timing, mapped onto addresses (A10–A1) H'013 to H'01E. 5 . 5 . 1 Display Window Registers (DSWR (HDS/HDE/VDS/VDE)) Bit: DSWR (HDS) — —...

  • Page 158: Horizontal Sync Pulse Width Register (Hswr)

    Bits 15 to 9 of DSWR (HDS) and DSWR (VDS) and bits 15 to 10 of DSWR (HDE) and DSWR (VDE) are reserved. Only 0 should be written to these bits (a read will return an undefined value). DSWR (HDS/HDE/VDS/VDE) bits HDS, HDE, VDS, and VDE retain their values in a reset. 5 .

  • Page 159: Vertical Start Position Register (Vspr)

    5 . 5 . 4 Vertical Start Position Register (VSPR) Bit: — — — — — — Initial value: — — — — — — Read/Write: — — — — — — Note: * Value is retained. The vertical start position register (VSPR) is a 16-bit readable/writable register that specifies the vertical sync signal start position in raster-line units.

  • Page 160: Display Off Output Registers H And L (Doorh, Doorl)

    5 . 5 . 6 Display Off Output Registers H and L (DOORH, DOORL) Bit: DOORH: — — — — — — — — — — Initial value: — — — — — — — — — — Read/Write: — —...

  • Page 161: Color Detection Registers H And L (Cderh, Cderl)

    5 . 5 . 7 Color detection registers H and L (CDERH, CDERL) Bit: CDERH: — — — — — — — — — — Initial value: — — — — — — — — — — Read/Write: — — —...

  • Page 162: Rendering Control Registers

    5 . 6 Rendering Control Registers The rendering control registers comprise two 16-bit registers related to rendering control, mapped onto addresses (A10–A1) H'01F and H'020. 5 . 6 . 1 Command Status Registers H and L (CSTRH, CSTRL) Bit: CSTRH —...

  • Page 163: Input Control Registers

    5 . 7 Input Control Registers The input control registers comprise five 16-bit registers related to the control of input data conversion, mapped onto addresses (A10–A1) H'021 to H'025. The settings in these registers are valid when the setting of bits YUV1 and YUV0 in the input data conversion mode register (IEMR) is 01 or 10.

  • Page 164: Image Data Size Registers X And Y (Idsrx, Idsry)

    5 . 7 . 2 Image Data Size Registers X and Y (IDSRX, IDSRY) Bit: IDSRX — — — — — IDSX IDSX IDSX IDSX IDSX IDSX IDSX IDSX IDSX IDSX IDSX* Initial value: — — — — — Read/Write: —...

  • Page 165: Color Palette

    5 . 8 Color Palette The color palette is mapped onto addresses (A10–A1) H'100 to H'2FF. Settings can be made for 256 pixels, with 6 bits each for R, G, and B. The color palette is only valid when the GBM bit in the rendering mode register (REMR) is 0 (8 bits/pixel).
  • Page 166 Color Palette Registers H, L000–255 (CP000RH, L to CP255H, L) are 32-bit readable/writable registers. The settings are valid when the GBM bit is 0. The color palette is controlled in 2-word units comprising one pixel. The same units must therefore be used for accesses to the color palette registers. When writing to color palette registers, first write to the R register, then to the G and B registers.

  • Page 168: Section 6 Usage Notes

    Section 6 Usage Notes 6 . 1 CPU Clock and Q2-CLK0 1. When the SuperH and Q2 are operated asynchronously, input a clock that satisfies the following conditions to the CLK0 pin. High level interval of RD input to Q2, and WE0 and WE1 > Q2 WE or RD setup time + hold time + Q2 operating clock cycle (see figure 6.2).

  • Page 169: Horizontal Display Start Position Register Value

    CLK0 (input)/CLKi (multiplication off/ multiplication on) RDHW RD (input) R D High-Level Setup Time and Hold Time in CPU Read Cycle Figure 6-2 Timing 6 . 2 Horizontal Display Start Position Register Value When the DSX value is 512 or greater, if drawing or UGM access is performed during display, noise may be generated in the range in which the number of dots in the X direction exceeds 512.
  • Page 170 HSYNC Range exceeding Noise Display screen (1) 16 bits/pixel (GBM = 1) HDS < ((36/32) × (DCLK/CLK0) × (500 + (X-direction screen size – 512)) – (X-direction screen size – 512)) ↓ [Sample calculation] When X-direction screen size = 640 dots, CLK0 = 28.2636 MHz, DCLK = 14.1318 MHz: HDS <...

  • Page 171: Notes On Data Transfer In Yuv Mode

    6 . 3 Notes on Data Transfer in YUV Mode 1. If data transfer is performed continuously by CPU access when a YUV mode setting of 10 (∆ YUV-RGB conversion) is used, provide for an interval of 36 CLK0 cycles or more to be left immediately before transferring the last data of each raster.

  • Page 172: Note On Use Of Auto Display Change Mode

    reset bit should not be set to 1 during Q2 drawing operations. After a hardware reset this bit is set to 1, so it should be cleared to 0 before performing drawing operations with the Q2. A dummy display list is provided to enable Q2 drawing to be aborted midway. An abort can be performed by executing a rendering start using the dummy display list.

  • Page 173: Notes On Dma Mode

    6 . 7 Notes on DMA Mode 1. Dummy memory read before DMA transfer A dummy UGM read should be performed immediately before setting DMA transfer to the UGM (DMA bits = 01). 2. Register access during DMA transfer To read a Q2 register during DMA transfer to the UGM (DMA bits = 01), it is necessary to set YUV = 01 for the YUV mode, then set DMA = 01 for the DMA mode, and start DMA transfer.

  • Page 174: Power-On Sequence

    6 . 8 Power-On Sequence The CLK0, CLK1, and RESET signal timing when powering on is shown in the figure 6-4. The time from the rise of VCCn until the rise of CLK0 and CLK1 should be 100 ms or less, and the time from the rise of VCCn until the rise of RESET, 100 ms or more.

  • Page 175: Q2 Internal Buffers

    6 . 9 Q2 Internal Buffers The Q2 has three internal buffers—a command buffer, source buffer, and work buffer—as shown in figure 6-5. Address 16 × n Command buffer A → B 16 × (n + 1) Display list Size: 16 words 16 ×...
  • Page 176 Therefore, when the Q2 fetches data in the UGM into a buffer, it performs buffer updating by managing the read destination address of each buffer. An outline of buffer updating is given in (d) to (f) below. (d) When the Q2 uses the command buffer, the buffer contents are updated each time the UGM address value indicated by the Q2 exceeds a 16-word boundary.

  • Page 177: Notes On Transition To Display Off Mode

    1. Clear the VBK bit and wait until the VBK bit is set to 1. 2. Set a value of VDE - VDS or greater in DSY. The DSY value set previously is treated as valid internally until the next internal update is performed. 3.

  • Page 178: Note On Polygon4A Source Reference Location

    6 . 1 2 Note on POLYGON4A Source Reference Location Problem: When the POLYGON4A command is used under the conditions shown below, a source reference error occurs and the same data is drawn at the rendering coordinate X = (64 × t) + 1 pixel and the following pixel (where t ≥...

  • Page 180: Section 7 Electrical Characteristics

    Section 7 Electrical Characteristics 7 . 1 Absolute Maximum Ratings Permanent damage to the chip may result if absolute maximum ratings are exceeded. In normal operation, it is advisable to observe the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the chip. Table 7-1 Absolute Maximum Ratings I t e m Symbol...

  • Page 181: Recommended Operating Conditions

    7 . 2 Recommended Operating Conditions 7 . 2 . 1 Recommended Operating Conditions Table 7-2 Recommended Operating Conditions I t e m Symbol T y p M a x Unit Power supply voltage , PLLV 4.75 5.25 CPUV 5 V operation 4.75 5.25 3.3 V operation...

  • Page 182: Electrical Characteristics Test Methods

    7 . 3 Electrical Characteristics Test Methods 7 . 3 . 1 Timing Testing The output low voltage for timing testing is 1.5 V. The output high voltage for timing testing is also 1.5 V. for timing testing (1.5 V) DC level (steady) V (0.4 V) Reference point...

  • Page 183: Test Load Circuit (All Output And Input/Output Pins)

    7 . 3 . 2 Test Load Circuit (All Output and Input/Output Pins) 5.0V Test Point RL = 1.8 kΩ C = 70 PF R = 10 kΩ All diodes are 1S2074 H or equivalent products. Input/output timing test levels (excluding CLK0 and CLK1) Low level: 1.5 V High level: 1.5 V Figure 7-2...

  • Page 184: Electrical Characteristics

    7 . 4 Electrical Characteristics 7 . 4 . 1 DC Characteristics Table 7-3 DC Characteristics = 5.0 V ±5%, (Unless otherwise indicated, V = CPUV = PLLV GND = CPUGND = PLGND = 0 V, Ta = 0 to +70°C) P i n I t e m Names...

  • Page 185: Ac Characteristics

    I t e m I n p u t Ou tput High-Z Pull-up Pin Names CMOS — — — CLK1, CLK0 — — — MODE2–0, RESET, A22–A1, CS1–0, RD, WE1–0, DACK CMOS — HSYNC/EXHSYNC, VSYNC/EXVSYNC, ODDF, MD15–0 CMOS — D15–D0 —...
  • Page 186 Table 7-4 Input Clocks (2) (Pins MODE2 to MODE0 = 000, 001, 010: Multiplication On) T e s t I t e m Symbol Min M a x Unit Conditions N o t e s ×1 Clock 0 Cycle Time 30.3 Figure 7-4 ×2...
  • Page 187 Reset Table 7-5 Reset T e s t I t e m Symbol M a x Unit Conditions N o t e s RESET Low Pulse Width — Figure 7-5 RESW c y c 1 RESET Uncertain Time — RES1 of Acceptance 1 RESET Uncertain Time —...
  • Page 188 (3) CPU Read Cycle Table 7-6 CPU Read Cycle T e s t I t e m Symbol M a x Unit Conditions N o t e s Address Setup Time — Figure 7-6 Address Hold Time — CSn Setup Time —...
  • Page 189 (4) CPU Write Cycle Table 7-7 CPU Write Cycle T e s t I t e m Symbol M a x Unit Conditions N o t e s Address Setup Time — Figure 7-7 Address Hold Time — CSn Setup Time —...
  • Page 190 (5) DMA Write Cycle Table 7-8 DMA Write Cycle T e s t I t e m Symbol M a x Unit Conditions N o t e s 1/2 × RD “High” Level Setup Time t — Figure 7-8 Multiplica- –...
  • Page 191 (7) UGM Read Cycle Table 7-10UGM Read Cycle T e s t I t e m Symbol M a x Unit Conditions N o t e s RAS Delay Time — Figure 7-11 RASD Figure 7-12 CAS Delay Time — CASD Row Address Setup Time —...
  • Page 192 (8) UGM Write Cycle Table 7-11UGM Write Cycle T e s t I t e m Symbol M a x Unit Conditions N o t e s RAS Delay Time — Figure 7-13 RASD Figure 7-14 CAS Delay Time — CASD Row Address Setup Time —...
  • Page 193 (10) Master Display Mode Table 7-13Master Display Mode T e s t I t e m Symbol M a x Unit Conditions N o t e s DCLK Rise Delay Time from — Figure 7-16 DCRD CLK1 FCLK Rise Delay Time from —...
  • Page 194 (11) TV Sync Display Mode Table 7-14TV Sync Display Mode T e s t I t e m Symbol M a x Unit Conditions N o t e s DCLK Rise Delay Time from — Figure 7-17 DCRD CLK1 Figure 7-18 Figure 7-19 µs DCLK Fall Delay Time 1...

  • Page 195: Timing Charts

    Table 7-14TV Sync Display Mode (cont) T e s t I t e m Symbol M a x Unit Conditions N o t e s ODDF Uncertain Time of — Figure 7-14 cyc1 Acceptance 1 ODDF Uncertain Time of — cyc1 Acceptance 2 Note: 1.
  • Page 196 CPWH CPWL 0.5V 0.5V 0.5V CLK0 (input) (pins MODE2 to MODE0 = 000) CLKi (pins MODE2 to MODE0 = 000) CLKD1 CLKD1 CPWH CPWL 0.5V 0.5V 0.5V CLK0 (input) (pins MODE2 to MODE0 = 001) CLKi (pins MODE2 to MODE0 = 001) CLKD1 CLKD1 CLKD3...

  • Page 197: Reset Timing

    7 . 5 . 2 Reset Timing Figure 7-5 Reset Timing...

  • Page 198: Cpu Read Cycle Timing

    7 . 5 . 3 CPU Read Cycle Timing CPU Read Cycle Timing (CPU ← Q2) with Hardware Wait Figure 7-6...

  • Page 199: Cpu Write Cycle Timing

    7 . 5 . 4 CPU Write Cycle Timing CPU Write Cycle Timing (CPU → Q2) with Hardware Wait Figure 7-7...

  • Page 200: Dma Write Cycle Timing (Dmac → Q2)

    DMA Write Cycle Timing (DMAC → Q2) 7 . 5 . 5 DMA Write Cycle Timing (DMAC → Q2) Figure 7-8...
  • Page 201 DMA Write Cycle Timing (DMAC → Q2) Figure 7-9...

  • Page 202: Interrupt Output Timing

    7 . 5 . 6 Interrupt Output Timing Figure 7-10 Interrupt Output Timing...

  • Page 203: Ugm Read Cycle Timing

    7 . 5 . 7 UGM Read Cycle Timing UGM Single Read Cycle Timing Figure 7-11 UGM (EDO-DRAM) Single Read Cycle Timing...
  • Page 204 UGM Burst Read Cycle Timing Figure 7-12 UGM (EDO-DRAM) Burst Read Cycle Timing...

  • Page 205: Ugm Write Cycle Timing

    7 . 5 . 8 UGM Write Cycle Timing UGM Single Write Cycle Timing Figure 7-13 UGM (EDO-DRAM) Single Write Cycle Timing...
  • Page 206 UGM Burst Write Cycle Timing Figure 7-14 UGM (EDO-DRAM) Burst Write Cycle Timing...

  • Page 207: Ugm Refresh Cycle Timing

    7 . 5 . 9 UGM Refresh Cycle Timing Figure 7-15 UGM (EDO-DRAM) Refresh Cycle Timing...

  • Page 208: 7 . 5 . 1 0 Master Mode Display Timing

    7 . 5 . 1 0 Master Mode Display Timing CLK1 (input) (DOT = 0) CLK1 (input) (DOT = 1) DCRD DCRD DCLK (output) FCFD FCRD FCRD FCLK (output) DD17 to DD0 (output) HSDD HSDD HSYNC (output) VSDD VSDD VSYNC (output) ODDD ODDD ODDF (output)

  • Page 209: Tv Sync Mode Display Timing

    7 . 5 . 1 1 TV Sync Mode Display Timing CLK1 (input) (DOT = 0) CLK1 (input) (DOT = 1) DCRD DCRD DCLK (output) FCFD FCRD FCRD FCLK (output) DD17 to DD0 (output) DIDD DIDD DISP (output) CDEDD CDEDD CDE (output) “High”...
  • Page 210 Figure 7-18 TV Sync Mode Display Timing...
  • Page 211 Figure 7-19 TV Sync Mode Display Timing (When DOT = 1 and E X H S Y N C cycle is odd multiple of CLK1 cycle)
  • Page 213 Figure 7-20 TV Sync Mode Display Timing (When DOT = 0, or DOT = 1 and E X H S Y N C cycle is even multiple of CLK1 cycle)

  • Page 214: Appendix A Registers

    Appendix A Registers Table A-1 Registers...
  • Page 215 Table A-1 Registers (cont)

  • Page 216: Appendix B Drawing Commands And Parameters

    Appendix B Drawing Commands and Parameters B . 1 Relationship Between Drawing Commands and Rendering Attributes Table B-1 Relationship Between Drawing Commands and Rendering Attributes Drawing Reference Data Rendering Attributes Destination Command × ∆ × × × POLYGON4A × ∆ ×...

  • Page 217: Drawing Command Codes

    B . 2 Drawing Command Codes Table B.2 Drawing Command Codes CODE DRAW MODE CODE COMMAND POLYGON4A POLYGON4B POLYGON4C FTRAP RFTRAP LINEW RLINEW LINE RLINE PLINE RPLINE MOVE RMOVE LCOFS RLCOFS CLRW UCLIP SCLIP JUMP GOSUB TRAP NOP3...

  • Page 218: Drawing Command Parameter Specifications

    B . 3 Drawing Command Parameter Specifications POLYGON4 Commands : Fixed at 0 Source starting points TXS, TYS TXS or TYS Given as unsigned max. 10-bit data. Specify correctly according to source area size. Source size TDX, TDY TDX or TDY Given as unsigned max.
  • Page 219 FTRAP, RFTRAP Number of vertices (2 ≤ n ≤ 65,535), absolute (1 ≤ n ≤ 65,535), relative Given as unsigned 16-bit data. Left-hand side coordinate DXL Sign extension Given as signed 11-bit data. Use sign extension in upper vacant bits. Absolute coordinate Vertex coordinate DXn (2 ≤...
  • Page 220 LINEW, RLINEW Number of vertices (2 ≤ n ≤ 65,535), absolute (1 ≤ n ≤ 65,535), relative Given as unsigned 16-bit data. Absolute coordinate Vertex coordinate DXn (2 ≤ n ≤ 65,535) Sign extension Given as signed 11-bit data. Use sign extension in upper vacant bits. Absolute coordinate Vertex coordinate DYn (2 ≤...
  • Page 221 LINE, RLINE Number of vertices (2 ≤ n ≤ 65,535), absolute (1 ≤ n ≤ 65,535), relative Given as unsigned 16-bit data. 16-bit/pixel color specification LINE COLOR0 Color data given as 16-bit data. 8-bit/pixel color specification LINE COLOR LINE COLOR Color data given as repeated 8-bit data.
  • Page 222 PLINE, RPLINE : Fixed at 0 bit/pixel color specification LINE COLOR0 Color data given as 16-bit data. 8-bit/pixel color specification LINE COLOR LINE COLOR Color data given as repeated 8-bit data. 1-bit/pixel source start upper address SOURCE ADDRESS H Given as upper 10 bits. 1-bit/pixel source start lower address SOURCE ADDRESS L Given as lower 13 bits.
  • Page 223 MOVE, RMOVE Absolute coordinate Sign extension Vertex coordinate XC Given as signed 11-bit data. Use sign extension in upper vacant bits. Absolute coordinate Sign extension Vertex coordinate YC Given as signed 11-bit data. Use sign extension in upper vacant bits. Relative coordinates Vertex coordinates XC, YC Given as signed 8-bit data.
  • Page 224 JUMP : Fixed at 0 Jump destination upper address JUMP ADDRESS H Given as upper 10 bits. Jump destination lower address JUMP ADDRESS L Given as lower 13 bits. Jump destination address is set as a word address. GOSUB : Fixed at 0 Subroutine upper address SUBROUTINE ADDRESS H Given as upper 10 bits.

  • Page 225: Appendix C Drawing Algorithms

    Appendix C Drawing Algorithms Straight Line Drawing Algorithms • 8-point drawing and 4-point drawing Figures C-1 (a) and (b) show examples of straight lines plotted on a bit-mapped display. Circles in the figures represent pixels. Due to the characteristics of a bit-mapped display, a straight line is drawn with the pixels arranged in a path differing slightly from an actual straight line.
  • Page 226 Figure C-2 Comparison of (a) 8-Point Drawing and (b) 4-Point Drawing Next, 8-point drawing straight line approximation is described, using figure C-3 (a). After pixel A is drawn, either pixel B or pixel C is selected; the basis for selection is proximity to an actual straight line.
  • Page 227 Readers interested in drawing algorithms can find further information in the sources listed below. 1. Jerry van Aken: “Curve-Drawing Algorithms for Raster Display,” ACM Trans. Graph. Vol. 4, No. 2 (April, 1985), 147–169 2. J.E. Bresenham: “Algorithm for Computer Control of a Digital Plotter,” IBM Syst. J. Vol. 4, No.

  • Page 228: Appendix D Package Dimensions

    Package Dimensions HD64411 Q2 User’s Manual Publication Date: 1st Edition, December 1997 Published by: Semiconductor and IC Div. Hitachi, Ltd. Edited by: Technical Documentation Center Hitachi Microcomputer System Ltd. Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.

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