Page 1 User’s Manual µ PD789860, 789861 Subseries 8-Bit Single-Chip Microcontrollers µ PD789860 µ PD78E9860A µ PD789861 µ PD78E9861A µ PD789860(A) Document No. U14826EJ5V0UD00 (5th edition) Date Published June 2004 NS CP(K) 2000, 2003 © Printed in Japan...
Page 2 [MEMO] User’s Manual U14826EJ5V0UD...
Page 3 A reset operation must be executed immediately after power-on for devices with reset functions. FIP and EEPROM are trademarks of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 Major Revisions in This Edition Pages Description • Addition of µ Throughout PD789860(A) as a product name µ pp. 21, 23, 24, 27 CHAPTER 1 GENERAL ( PD789860 SUBSERIES) • Addition of 1.4 Quality Grade • Update of 1.6 78K/0S Series Lineup to latest version •...
Page 7 Target Readers This manual is intended for user engineers who wish to understand the functions of µ PD789860, 789861 Subseries in order to design and develop its application systems and programs. The target devices are the following subseries products. •...
Page 8 PD789860(A) ◊ To understand the overall functions of the µ PD789860, 789861 Subseries → Read this manual in the order of the CONTENTS. ◊ How to read register formats → The name of a bit whose number is enclosed with <> is reserved in the assembler and is defined as an sfr variable by the #pragma sfr directive for the C compiler.
Page 9: User's Manual U14826Ej5V0Ud
However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. µ PD789860, 789861 Subseries User’s Manual This manual 78K/0S Series Instructions User’s Manual U11047E Documents Related to Development Software Tools (User’s Manuals) Document Name Document No.
Page 10: Table Of Contents
CONTENTS µ CHAPTER 1 GENERAL ( PD789860 SUBSERIES) ................21 Features ............................21 Applications..........................21 Ordering Information .........................21 Quality Grade..........................22 Pin Configuration (Top View)....................22 78K/0S Series Lineup.........................23 Block Diagram ..........................26 Overview of Functions.......................27 Differences Between Standard Quality Grade Products and (A) Products ......30 µ...
Page 11 Reading from I/O port........................68 6.4.3 Arithmetic operation of I/O port....................68 µ CHAPTER 7 CLOCK GENERATOR ( PD789860 SUBSERIES) ............69 Clock Generator Functions....................... 69 Clock Generator Configuration ....................69 Clock Generator Control Register.................... 70 System Clock Oscillators......................71 7.4.1...
Page 12 Clock Generator Operation .......................74 Changing Setting of CPU Clock....................75 7.6.1 Time required for switching CPU clock ..................75 7.6.2 Switching CPU clock ........................75 µ CHAPTER 8 CLOCK GENERATOR ( PD789861 SUBSERIES)............76 Clock Generator Functions .......................76 Clock Generator Configuration ....................76 Clock Generator Control Register....................77 System Clock Oscillators ......................78 8.4.1 System clock oscillator ........................78...
Page 13 CHAPTER 12 BIT SEQUENTIAL BUFFER ..................132 12.1 Bit Sequential Buffer Functions .....................132 12.2 Bit Sequential Buffer Configuration..................132 12.3 Bit Sequential Buffer Control Register ..................133 12.4 Bit Sequential Buffer Operation .....................134 CHAPTER 13 KEY RETURN CIRCUIT....................135 13.1 Key Return Circuit Function ....................135 13.2 Key Return Circuit Configuration and Operation ..............135 CHAPTER 14 INTERRUPT FUNCTIONS ....................136 14.1 Interrupt Function Types......................136...
Page 14 19.1.3 Description of “Flag” column......................171 19.2 Operation List ...........................172 19.3 Instructions Listed by Addressing Type ................177 CHAPTER 20 ELECTRICAL SPECIFICATIONS .................180 CHAPTER 21 EXAMPLE OF RC OSCILLATION FREQUENCY CHARACTERISTICS (REFERENCE VALUES)....................195 CHAPTER 22 PACKAGE DRAWING ....................196 CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS............197 APPENDIX A DEVELOPMENT TOOLS....................199 Software Package ........................201 Language Processing Software .....................201...
Page 15 Memory Map ( PD789860, 789861).......................39 µ Memory Map ( PD78E9860A, 78E9861A) .....................40 µ Data Memory Addressing ( PD789860, 789861) ...................42 µ Data Memory Addressing ( PD78E9860A, 78E9861A)..................43 Program Counter Configuration ........................44 Program Status Word Configuration .......................44 Stack Pointer Configuration ..........................45 Data to Be Saved to Stack Memory ........................45...
Page 16 LIST OF FIGURES (2/4) Figure No. Title Page Format of 8-Bit Timer Mode Control Register 30.....................89 Format of 8-Bit Timer Mode Control Register 40.....................90 Format of Carrier Generator Output Control Register 40 ................91 Format of Port Mode Register 2 ........................92 Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation)............95 Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Cleared to 00H)......95 9-10...
Page 17 LIST OF FIGURES (3/4) Figure No. Title Page 11-9 LVI Circuit Operation Timing .........................131 12-1 Block Diagram of Bit Sequential Buffer ......................132 12-2 Format of Bit Sequential Buffer Output Control Register 10 .................133 12-3 Format of Port Mode Register 2........................133 12-4 Operation Timing of Bit Sequential Buffer .....................134 13-1...
Page 18 LIST OF FIGURES (4/4) Figure No. Title Page 17-4 Pin Connection Example ........................164 17-5 Signal Conflict (Input Pin of Serial Interface)....................165 17-6 Abnormal Operation of Other Device ......................165 17-7 Signal Conflict (RESET Pin)..........................166 17-8 Wiring Example for EEPROM Writing Adapter with Pseudo 3-Wire..............167 Development Tools ............................200 Connection Condition of Target........................205 User’s Manual U14826EJ5V0UD...
Page 19 LIST OF TABLES (1/2) Table No. Title Page Standard Quality Grade Products and (A) Products ..................27 Types of Pin I/O Circuits and Recommended Connection of Unused Pins .............38 Internal ROM Capacity............................41 Vector Table ..............................41 Special Function Registers ..........................48 EEPROM Write Time (When Operating at f = 5.0 MHz)................60 EEPROM Write Time (When Operating at f = 1.0 MHz)................60...
Page 20 LIST OF TABLES (2/2) Table No. Title Page 10-4 Inadvertent Program Loop Detection Time of Watchdog Timer ..............122 10-5 Interval Time of Watchdog Timer ........................123 12-1 Configuration of Bit Sequential Buffer ......................132 14-1 Interrupt Sources............................137 14-2 Interrupt Request Signals and Corresponding Flags..................139 14-3 Time from Generation of Maskable Interrupt Request to Servicing...............143 15-1...
Page 21: Chapter 1 General ( Μ Pd789860 Subseries)
µ CHAPTER 1 GENERAL ( PD789860 SUBSERIES) 1.1 Features • ROM and RAM capacity Item Program Memory Data Memory (ROM) Product Name Internal High-Speed RAM EEPROM µ PD789860, Mask ROM 4 KB 128 bytes 32 bytes µ PD789860(A) µ PD78E9860A...
Page 22: Quality Grade
P l e a s e r e f e r t o " Q u a l i t y G r a d e s o n N E C S e m i c o n d u c t o r D e v i c e s " ( D o c u m e n t N o . C 1 1 5 3 1 E ) p u b l i s h e d b y NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Page 23: 0S Series Lineup
PD789850A with enhanced timer and A/D converter, etc. µ 30-pin PD789850A On-chip CAN controller Keyless entry µ µ 30-pin PD789862 PD789860 with enhanced timer function, SIO, and expanded ROM and RAM µ µ 20-pin PD789861 RC oscillation version of PD789860 µ 20-pin PD789860...
Page 24 µ CHAPTER 1 GENERAL ( PD789860 SUBSERIES) The major differences between subseries are shown below. Series for General-Purpose and LCD Drive Function Timer 8-Bit 10-Bit Serial Interface Remarks Capacity Subseries 8-Bit 16-Bit Watch WDT MIN.Value (Bytes) µ − − −...
Page 25 µ CHAPTER 1 GENERAL ( PD789860 SUBSERIES) Series for ASSP Function Timer 8-Bit 10-Bit Serial Interface Remarks Capacity Subseries 8-Bit 16-Bit Watch WDT MIN.Value (Bytes) µ − − − − − PD789800 2 ch 1 ch 2 ch (USB: 1 ch) 4.0 V...
Page 26: Block Diagram
µ CHAPTER 1 GENERAL ( PD789860 SUBSERIES) 1.7 Block Diagram PORT 0 P00-P07 8-bit CASCADED TIMER30 16-bit TIMER PORT 2 P20, P21 78K/0S TMI/P21 8-bit COUNTER (EEPROM) TIMER/EVENT CPU CORE TMO/P20 4 KB COUNTER40 PORT 4 P40-P43 BSFO/P20 BIT SEQ. BUFFER...
Page 27: Overview Of Functions
The only difference between the standard quality grade product ( PD789860) and (A) product ( PD789860(A)) in µ PD789860 Subseries is the quality grade. The other features (functions and electrical specifications) are the same. Table 1-1. Standard Quality Grade Products and (A) Products Part Number...
Page 28: Chapter 2 General ( Μ Pd789861 Subseries)
µ CHAPTER 2 GENERAL ( PD789861 SUBSERIES) 2.1 Features • ROM and RAM capacity Item Program Memory Data Memory (ROM) Product Name Internal High-Speed RAM EEPROM µ PD789861 Mask ROM 4 KB 128 bytes 32 bytes µ PD78E9861A EEPROM 4 KB •...
Page 29: Pin Configuration (Top View)
µ CHAPTER 2 GENERAL ( PD789861 SUBSERIES) 2.4 Pin Configuration (Top View) 20-pin plastic SSOP (7.62 mm (300)) µ PD789861MC-×××-5A4 µ PD78E9861AMC-5A4 RESET P21/TMI P20/TMO/BSFO IC (V P43/KR13 P42/KR12 P41/KR11 P40/KR10 Caution Connect the IC (Internally Connected) pin directly to V µ...
Page 30: 0S Series Lineup
PD789850A with enhanced timer and A/D converter, etc. µ 30-pin PD789850A On-chip CAN controller Keyless entry µ µ 30-pin PD789862 PD789860 with enhanced timer function, SIO, and expanded ROM and RAM µ µ 20-pin PD789861 RC oscillation version of PD789860 µ 20-pin PD789860...
Page 31 µ CHAPTER 2 GENERAL ( PD789861 SUBSERIES) The major differences between subseries are shown below. Series for General-Purpose and LCD Drive Function Timer 8-Bit 10-Bit Serial Interface Remarks Capacity Subseries 8-Bit 16-Bit Watch WDT MIN.Value (Bytes) µ − − − Small- PD789046 16 K...
Page 32 − − − − Keyless PD789861 2 ch 1 ch 1.8 V RC-oscillation entry version, on-chip EEPROM µ PD789860 On-chip EEPROM µ PD789862 16 K 1 ch 2 ch 1 ch (UART: 1 ch) µ − − − − PD789871...
Page 33: Block Diagram
µ CHAPTER 2 GENERAL ( PD789861 SUBSERIES) 2.6 Block Diagram PORT 0 P00-P07 8-bit CASCADED TIMER30 16-bit TIMER PORT 2 P20, P21 78K/0S TMI/P21 8-bit COUNTER (EEPROM) TIMER/EVENT CPU CORE TMO/P20 4 KB COUNTER40 PORT 4 P40-P43 BSFO/P20 BIT SEQ. BUFFER RESET SYSTEM CONTROL...
Page 34: Overview Of Functions
µ CHAPTER 2 GENERAL ( PD789861 SUBSERIES) 2.7 Overview of Functions µ µ Part Number PD789861 PD78E9861A Item Internal memory Mask ROM EEPROM 4 KB High-speed RAM 128 bytes EEPROM 32 bytes Oscillator RC oscillator µ Minimum instruction execution time 2.0/8.0 s (@1.0 MHz operation with system clock) 8 bits ×...
Page 35: Chapter 3 Pin Functions
Internally connected. Connect directly to V − − − This pin is used to set the EEPROM programming mode and applies a high voltage when a program is written or verified. µ Notes 1. PD789860 Subseries only µ PD789861 Subseries only User’s Manual U14826EJ5V0UD...
Page 36: Description Of Pin Functions
An active-low system reset signal is input to this pin. µ 3.2.5 X1, X2 ( PD789860 Subseries) These pins are used to connect a crystal resonator for system clock oscillation. To supply an external clock, input the clock to X1 and input the inverted signal to X2.
Page 37: Vdd
3.2.10 IC (mask ROM version only) µ The IC (Internally Connected) pin is used to set the PD789860 and 789861 to test mode before shipment. In normal operation mode, directly connect this pin to the V pin with as short a wiring length as possible.
Page 38: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 3 PIN FUNCTIONS 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the I/O circuit configuration of each type, see Figure 3-1. Table 3-1.
Page 39: Chapter 4 Cpu Architecture
CHAPTER 4 CPU ARCHITECTURE 4.1 Memory Space µ PD789860, 789861 Subseries can each access up to 64 KB of memory space. Figures 4-1 and 4-2 show the memory maps. µ Figure 4-1. Memory Map ( PD789860, 789861) F F F F H...
Page 40 CHAPTER 4 CPU ARCHITECTURE µ Figure 4-2. Memory Map ( PD78E9860A, 78E9861A) F F F F H Special function registers (SFR) 256 × 8 bits F F 0 0 H F E F F H Internal high-speed RAM 128 × 8 bits F E 8 0 H F E 7 F H Reserved...
Page 41: Internal Program Memory Space
The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). µ PD789860, 789861 Subseries provide the following internal ROMs (or EEPROM) containing the following capacities. Table 4-1. Internal ROM Capacity...
Page 42: Special Function Register (Sfr) Area
µ Each of the PD789860, 789861 Subseries is provided with a wide range of addressing modes to make memory manipulation as efficient as possible. The data memory area (FE80H to FFFFH) can be accessed using a unique addressing mode according to its use, such as a special function register (SFR). Figures 4-3 and 4-4 illustrate the data memory addressing.
Page 43 CHAPTER 4 CPU ARCHITECTURE µ Figure 4-4. Data Memory Addressing ( PD78E9860A, 78E9861A) F F F F H Special function registers (SFR) SFR addressing 256 × 8 bits F F 2 0 H F E 1 F H F F 0 0 H F E F F H Short direct addressing Internal high-speed RAM...
Page 44: Processor Registers
CHAPTER 4 CPU ARCHITECTURE 4.2 Processor Registers µ PD789860, 789861 Subseries provide the following on-chip processor registers: 4.2.1 Control registers The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program counter, a program status word, and a stack pointer.
Page 45: Stack Pointer Configuration
CHAPTER 4 CPU ARCHITECTURE (d) Carry flag (CY) This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area.
Page 46: General-Purpose Registers
CHAPTER 4 CPU ARCHITECTURE 4.2.2 General-purpose registers A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H). In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL).
Page 47: Special Function Registers (Sfrs)
CHAPTER 4 CPU ARCHITECTURE 4.2.3 Special function registers (SFRs) Unlike the general-purpose registers, each special function register has a special function. The special function registers are allocated to the 256-byte area FF00H to FFFFH. The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and bit manipulation instructions.
Page 48: Special Function Registers
Oscillation stabilization time selection OSTS Note 3 register √ √ − FFFBH Processor clock control register Notes 1. Specify address FF10H directly for 16-bit access. 2. This value is 04H only after a power-on-clear reset. µ PD789860 Subseries only User’s Manual U14826EJ5V0UD...
Page 49: Instruction Address Addressing
CHAPTER 4 CPU ARCHITECTURE 4.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 50: Immediate Addressing
CHAPTER 4 CPU ARCHITECTURE 4.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) to branch. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces. [Illustration] In case of CALL !addr16 and BR !addr16 instructions CALL or BR...
Page 51: Register Addressing
CHAPTER 4 CPU ARCHITECTURE 4.3.4 Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) to branch. This function is carried out when the BR AX instruction is executed. [Illustration] User’s Manual U14826EJ5V0UD...
Page 52: Operand Address Addressing
CHAPTER 4 CPU ARCHITECTURE 4.4 Operand Address Addressing The following methods (addressing) are available to specify the register and memory to undergo manipulation during instruction execution. 4.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier Description...
Page 53: Short Direct Addressing
CHAPTER 4 CPU ARCHITECTURE 4.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word. The fixed space where this addressing is applied is the 256-byte space FE20H to FF1FH. An internal high- speed RAM is mapped at FE20H to FEFFH and the special function registers (SFR) are mapped at FF00H to FF1FH.
Page 54: Special Function Register (Sfr) Addressing
CHAPTER 4 CPU ARCHITECTURE 4.4.3 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H to FF1FH can also be accessed with short direct addressing.
Page 55: Register Addressing
CHAPTER 4 CPU ARCHITECTURE 4.4.4 Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
Page 56: Register Indirect Addressing
CHAPTER 4 CPU ARCHITECTURE 4.4.5 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces.
Page 57: Based Addressing
CHAPTER 4 CPU ARCHITECTURE 4.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored.
Page 58: Chapter 5 Eeprom (Data Memory)
CHAPTER 5 EEPROM (DATA MEMORY) 5.1 Memory Space µ PD789860, 789861 Subseries have 32 × 8 bits of electrically erasable Besides internal high-speed RAM, the PROM (EEPROM) on-chip as data memory. Unlike normal RAM, EEPROM can maintain its contents even if its power supply is cut. In addition, unlike EPROM, its contents can be electrically erased without using ultraviolet rays.
Page 59: Format Of Eeprom Write Control Register 10
CHAPTER 5 EEPROM (DATA MEMORY) Figure 5-2. Format of EEPROM Write Control Register 10 Symbol <2> <1> <0> Address After reset Note EEWC10 EWCS102 EWCS101 EWCS100 ERE10 EWST10 EWE10 FFD8H EWCS102 EWCS101 EWCS100 EEPROM timer count clock selection < 1.41 MHz) or f (Setting enabled only when f or f...
Page 60 CHAPTER 5 EEPROM (DATA MEMORY) Table 5-1. EEPROM Write Time (When Operating at f = 5.0 MHz) Note 1 EWCS102 EWCS101 EWCS100 EEPROM Timer Count Clock EEPROM Data Write Time × 145 (3.71 ms) (39.1 kHz) Output of 8-bit timer 40 × 145 Note 2 Output of 8-bit timer 40 Other than above...
Page 61: Notes For Eeprom Writing
CHAPTER 5 EEPROM (DATA MEMORY) 5.4 Notes for EEPROM Writing The following caution points pertain to writing to EEPROM. (1) When fetching an instruction from EEPROM or stopping the system clock oscillator, be sure to do so after setting EEPROM to write-disabled (EWE10 = 0). (2) Set the count clock in a state in which the selected clock is operating (oscillating).
Page 62 CHAPTER 5 EEPROM (DATA MEMORY) (6) Do not execute the following operations while writing to EEPROM, as execution will cause the EEPROM cell value at that address to become undefined. • Turn off the power • Execute a reset • Clear ERE10 to 0 •...
Page 63: Chapter 6 Port Functions
CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions µ PD789860, 789861 Subseries is provided with the ports shown in Table 6-1. These ports enable several types of control. These ports, while originally designed as digital input/output ports, have alternate functions. For the alternate functions, see CHAPTER 3 PIN FUNCTIONS.
Page 64: Port 0
CHAPTER 6 PORT FUNCTIONS 6.2.1 Port 0 This is an 8-bit I/O port with an output latch. Port 0 can be set to input or output mode in 1-bit units by using port mode register 0 (PM0). RESET input sets port 0 to input mode. Figure 6-1 shows a block diagram of port 0.
Page 65: Port 2
CHAPTER 6 PORT FUNCTIONS 6.2.2 Port 2 This is a 2-bit I/O port with output latches. Port 2 can be set to input or output mode in 1-bit units by using port mode register 2 (PM2). RESET input sets port 2 to input mode. Figures 6-2 and 6-3 show block diagrams of port 2.
Page 66: Port 4
CHAPTER 6 PORT FUNCTIONS Figure 6-3. Block Diagram of P21 Alternate function PORT Output latch (P21) P21/TMI PM21 Port mode register Port 2 read signal Port 2 write signal 6.2.3 Port 4 This is a 4-bit input-only port. Mask ROM versions can specify an on-chip pull-up resistor by means of the mask option.
Page 67: Port Function Control Registers
CHAPTER 6 PORT FUNCTIONS 6.3 Port Function Control Registers The following registers are used to control the ports. • Port mode registers (PM0, PM2) Port mode registers (PM0, PM2) PM0 and PM2 are registers for which port I/O settings can be controlled in 1-bit units. Each port mode register is set with a 1-bit or 8-bit memory manipulation instruction.
Page 68: Operation Of Port Functions
CHAPTER 6 PORT FUNCTIONS 6.4 Operation of Port Functions The operation of a port differs depending on whether the port is set to input or output mode, as described below. 6.4.1 Writing to I/O port In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port.
Page 69: Chapter 7 Clock Generator ( Μ Pd789860 Subseries)
µ CHAPTER 7 CLOCK GENERATOR ( PD789860 SUBSERIES) 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following type of system clock oscillator is used. • System clock (crystal/ceramic) oscillator This circuit oscillates at 1.0 to 5.0 MHz.
Page 70: Clock Generator Control Register
µ CHAPTER 7 CLOCK GENERATOR ( PD789860 SUBSERIES) 7.3 Clock Generator Control Register The clock generator is controlled by the following register: • Processor clock control register (PCC) Processor clock control register (PCC) PCC selects the CPU clock and the division ratio.
Page 71: System Clock Oscillators
µ CHAPTER 7 CLOCK GENERATOR ( PD789860 SUBSERIES) 7.4 System Clock Oscillators 7.4.1 System clock oscillator The system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the inverted signal to the X2 pin.
Page 72: Examples Of Incorrect Resonator Connection
µ CHAPTER 7 CLOCK GENERATOR ( PD789860 SUBSERIES) 7.4.2 Examples of incorrect resonator connection Figure 7-4 shows examples of incorrect resonator connections. Figure 7-4. Examples of Incorrect Resonator Connection (1/2) (a) Wiring too long (b) Crossed signal line PORTn (n = 0, 2, 4)
Page 73: Frequency Divider
µ CHAPTER 7 CLOCK GENERATOR ( PD789860 SUBSERIES) Figure 7-4. Examples of Incorrect Resonator Connection (2/2) (e) Signal is fetched 7.4.3 Frequency divider The frequency divider divides the system clock oscillator output (f ) and generates clocks. User’s Manual U14826EJ5V0UD...
Page 74: Clock Generator Operation
µ CHAPTER 7 CLOCK GENERATOR ( PD789860 SUBSERIES) 7.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode: • System clock • CPU clock • Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC) as follows: µ...
Page 75: Changing Setting Of Cpu Clock
µ CHAPTER 7 CLOCK GENERATOR ( PD789860 SUBSERIES) 7.6 Changing Setting of CPU Clock 7.6.1 Time required for switching CPU clock The CPU clock can be selected by using bit 1 (PCC0) of the processor clock control register (PCC). Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old clock is used for the duration of several instructions after that (see Table 7-2).
Page 76: Chapter 8 Clock Generator ( Μ Pd789861 Subseries)
µ CHAPTER 8 CLOCK GENERATOR ( PD789861 SUBSERIES) 8.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following type of system clock oscillator is used. • System clock (RC) oscillator This circuit oscillates at 1.0 MHz ±15%.
Page 77: Clock Generator Control Register
µ CHAPTER 8 CLOCK GENERATOR ( PD789861 SUBSERIES) 8.3 Clock Generator Control Register The clock generator is controlled by the following register: • Processor clock control register (PCC) Processor clock control register (PCC) PCC selects the CPU clock and the division ratio. PCC is set with a 1-bit or 8-bit memory manipulation instruction.
Page 78: System Clock Oscillators
µ CHAPTER 8 CLOCK GENERATOR ( PD789861 SUBSERIES) 8.4 System Clock Oscillators 8.4.1 System clock oscillator The system clock oscillator is oscillated by the resistor (R) and capacitor (C) (1.0 MHz TYP.) connected across the CL1 and CL2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the CL1 pin, and input the inverted signal to the CL2 pin.
Page 79: Examples Of Incorrect Resonator Connection
µ CHAPTER 8 CLOCK GENERATOR ( PD789861 SUBSERIES) 8.4.2 Examples of incorrect resonator connection Figure 8-4 shows examples of incorrect resonator connections. Figure 8-4. Examples of Incorrect Resonator Connection (1/2) (a) Wiring too long (b) Crossed signal line PORTn (n = 0, 2, 4) (c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates)
Page 80: Frequency Divider
µ CHAPTER 8 CLOCK GENERATOR ( PD789861 SUBSERIES) Figure 8-4. Examples of Incorrect Resonator Connection (2/2) (e) Signal is fetched 8.4.3 Frequency divider The frequency divider divides the system clock oscillator output (f ) and generates clocks. User’s Manual U14826EJ5V0UD...
Page 81: Clock Generator Operation
µ CHAPTER 8 CLOCK GENERATOR ( PD789861 SUBSERIES) 8.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode: • System clock • CPU clock • Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC) as follows: µ...
Page 82: Changing Setting Of Cpu Clock
µ CHAPTER 8 CLOCK GENERATOR ( PD789861 SUBSERIES) 8.6 Changing Setting of CPU Clock 8.6.1 Time required for switching CPU clock The CPU clock can be selected by using bit 1 (PCC0) of the processor clock control register (PCC). Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old clock is used for the duration of several instructions after that (see Table 8-2).
Page 83: Chapter 9 8-Bit Timers 30 And 40
9.1 8-Bit Timers 30, 40 Functions µ PD789860, 789861 Subseries have on chip an 8-bit timer (timer 30) (1 channel) and an 8-bit timer/event counter (timer 40) (1 channel). The operation modes shown in the table below are possible by means of mode register settings.
Page 84: 8-Bit Timers 30, 40 Configuration
CHAPTER 9 8-BIT TIMERS 30 AND 40 9.2 8-Bit Timers 30, 40 Configuration The 8-bit timers include the following hardware. Table 9-2. Configuration of 8-Bit Timers 30, 40 Item Configuration 8 bits × 2 (TM30, TM40) Timer counter Compare registers: 8 bits × 3 (CR30, CR40, CRH40) Registers Timer output 1 (TMO)
Page 85: Timer 30 Block Diagram
Figure 9-1. Timer 30 Block Diagram Internal bus 8-bit timer mode control register 30 (TMC30) TCE30 TCL302 TCL301 TCL300 TMD301 TMD300 8-bit compare Decoder register 30 (CR30) Selector To Figure 9-2 (G) Match Timer 30 match signal Bit 7 of TM40 (in carrier generator mode) (From Figure 9-2 (A)) 8-bit timer...
Page 86: Timer 40 Block Diagram
Figure 9-2. Timer 40 Block Diagram Internal bus Carrier generator output 8-bit timer mode control control register 40 register 40 (TMC40) (TCA40) 8-bit compare 8-bit compare register H40 TCE40 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40 register 40 (CR40) RMC40 NRZB40 NRZ40 (CRH40) Decoder From Figure 9-1 (G)
Page 87 CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-3. Block Diagram of Output Controller (Timer 40) TOE40 RMC40 NRZ40 PM20 output latch TMO/P20/ BSFO Carrier clock Carrier generator mode 8-bit compare register 30 (CR30) This register is an 8-bit register that always compares the count value of 8-bit timer counter 30 (TM30) with the value set in CR30 and generates an interrupt request (INTTM30) if they match.
Page 88: 8-Bit Timers 30, 40 Control Registers
CHAPTER 9 8-BIT TIMERS 30 AND 40 Discrete mode TM30 • Reset • Clearing of TCE30 (bit 7 of 8-bit timer mode control register 30 (TMC30)) to 0 • Match of TM30 and CR30 • TM30 count value overflow (ii) TM40 •...
Page 89: Format Of 8-Bit Timer Mode Control Register 30
CHAPTER 9 8-BIT TIMERS 30 AND 40 8-bit timer mode control register 30 (TMC30) TMC30 is the register that controls the setting of the timer 30 count clock and the setting of the operating mode. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 90: Format Of 8-Bit Timer Mode Control Register 40
CHAPTER 9 8-BIT TIMERS 30 AND 40 8-bit timer mode control register 40 (TMC40) TMC40 is the register that controls the setting of the timer 40 count clock and the setting of the operating mode. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 91: Format Of Carrier Generator Output Control Register 40
CHAPTER 9 8-BIT TIMERS 30 AND 40 Carrier generator output control register 40 (TCA40) TCA40 is used to set the timer output data in the carrier generator mode. This register is set with an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 9-6.
Page 92: Format Of Port Mode Register 2
CHAPTER 9 8-BIT TIMERS 30 AND 40 Port mode register 2 (PM2) PM2 sets port 2 to input/output in 1-bit units. When using the P20/TMO/BSFO pin as a timer output, clear the PM20 and P20 output latch to 0. When using the P21/TMI pin as a timer input, set the PM21 to 1. This register is set with a 1-bit or 8-bit memory manipulation instruction.
Page 93: 8-Bit Timers 30, 40 Operation
CHAPTER 9 8-BIT TIMERS 30 AND 40 9.4 8-Bit Timers 30, 40 Operation 9.4.1 Operation as 8-bit timer counter Timer 30 and timer 40 can independently be used as an 8-bit timer counter. The following modes can be used for the 8-bit timer counter. •...
Page 94 CHAPTER 9 8-BIT TIMERS 30 AND 40 Table 9-3. Interval Time of Timer 30 (During f = 5.0 MHz Operation) TCL302 TCL301 TCL300 Minimum Interval Time Maximum Interval Time Resolution µ µ (12.8 (3.28 ms) (12.8 µ µ (51.2 (13.1 ms) (51.2 Input cycle of timer 40 match Input cycle of timer 40 match...
Page 95: Timing Of Interval Timer Operation With 8-Bit Resolution (Basic Operation)
CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-8. Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation) Count clock TMn0 Clear Clear Clear CRn0 TCEn0 Count start Count stop INTTMn0 Interrupt acknowledgement Interrupt acknowledgement Interrupt acknowledgement Note Interval time Interval time Note Timer 40 only Remarks 1.
Page 96: Timing Of Interval Timer Operation With 8-Bit Resolution (When Crn0 Is Set To Ffh)
CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-10. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH) Count clock TMn0 Clear Clear Clear CRn0 TCEn0 Count start INTTMn0 Note Note Timer 40 only Remark n = 3, 4 Figure 9-11.
Page 97 CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-12. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N > M)) Count clock N − 1 TMn0 Clear Clear Clear CRn0 TCEn0 TMn0 overflows because M <...
Page 98: Timing Of Interval Timer Operation With 8-Bit Resolution (When Timer 40 Match Signal Is Selected For Timer 30 Count Clock)
CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-13. Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 40 Match Signal Is Selected for Timer 30 Count Clock) Timer 40 count clock TM40 Clear Clear Clear Clear CR40 TCE40 Count start INTTM40 Input clock to timer 30...
Page 99: Timing Of Operation Of External Event Counter With 8-Bit Resolution
CHAPTER 9 8-BIT TIMERS 30 AND 40 Operation as external event counter with 8-bit resolution (timer 40 only) The external event counter counts the number of external clock pulses input to the TMI/P21 pin by using 8-bit timer counter 40 (TM40). To operate timer 40 as an external event counter, settings must be made in the following sequence.
Page 100 CHAPTER 9 8-BIT TIMERS 30 AND 40 Operation as square-wave output wit 8-bit resolution (timer 40 only) Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare register 40 (CR40). To operate timer 40 for square-wave output, settings must be made in the following sequence. <1>...
Page 101: Timing Of Square-Wave Output With 8-Bit Resolution
CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-15. Timing of Square-Wave Output with 8-Bit Resolution Count clock TM40 Clear Clear Clear CR40 TCE40 Count start INTTM40 Interrupt acknowledgement Interrupt acknowledgement Interrupt acknowledgement Note Square-wave output cycle Note The initial value of TMO is low level when output is enabled (TOE40 = 1). Square-wave output cycle = 2 (N+1) ×...
Page 102: Operation As 16-Bit Timer Counter
CHAPTER 9 8-BIT TIMERS 30 AND 40 9.4.2 Operation as 16-bit timer counter Timer 30 and timer 40 can be used as a 16-bit timer counter using cascade connection. In this case, 8-bit timer counter 30 (TM30) is the higher 8 bits and 8-bit timer counter 40 (TM40) is the lower 8 bits. 8-bit timer 40 controls reset and clear.
Page 103 CHAPTER 9 8-BIT TIMERS 30 AND 40 Table 9-9. Interval Time with 16-Bit Resolution (During f = 5.0 MHz Operation) TCL402 TCL401 TCL400 Minimum Interval Time Maximum Interval Time Resolution µ µ (0.2 (13.1 ms) (0.2 µ µ (0.8 (52.4 ms) (0.8 input cycle ×...
Page 104: Timing Of Interval Timer Operation With 16-Bit Resolution
Figure 9-16. Timing of Interval Timer Operation with 16-Bit Resolution TM40 count clock TM40 FFH 00H 7FH 80H FFH 00H 7FH 80H FFH 00H count value Not cleared because TM30 does not match Cleared because TM30 and TM40 match simultaneously CR40 TCE40 Count start...
Page 105 CHAPTER 9 8-BIT TIMERS 30 AND 40 Operation as external event counter with 16-bit resolution The external event counter counts the number of external clock pulses input to the TMI/P21 pin by TM30 and TM40. To operate as an external event counter with 16-bit resolution, settings must be made in the following sequence.
Page 106: Timing Of External Event Counter Operation With 16-Bit Resolution
Figure 9-17. Timing of External Event Counter Operation with 16-Bit Resolution TMI pin input TM40 FFH 00H 7FH 80H FFH 00H 7FH 80H FFH 00H count value Not cleared because TM30 does not match Cleared because TM30 and TM40 match simultaneously CR40 TCE40 Count start...
Page 107 CHAPTER 9 8-BIT TIMERS 30 AND 40 Operation as square-wave output with 16-bit resolution Square waves of any frequency can be output at an interval specified by the count value preset in CR30 and CR40. To operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence. <1>...
Page 108: Timing Of Square-Wave Output With 16-Bit Resolution
Figure 9-18. Timing of Square-Wave Output with 16-Bit Resolution TM40 count clock TM40 FFH 00H 7FH 80H FFH 00H 7FH 80H FFH 00H count value Not cleared because TM30 does not match Cleared because TM30 and TM40 match simultaneously CR40 TCE40 Count start TM30...
Page 109: Operation As Carrier Generator
CHAPTER 9 8-BIT TIMERS 30 AND 40 9.4.3 Operation as carrier generator An arbitrary carrier clock generated by TM40 can be output in the cycle set in TM30. To operate timer 30 and timer 40 as carrier generators, setting must be made in the following sequence. <1>...
Page 110 CHAPTER 9 8-BIT TIMERS 30 AND 40 The operation of the carrier generator is as follows. <1> When the count value of TM40 matches the value set in CR40, an interrupt request signal (INTTM40) is generated and output of timer 40 is inverted, which makes the compare register switch from CR40 to CRH40.
Page 111: Timing Of Carrier Generator Operation (When Cr40 = N, Crh40 = M (M > N))
CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-19. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > N)) TM40 count clock TM40 count value Clear Clear Clear Clear CR40 CRH40 TCE40 Count start INTTM40 Carrier clock TM30 count clock...
Page 112: Timing Of Carrier Generator Operation (When Cr40 = N, Crh40 = M (M < N))
CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-20. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M < N)) TM40 count clock TM40 count value Clear Clear Clear Clear CR40 CRH40 TCE40 Count start INTTM40 Carrier clock TM30 count clock...
Page 113: Timing Of Carrier Generator Operation (When Cr40 = Crh40 = N)
CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-21. Timing of Carrier Generator Operation (When CR40 = CRH40 = N) TM40 count clock TM40 count value Clear Clear Clear Clear Clear CR40 CRH40 TCE40 Count start INTTM40 Carrier clock TM30 count clock TM30 count value...
Page 114: Operation As Pwm Output (Timer 40 Only)
CHAPTER 9 8-BIT TIMERS 30 AND 40 9.4.4 Operation as PWM output (timer 40 only) In the PWM output mode, a pulse of any duty ratio can be output by setting a low-level width using CR40 and a high-level width using CRH40. To operate timer 40 in PWM output mode, settings must be made in the following sequence.
Page 115: Pwm Output Mode Timing (Basic Operation)
CHAPTER 9 8-BIT TIMERS 30 AND 40 Figure 9-22. PWM Output Mode Timing (Basic Operation) TM40 count clock TM40 count value Clear Clear Clear Clear CR40 CRH40 TCE40 Count start INTTM40 Note Note The initial value of TMO is low level when output is enabled (TOE40 = 1). Figure 9-23.
Page 116: Notes On Using 8-Bit Timers 30, 40
CHAPTER 9 8-BIT TIMERS 30 AND 40 9.5 Notes on Using 8-Bit Timers 30, 40 Error on starting timer An error of up to 1.5 clocks is included in the time between the timer being started and a match signal being generated.
Page 117: Counting Operation If Timer Is Started When Tmi Is High
CHAPTER 9 8-BIT TIMERS 30 AND 40 Count value if external clock input from TMI pin is selected When the external clock signal input from the TMI pin is selected as the count clock, the count value may start from 01H if the timer is enabled (TCE40 = 0 → 1) while the TMI pin is high. This is because the input signal of the TMI pin is internally ANDed with the TCE40 signal.
Page 118: Chapter 10 Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.1 Watchdog Timer Functions The watchdog timer has the following functions: • Watchdog timer • Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). Watchdog timer The watchdog timer is used to detect inadvertent program loops.
Page 119: Watchdog Timer Configuration
CHAPTER 10 WATCHDOG TIMER 10.2 Watchdog Timer Configuration The watchdog timer includes the following hardware. Table 10-3. Configuration of Watchdog Timer Item Configuration Control registers Timer clock selection register 2 (TCL2) Watchdog timer mode register (WDTM) Figure 10-1. Block Diagram of Watchdog Timer Internal bus TMMK4 Prescaler...
Page 120: Watchdog Timer Control Registers
CHAPTER 10 WATCHDOG TIMER 10.3 Watchdog Timer Control Registers The following two registers are used to control the watchdog timer. • Timer clock selection register 2 (TCL2) • Watchdog timer mode register (WDTM) Timer clock selection register 2 (TCL2) TCL2 sets the watchdog timer count clock. This register is set with an 8-bit memory manipulation instruction.
Page 121: Format Of Watchdog Timer Mode Register
CHAPTER 10 WATCHDOG TIMER Watchdog timer mode register (WDTM) WDTM sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 10-3.
Page 122: Watchdog Timer Operation
CHAPTER 10 WATCHDOG TIMER 10.4 Watchdog Timer Operation 10.4.1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (inadvertent program loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (TCL20 to TCL22) of the timer clock selection register 2 (TCL2).
Page 123: Operation As Interval Timer
CHAPTER 10 WATCHDOG TIMER 10.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at an interval specified by a preset count value.
Page 124: Chapter 11 Power-On-Clear Circuits
CHAPTER 11 POWER-ON-CLEAR CIRCUITS 11.1 Power-on-Clear Circuit Functions The power-on-clear circuits include the following two circuits, which have the following functions. Power-on-clear (POC) circuit • Compares the detection voltage (V ) with the power supply voltage (V ) and generates an internal reset signal if V <...
Page 125: Block Diagram Of Power-On-Clear Circuit
CHAPTER 11 POWER-ON-CLEAR CIRCUITS Figure 11-1. Block Diagram of Power-on-Clear Circuit P-ch P-ch Internal reset signal − Detection POCOF1 POCMK1 POCMK0 voltage source (V Power on clear register 1 (POCF1) Internal bus Figure 11-2. Block Diagram of Low-Voltage Detection Circuit P-ch LVI stop signal (set during STOP...
Page 126: Power-On-Clear Circuit Control Registers
CHAPTER 11 POWER-ON-CLEAR CIRCUITS 11.3 Power-on-Clear Circuit Control Registers The following three registers control the power-on-clear circuits. • Power-on-clear register 1 (POCF1) • Low-voltage detection register 1 (LVIF1) • Low-voltage detection level selection register 1 (LVIS1) Power-on-clear register 1 (POCF1) POCF1 controls POC circuit operation.
Page 127: Format Of Low-Voltage Detection Register 1
CHAPTER 11 POWER-ON-CLEAR CIRCUITS Low-voltage detection register 1 (LVIF1) LVIF1 controls the operation of the LVI circuit. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 11-4. Format of Low-Voltage Detection Register 1 Symbol <7>...
Page 128: Power-On-Clear Circuit Operation
CHAPTER 11 POWER-ON-CLEAR CIRCUITS 11.4 Power-on-Clear Circuit Operation 11.4.1 Power-on-clear (POC) circuit operation The POC circuit compares the detection voltage (V ) with the power supply voltage (V ) and generates an internal reset signal if V < V For mask ROM versions, it is possible to select a POC switching circuit, normally operating POC circuit, or normally halted POC circuit by using a mask option.
Page 129: Timing Of Internal Reset Signal Generation When Poc Circuit Normally Halted
CHAPTER 11 POWER-ON-CLEAR CIRCUITS Figure 11-7. Timing of Internal Reset Signal Generation When POC Circuit Normally Halted Power supply voltage (V Detection voltage (V 1.8 V Time Internal reset “H” signal Figure 11-8. Timing of Internal Reset Signal Generation in POC Switching Circuit Power supply voltage (V Detection voltage (V 1.8 V...
Page 130: Operation Of Low-Voltage Detection (Lvi) Circuit
CHAPTER 11 POWER-ON-CLEAR CIRCUITS 11.4.2 Operation of low-voltage detection (LVI) circuit The LVI circuit compares the detection voltage (V ) with the power supply voltage (V ) and generates an interrupt request signal (INTLVI1) if V < V (LVI circuit operating). As shown in Figure 11-2 Block Diagram of Low-Voltage Detection Circuit, the divided resistors and comparators of the LVI circuit turn OFF when the reset signal is generated or in STOP mode.
Page 131: Lvi Circuit Operation Timing
CHAPTER 11 POWER-ON-CLEAR CIRCUITS Processing to enable LVI interrupt again after LVI interrupt servicing SET1 LVIMK1; LVI interrupt disabled CLR1 LVION1; LVI operation disabled SET1 LVION1; LVI operation enabled CLR1 LVIMK1; LVI interrupt enabled Figure 11-9 shows the LVI circuit operation timing. Figure 11-9.
Page 132: Chapter 12 Bit Sequential Buffer
CHAPTER 12 BIT SEQUENTIAL BUFFER 12.1 Bit Sequential Buffer Functions µ PD789860, 789861 Subseries have an on-chip bit sequential buffer of 8 bits + 8 bits = 16 bits. The functions of the bit sequential buffer are shown below. •...
Page 133: Bit Sequential Buffer Control Register
CHAPTER 12 BIT SEQUENTIAL BUFFER 12.3 Bit Sequential Buffer Control Register The bit sequential buffer is controlled by the following three registers. • Bit sequential buffer output control register 10 (BSFC10) • Port mode register 2 (PM2) • Port 2 (P2) Bit sequential buffer output control register 10 (BSFC10) BSFC10 controls the operation of the bit sequential buffer.
Page 134: Bit Sequential Buffer Operation
CHAPTER 12 BIT SEQUENTIAL BUFFER 12.4 Bit Sequential Buffer Operation Set as follows to operate the bit sequential buffer. <1> Set values to bit sequential buffer 10 data registers L and H (BSFRL10, BSFRH10) <2> Set the bit sequential buffer to operation enabled (BSFE10 = 1) If the LSB of BSFRL10 is being output at P20/BSFO/TMO, set P20 to output mode (PM20 = 0) and the output latch of P20 to 0 <3>...
Page 135: Chapter 13 Key Return Circuit
CHAPTER 13 KEY RETURN CIRCUIT 13.1 Key Return Circuit Function In STOP mode, this circuit generates a key return interrupt (INTKR1) by inputting a P40/KR10 to P43/KR13 falling edge. Cautions 1. The key return interrupt is a non-maskable interrupt that is effective only in STOP mode. In addition, P40/KR10 to P43/KR13 key input cannot be performed by mask control.
Page 136: Chapter 14 Interrupt Functions
CHAPTER 14 INTERRUPT FUNCTIONS 14.1 Interrupt Function Types The following two types of interrupt functions are used. Non-maskable interrupts This interrupt is acknowledged unconditionally even if interrupts are disabled. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated.
Page 137: Interrupt Sources And Configuration
CHAPTER 14 INTERRUPT FUNCTIONS 14.2 Interrupt Sources and Configuration There are a total of 7 non-maskable and maskable interrupt sources (see Table 14-1). Table 14-1. Interrupt Sources Note 1 Interrupt Type Priority Interrupt Source Internal/External Vector Table Basic Address Configuration Name Trigger Note 2...
Page 138: Basic Configuration Of Interrupt Function
CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Basic Configuration of Interrupt Function (A) External/internal non-maskable interrupt Internal bus Vector table Interrupt request address generator Standby release signal (B) Internal maskable interrupt Internal bus Vector table address generator Interrupt request Standby release signal Interrupt request flag Interrupt enable flag MK: Interrupt mask flag...
Page 139: Interrupt Function Control Registers
CHAPTER 14 INTERRUPT FUNCTIONS 14.3 Interrupt Function Control Registers The interrupt functions are controlled by the following three types of registers. • Interrupt request flag register 0 (IF0) • Interrupt mask flag register 0 (MK0) • Program status word (PSW) Table 14-2 lists interrupt requests, the corresponding interrupt request flags, and interrupt mask flags.
Page 140: Format Of Interrupt Mask Flag Register 0
CHAPTER 14 INTERRUPT FUNCTIONS Interrupt mask flag register 0 (MK0) The interrupt mask flag is used to enable and disable the corresponding maskable interrupts. MK0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MK0 to FFH. Figure 14-3.
Page 141: Interrupt Servicing Operation
µ Caution The PD789860 and 789861 Subseries have two non-maskable interrupt sources. Therefore, during execution of a non-maskable interrupt servicing program, a new non-maskable interrupt request is not acknowledged until the RETI instruction is executed. Be sure to execute the RETI instruction after the interrupt servicing program has been executed.
Page 142: Flowchart From Non-Maskable Interrupt Request Generation To Acknowledgment (Intwdt)
CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-5. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment (INTWDT) Start WDTM4 = 1 (watchdog timer mode is selected) Interval timer overflows WDTM3 = 0 (non-maskable interrupt is selected) Reset processing Interrupt request is generated Interrupt servicing is started WDTM: Watchdog timer mode register WDT:...
Page 143: Maskable Interrupt Request Acknowledgment Operation
CHAPTER 14 INTERRUPT FUNCTIONS 14.4.2 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt enabled status (when the IE flag is set to 1).
Page 144: Interrupt Request Acknowledgment Processing Algorithm
CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-8. Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (Interrupt request generated) ××MK = 0? Interrupt request pending IE = 1? Interrupt request pending Vectored interrupt servicing ××IF: Interrupt request flag ××MK: Interrupt mask flag Flag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable) Figure 14-9.
Page 145: Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set At Last Clock During Instruction Execution)
CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-10. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last Clock During Instruction Execution) 8 clocks Clock Interrupt Saving PSW and PC, jump servicing MOV A, r to interrupt servicing program Interrupt If an interrupt request flag (××IF) is set at the last clock of the instruction, the interrupt acknowledgment processing starts after the next instruction is executed.
Page 146: Multiple Interrupt Servicing
CHAPTER 14 INTERRUPT FUNCTIONS 14.4.3 Multiple interrupt servicing Multiple interrupt servicing in which another interrupt is acknowledged while an interrupt is being serviced can be performed using a priority order system. When two or more interrupts are generated at once, interrupt servicing is performed according to the priority assigned to each interrupt request in advance (see Table 14-1).
Page 147: Interrupt Request Pending
CHAPTER 14 INTERRUPT FUNCTIONS 14.4.4 Interrupt request pending Some instructions may keep pending the acknowledgment of an instruction request until the completion of the execution of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external interrupt) is generated during the execution.
Page 148: Chapter 15 Standby Function
CHAPTER 15 STANDBY FUNCTION 15.1 Standby Function and Configuration 15.1.1 Standby function The standby function is used to reduce the power consumption of the system and can be effected in the following two modes: HALT mode This mode is set when the HALT instruction is executed. HALT mode stops the operation clock of the CPU. The system clock oscillator continues oscillating.
Page 149: Standby Function Control Register
µ PD789861, 78E9861A: Oscillation stabilization time is fixed to 2 and cannot be selected by mask option. µ Note PD789860 Subseries only. µ There is no oscillation stabilization time selection register in the PD789861 Subseries. The oscillation µ stabilization time of the PD789861 Subseries is fixed at 2 Figure 15-1.
Page 150: Standby Function Operation
CHAPTER 15 STANDBY FUNCTION 15.2 Standby Function Operation 15.2.1 HALT mode HALT mode HALT mode is set by executing the HALT instruction. The operation statuses in HALT mode are shown in the following table. Table 15-1. Operation Statuses in HALT Mode Item HALT Mode Operation Status System clock...
Page 151: Releasing Halt Mode By Interrupt
CHAPTER 15 STANDBY FUNCTION Releasing HALT mode HALT mode can be released by the following three sources: (a) Releasing by unmasked interrupt request HALT mode is released by an unmasked interrupt request. In this case, if interrupt request acknowledgment is enabled, vectored interrupt servicing is performed. If interrupt acknowledgment is disabled, the instruction at the next address is executed.
Page 152: Releasing Halt Mode By Reset Input
Oscillation Oscillation stop Oscillation Clock µ Note In the PD789860, 2 or 2 can be selected by using the mask option. µ In the PD78E9860A, 2 : 6.55 ms (@f = 5.0 MHz operation) µ µ In the...
Page 153: Stop Mode
CHAPTER 15 STANDBY FUNCTION 15.2.2 STOP mode Setting and operation status of STOP mode STOP mode is set by executing the STOP instruction. Caution Because standby mode can be released by an interrupt request signal, standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset.
Page 154: Releasing Stop Mode By Interrupt
CHAPTER 15 STANDBY FUNCTION Releasing STOP mode STOP mode can be released by the following three sources: (a) Releasing by unmasked interrupt request STOP mode is released by an unmasked interrupt request. In this case, vectored interrupt servicing is performed if interrupt acknowledgment is enabled after the oscillation stabilization time has elapsed. If interrupt acknowledgment is disabled, the instruction at the next address is executed.
Page 155: Releasing Stop Mode By Reset Input
Oscillation Oscillation stop Oscillation Clock µ Note In the PD789860, 2 or 2 can be selected by using the mask option. µ In the PD78E9860A, 2 : 6.55 ms (@f = 5.0 MHz operation) µ µ In the...
Page 156: Chapter 16 Reset Function
CHAPTER 16 RESET FUNCTION The following three operations are available to generate reset signals. External reset input by RESET signal input Internal reset by watchdog timer inadvertent program loop time detection Internal reset by comparison of POC circuit power supply voltage and detection voltage External reset and internal reset have no functional differences.
Page 157: Reset Timing By Reset Input
CHAPTER 16 RESET FUNCTION Figure 16-2. Reset Timing by RESET Input X1, CL1 Reset period Oscillation Normal operation Normal operation (oscillation stabilization (reset processing) stops) time wait RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 16-3. Reset Timing by Watchdog Timer Overflow X1, CL1 Reset period Oscillation...
Page 158: Status Of Hardware After Reset
PC will be undefined, while the remainder of the hardware will be the same as after the reset. 2. In standby mode, the RAM enters the hold state after a reset. µ PD789860 Subseries only 4. This value is 04H only after a power-on-clear reset. User’s Manual U14826EJ5V0UD...
Page 159: Chapter 17 Μ Pd78E9860A, 78E9861A
µ CHAPTER 17 PD78E9860A, 78E9861A µ µ EEPROM versions in the PD789860, 789861 Subseries include the PD78E9860A and 78E9861A. µ µ µ PD78E9860A replaces the internal ROM of the PD789860 with EEPROM. The PD78E9861A replaces the µ µ internal ROM of the PD789861 with EEPROM.
Page 160: Eeprom Features (Program Memory)
µ CHAPTER 17 PD78E9860A, 78E9861A 17.1 EEPROM Features (Program Memory) µ The on-chip program memory in the PD78E9860A and 78E9861A is EEPROM. This chapter describes the functions of the EEPROM incorporated in the program memory area. For the EEPROM incorporated in data memory, see CHAPTER 5 EEPROM (DATA MEMORY). µ...
Page 161: Communication Mode
µ CHAPTER 17 PD78E9860A, 78E9861A 17.1.2 Communication mode Use the communication mode shown in Table 17-2 to perform communication between the dedicated flash µ programmer and PD78E9860A, 78E9861A. Table 17-2. Communication Mode List Note 1 Communication TYPE Setting Pins Used Number of Mode Pulses...
Page 162: Example Of Connection With Dedicated Flash Programmer
µ CHAPTER 17 PD78E9860A, 78E9861A Figure 17-3. Example of Connection with Dedicated Flash Programmer µ (a) Pseudo 3-wire ( PD78E9860A) µ Dedicated flash programmer PD78E9860A VPP1 RESET RESET (serial clock) (serial input) (serial output) Note (b) Pseudo 3-wire (µPD78E9861A) µ Dedicated flash programmer PD78E9861A VPP1...
Page 163: Pin Connection List
µ CHAPTER 17 PD78E9860A, 78E9861A If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated flash µ programmer, the following signals are generated for the PD78E9860A, 78E9861A. For details, refer to the manual of Flashpro III/Flashpro IV.
Page 164: On-Board Pin Processing
µ CHAPTER 17 PD78E9860A, 78E9861A 17.1.3 On-board pin processing When performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mode and EEPROM programming mode may be required in some cases.
Page 165: Signal Conflict (Input Pin Of Serial Interface)
µ CHAPTER 17 PD78E9860A, 78E9861A Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device or set the other device to the output high impedance status.
Page 166: Signal Conflict (Reset Pin)
µ CHAPTER 17 PD78E9860A, 78E9861A <RESET pin> If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator. If the reset signal is input from the user system in the EEPROM programming mode, a normal programming operation cannot be performed.
Page 167: Connection Of Adapter For Eeprom Writing
µ CHAPTER 17 PD78E9860A, 78E9861A 17.1.4 Connection of adapter for EEPROM writing The following figures show the examples of recommended connection when the adapter for EEPROM writing is used. Figure 17-8. Wiring Example for EEPROM Writing Adapter with Pseudo 3-Wire (1/2) µ...
Page 168 µ CHAPTER 17 PD78E9860A, 78E9861A Figure 17-8. Wiring Example for EEPROM Writing Adapter with Pseudo 3-Wire (2/2) µ PD78E9861A VDD (2.7 to 3.6 V) VDD2 (LVDD) CLKOUT RESET RESERVE/HS User’s Manual U14826EJ5V0UD...
Page 169: Chapter 18 Mask Options
CHAPTER 18 MASK OPTIONS µ PD789860 and 789861 have the following mask options. • P40 to P43 mask options On-chip pull-up resistors can be selected in bit units. <1> Specify on-chip pull-up resistors <2> Do not specify on-chip pull-up resistors •...
Page 170: Chapter 19 Instruction Set Overview
CHAPTER 19 INSTRUCTION SET OVERVIEW µ This chapter lists the instruction set of the PD789860, 789861 Subseries. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E). 19.1 Operation 19.1.1 Operand identifiers and description methods...
Page 171: Description Of "Operation" Column
CHAPTER 19 INSTRUCTION SET OVERVIEW 19.1.2 Description of “Operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 172: Operation List
CHAPTER 19 INSTRUCTION SET OVERVIEW 19.2 Operation List Mnemonic Operand Bytes Clocks Operation Flag AC CY r ← byte r, #byte (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte A ← r Note 1 A, r r ← A Note 1 r, A A ←...
Page 173 CHAPTER 19 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag AC CY rp ← word MOVW rp, #word AX ← (saddrp) AX, saddrp (saddrp) ← AX saddrp, AX AX ← rp Note AX, rp rp ← AX Note rp, AX AX ↔...
Page 174 CHAPTER 19 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag AC CY A, CY ← A − byte − CY × × × SUBC A, #byte (saddr), CY ← (saddr) − byte − CY × × × saddr, #byte A, CY ←...
Page 175 CHAPTER 19 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag AC CY A − byte × × × A, #byte (saddr) − byte × × × saddr, #byte A − r × × × A, r A − (saddr) ×...
Page 176 CHAPTER 19 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag AC CY (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) CALL !addr16 PC ← addr16, SP ← SP − 2 (SP − 1) ← (PC + 1) , (SP −...
Page 177: Instructions Listed By Addressing Type
CHAPTER 19 INSTRUCTION SET OVERVIEW 19.3 Instructions Listed by Addressing Type 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte saddr !addr16 [DE] [HL] $addr16 None [HL + byte] 1st Operand...
Page 178 CHAPTER 19 INSTRUCTION SET OVERVIEW 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note 2nd Operand #word saddrp None 1st Operand ADDW SUBW MOVW MOVW MOVW CMPW XCHW Note MOVW MOVW INCW DECW PUSH saddrp MOVW MOVW Note Only when rp = BC, DE, or HL.
Page 179 CHAPTER 19 INSTRUCTION SET OVERVIEW Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand !addr16 [addr5] $addr16 1st Operand Basic instructions CALL CALLT Compound instructions DBNZ Other instructions RET, RETI, NOP, EI, DI, HALT, STOP User’s Manual U14826EJ5V0UD...
Page 180: Chapter 20 Electrical Specifications
CHAPTER 20 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit Supply voltage –0.3 to +6.5 µ PD78E9860A, 78E9861A only, Note –0.3 to +10.5 Input voltage –0.3 to V + 0.3 Output voltage –0.3 to V + 0.3 Output current, high Per pin...
Page 181 CHAPTER 20 ELECTRICAL SPECIFICATIONS System Clock Oscillator Characteristics µ Ceramic or crystal oscillation ( PD789860, 789860(A), 78E9860A) = –40 to +85°C, V = 1.8 to 5.5 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Ceramic resonator Oscillation frequency...
Page 182 The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the µ PD789860 and 789860(A) so that the internal operating conditions are within the specifications of the DC and AC characteristics. User's Manual U14826EJ5V0UD...
Page 183 CHAPTER 20 ELECTRICAL SPECIFICATIONS µ RC oscillation ( PD789861, 78E9861A) = –40 to +85°C, V = 1.8 to 3.6 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit RC oscillator Oscillation frequency = Oscillation 0.85 1.15 Notes 1,2 voltage range External clock CL1 input frequency Note 1...
Page 184 CHAPTER 20 ELECTRICAL SPECIFICATIONS µ DC Characteristics ( PD789860, 789860(A), 78E9860A) (T = –40 to +85°C, V = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output current, low Per pin All pins Output current, high Per pin –0.75...
Page 185 CHAPTER 20 ELECTRICAL SPECIFICATIONS µ DC Characteristics ( PD789861, 78E9861A) (T = –40 to +85°C, V = 1.8 to 3.6 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output current, low Per pin All pins Output current, high Per pin –0.5 All pins –5.0...
Page 186 CHAPTER 20 ELECTRICAL SPECIFICATIONS µ DC Characteristics (T = –40 to +85°C, V = 1.8 to 5.5 V ( PD789860, 789860(A))) Parameter Symbol Conditions MIN. TYP. MAX. Unit = 5.0 V ±10% Note Power supply current 5.0 MHz Ceramic/crystal oscillation: crystal oscillation operating µ...
Page 187 CHAPTER 20 ELECTRICAL SPECIFICATIONS µ DC Characteristics (T = –40 to +85°C, V = 1.8 to 3.6 V ( PD789861)) Parameter Symbol Conditions MIN. TYP. MAX. Unit = 3.0 V ±10% Note Power supply current 1.0 MHz RC oscillation: RC oscillation operating mode µ...
Page 188 CHAPTER 20 ELECTRICAL SPECIFICATIONS DC Characteristics µ µ = –40 to +85°C, V = 1.8 to 5.5 V ( PD78E9860A), V = 1.8 to 3.6 V ( PD78E9861A)) Parameter Symbol Conditions MIN. TYP. MAX. Unit = 5.0 V ±10% Note Power supply current 5.0 MHz Ceramic/crystal oscillation:...
Page 189 CHAPTER 20 ELECTRICAL SPECIFICATIONS AC Characteristics Basic operation µ PD789860, 789860(A), 78E9860A (T = –40 to +85°C, V = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 2.7 V ≤ V ≤ 5.5 V µ Cycle time...
Page 190 CHAPTER 20 ELECTRICAL SPECIFICATIONS µ PD789861, 78E9861A (T = –40 to +85°C, V = 1.8 to 3.6 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit µ 2.7 V ≤ V ≤ 3.6 V Cycle time 9.42 (minimum instruction execution µ time) 1.8 V ≤...
Page 191 CHAPTER 20 ELECTRICAL SPECIFICATIONS AC Timing Measurement Points (Excluding X1, CL1 Input) 0.8V 0.8V Points of measurement 0.2V 0.2V Clock Timing (MIN.) X1 (CL1) input (MAX.) Remark or f TMI Timing Key Return Input Timing KRIL KR10 to KR13 RESET Input Timing RESET User’s Manual U14826EJ5V0UD...
Page 192 CHAPTER 20 ELECTRICAL SPECIFICATIONS Power-on-Clear Circuit Characteristics (a) DC characteristics (T = –40 to +85°C, µ µ = 1.8 to 5.5 V ( PD789860, 789860(A), 78E9860A), V = 1.8 to 3.6 V ( PD789861, 78E9861A)) Parameter Symbol Conditions MIN. TYP.
Page 193 CHAPTER 20 ELECTRICAL SPECIFICATIONS EEPROM Characteristics (T = –40 to +85°C, µ µ = 1.8 to 5.5 V ( PD789860, 789860(A), 78E9860A), V = 1.8 to 3.6 V ( PD789861, 78E9861A)) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 1...
Page 194 Notes 1. Time required to stabilize oscillation after a reset or STOP mode release. µ µ 2. This is fixed to 2 in the PD78E9860A. In the PD789860 and 789860(A), 2 or 2 can be selected by a mask option. 3. 2 , or 2 can be selected using bits 0 to 2 of the oscillation stabilization time selection register (OSTS0 to OSTS2).
Page 195: Chapter 21 Example Of Rc Oscillation Frequency Characteristics
CHAPTER 21 EXAMPLE OF RC OSCILLATION FREQUENCY CHARACTERISTICS (REFERENCE VALUES) µ vs. V (RC Oscillation: PD789861, R = 24 kΩ, C = 30 pF) = 25˚C) 24 kΩ 1.10 30 pF 1.05 Sample A Sample B 0.95 Sample C 0.90 Supply voltage V User’s Manual U14826EJ5V0UD...
Page 196: Chapter 22 Package Drawing
CHAPTER 22 PACKAGE DRAWING 20-PIN PLASTIC SSOP (7.62 mm (300)) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.13 mm of 6.65±0.15 its true position (T.P.) at maximum material condition. 0.475 MAX. 0.65 (T.P.) +0.08 0.24 −0.07 0.1±0.05...
Page 197: Chapter 23 Recommended Soldering Conditions
µ PD789860, 789860(A), 789861, 78E9860A, and 78E9861A should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website.
Page 198 CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS Table 23-1. Surface Mounting Type Soldering Conditions (2/2) µ PD78E9860AMC-5A4: 20-pin plastic SSOP (7.62 mm (300)) µ PD78E9861AMC-5A4: 20-pin plastic SSOP (7.62 mm (300)) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or IR35-103-2 Note higher), Count: Two times or less, Exposure limit: 3 days...
Page 199: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS µ The following development tools are available for development of systems using the PD789860, 789861 Subseries. Figure A-1 shows development tools. • Compatibility with PC98-NX series Unless stated otherwise, products which are supported by IBM PC/AT and compatibles can also be used with the PC98-NX series.
Page 200: A-1 Development Tools
APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools Software package · Software package Language processing software Debugging software · · Assembler package Integrated debugger · C compiler package · System simulator · Device file · Note 1 C library source file Control software ·...
Page 201: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0S This is a package that bundles the software tools required for development of the 78K/0S Series. Software package The following tools are included. RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, and device files µ Part number: S××××SP78K0S ××××...
Page 202: Control Software
APPENDIX A DEVELOPMENT TOOLS ×××× in the part number differs depending on the host machine and operating system to be used. Remark µ S××××RA78K0S µ S××××CC78K0S ×××× Host Machine Supply Media AB13 PC-9800 series, IBM PC/AT Japanese Windows 3.5” 2HD FD and compatibles BB13 English Windows...
Page 203: Debugging Tools (Hardware)
APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) IE-78K0S-NS In-circuit emulator for debugging hardware and software of application system using 78K/0S In-circuit emulator Series. Supports integrated debugger (ID78K0S-NS). Used in combination with AC adapter, emulation probe, and interface adapter for connecting the host machine. IE-78K0S-NS-A This in-circuit emulator has a coverage function in addition to the functions of the IE-78K0S- In-circuit emulator...
Page 204: Debugging Tools (Software)
APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) ID78K0S-NS This debugger supports the in-circuit emulators for the 78K/0S Series, IE-78K0S-NS and IE- Integrated debugger 78K0S-NS-A. ID78K0S-NS is Windows-based software. This debugger has enhanced debugging functions supporting C language. By using its window integration function that associates the source program, disassemble display, and memory display with trace results, the trace results can be displayed corresponding to the source program.
Page 205: Appendix B Notes On Target System Design
APPENDIX B NOTES ON TARGET SYSTEM DESIGN The following show the conditions when connecting the emulation probe to the conversion connector and conversion socket. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system.
Page 206: Appendix C Register Index
APPENDIX C REGISTER INDEX C.1 Register Name Index (in Alphabetical Order) Bit sequential buffer 10 data registers L, H (BSFRL10, BSFRH10)................132 Bit sequential buffer output control register 10 (BSFC10) ...................133 Carrier generator output control register 40 (TCA40) ....................91 EEPROM write control register 10 (EEWC10) ......................58 8-bit compare register 30 (CR30) ..........................87 8-bit compare register 40 (CR40) ..........................87 8-bit compare register H40 (CRH40)..........................87...
Page 207: Register Symbol Index (In Alphabetical Order)
APPENDIX C REGISTER INDEX C.2 Register Symbol Index (in Alphabetical Order) BSFC10: Bit sequential buffer output control register 10 ..................133 BSFRL10, BSFRH10: Bit sequential buffer 10 data registers L, H .....................132 CR30: 8-bit compare register 30 ..........................87 CR40: 8-bit compare register 40 ..........................87 CRH40: 8-bit compare register H40........................87 EEWC10:...
Page 208: Appendix D Revision History
Edition Description Applied to µ Change of PD789860, 789861 Subseries status from under development Throughout to development completed Modification of INTTMn0 timing in Figure 9-12 Timing of Interval Timer CHAPTER 9 8-BIT TIMER Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N >...
Page 209 SOLDERING CONDITIONS APPENDIX B NOTES ON TARGET SYSTEM DESIGN µ • Addition of 5 th PD789860(A) as a product name Throughout • Addition of 1.4 Quality Grade CHAPTER 1 GENERAL µ • Update of 1.6 78K/0S Series Lineup to latest version PD789860 SUBSERIES) •...
Page 210 APPENDIX D REVISION HISTORY (3/3) Edition Description Applied to • Modification of caution in Figure 14-3 Format of Interrupt Mask Flag 5 th CHAPTER 14 INTERRUPT Register 0 FUNCTIONS • Modification of a signal name in Figure 14-6 Timing of Non-Maskable Interrupt Request Acknowledgment •...

This manual is also suitable for:

Pd78e9861a Pd78e9860a Pd789860(a)Pd789861

NEC PD789860 User Manual

CHAPTER 1 GENERAL ( Μ PD789860 SUBSERIES)

Features

Applications

Ordering Information

Quality Grade

Pin Configuration (Top View)

0S Series Lineup

Block Diagram

Overview of Functions

Differences between Standard Quality Grade Products and (A) Products

CHAPTER 2 GENERAL ( Μ PD789861 SUBSERIES)

Features

Applications

Ordering Information

Pin Configuration (Top View)

0S Series Lineup

Block Diagram

Overview of Functions

Chapter 3 Pin Functions

Pin Function List

Description of Pin Functions

Pin I/O Circuits and Recommended Connection of Unused Pins

Chapter 4 Cpu Architecture

Memory Space

Processor Registers

Instruction Address Addressing

Operand Address Addressing

Chapter 5 Eeprom (Data Memory)

Memory Space

EEPROM Configuration

EEPROM Control Register

Notes for EEPROM Writing

Chapter 6 Port Functions

Port Configuration

Port Function Control Registers

Operation of Port Functions

CHAPTER 7 CLOCK GENERATOR ( Μ PD789860 SUBSERIES)

Clock Generator Functions

Clock Generator Configuration

Clock Generator Control Register

System Clock Oscillators

Clock Generator Operation

Changing Setting of CPU Clock

CHAPTER 8 CLOCK GENERATOR ( Μ PD789861 SUBSERIES)

Clock Generator Functions

Clock Generator Configuration

Clock Generator Control Register

System Clock Oscillators

Clock Generator Operation

Changing Setting of CPU Clock

Chapter 9 8-Bit Timers 30 and 40

8-Bit Timers 30, 40 Functions

8-Bit Timers 30, 40 Configuration

8-Bit Timers 30, 40 Control Registers

8-Bit Timers 30, 40 Operation

Notes on Using 8-Bit Timers 30, 40

Chapter 10 Watchdog Timer

Watchdog Timer Functions

Watchdog Timer Configuration

Watchdog Timer Control Registers

Watchdog Timer Operation

Chapter 11 Power-On-Clear Circuits

Power-On-Clear Circuit Functions

Power-On-Clear Circuit Configuration

Power-On-Clear Circuit Control Registers

Power-On-Clear Circuit Operation

Chapter 12 Bit Sequential Buffer

Bit Sequential Buffer Functions

Bit Sequential Buffer Configuration

Bit Sequential Buffer Control Register

Bit Sequential Buffer Operation

Chapter 13 Key Return Circuit

Key Return Circuit Function

Key Return Circuit Configuration and Operation

Chapter 14 Interrupt Functions

Interrupt Function Types

Interrupt Sources and Configuration

Interrupt Function Control Registers

Interrupt Servicing Operation