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Manuals and User Guides for Motorola DSP56309. We have
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Motorola DSP56309 manual available for free PDF download: User Manual
Motorola DSP56309 User Manual (425 pages)
24-Bit Digital Signal Processor
Brand:
Motorola
| Category:
Signal Processors
| Size: 2.1 MB
Table of Contents
Table of Contents
2
Dsp56309 Overview
6
List of Figures
20
Section 1 Dsp56309 Overview
30
Introduction
32
Manual Organization
32
Signal/Connection Descriptions
32
Manual Conventions
34
Table 1-1 High True/Low True Signal Conventions
34
Dsp56309 Features
35
Dsp56309 Core Description
36
General Features
36
Hardware Debugging Support
36
Reduced Power Dissipation
36
Data ALU
37
Data ALU Registers
37
Dsp56300 Core Functional Blocks
37
Address Generation Unit (AGU)
38
Multiplier-Accumulator (MAC)
38
Program Control Unit (PCU)
39
JTAG TAP and Once Module
40
PLL and Clock Oscillator
40
Memory Configuration
41
Off-Chip Memory Expansion
41
On-Chip Memory
41
Table 1-2 on Chip Memory
41
Internal Buses
42
Dsp56309 Block Diagram
43
Figure 1-1 DSP56309 Block Diagram
43
Direct Memory Access (Dma)
44
Dsp56309 Architecture Overview
44
GPIO Functionality
44
Enhanced Synchronous Serial Interface (ESSI)
45
Host Interface (HI08)
45
Serial Communications Interface (SCI)
45
Timer Module
46
Section 2 Signal/Connection Descriptions
48
Section 2 Signal/Connection Descriptions
49
Signal Groupings
50
Table 2-1 DSP56309 Functional Signal Groupings
50
Table 2-14 Serial Communication Interface (SCI)
50
Figure 2-1 Signals Identified by Functional Group
51
Power
52
Table 2-2 Power Inputs
52
Ground
53
Table 2-3 Grounds
53
Clock
54
Table 2-4 Clock Signals
54
Phase-Locked Loop (Pll)
55
Table 2-5 Phase-Locked Loop Signals
55
External Address Bus
56
External Memory Expansion Port (Port A)
56
Table 2-6 External Address Bus Signals
56
External Bus Control
57
External Data Bus
57
Table 2-7 External Data Bus Signals
57
Table 2-8 External Bus Control Signals
57
Interrupt and Mode Control
61
Table 2-9 Interrupt and Mode Control
61
Host Interface (Hi08)
63
Host Port Usage Considerations
63
Host Port Configuration
64
Table 2-10 Host Port Usage Considerations
64
Table 2-11 Host Interface
65
Enhanced Synchronous Serial Interface
71
Essi0
71
Table 2-12 Enhanced Synchronous Serial Interface 0 (ESSI0)
71
Essi1
74
Table 2-13 Enhanced Synchronous Serial Interface 1 (ESSI1)
75
Serial Communication Interface (Sci)
79
Timers
80
Table 2-15 Triple Timer Signals
81
Once/Jtag Interface
82
Table 2-16 Once/Jtag Interface
82
Section 3 Memory Configuration
86
Data Memory Spaces
88
Memory Spaces
88
Program Memory Space
88
Data Memory Space
89
Y Data Memory Space
89
Memory Space Configuration
90
Ram Configuration
90
Table 3-1 Memory Space Configuration Bit Settings for the DSP56309
90
Table 3-2 RAM Configuration Bit Settings for the DSP56309
90
On-Chip Program Memory (Program RAM)
91
On-Chip X Data Memory (X Data RAM)
91
Bootstrap ROM
92
Memory Configurations
92
Memory Space Configurations
92
On-Chip y Data Memory (y Data RAM)
92
Table 3-3 Memory Space Configurations for the DSP56309
92
RAM Configurations
93
Table 3-4 RAM Configurations for the DSP56309
93
Table 3-5 Memory Locations for Program RAM and Instruction Cache
93
Memory Maps
94
Table 3-6 Memory Locations for Data RAM
94
Figure 3-1 Default Settings (0, 0, 0)
95
Figure 3-2 Instruction Cache Enabled (0, 0, 1)
96
Figure 3-3 Switched Program RAM (0, 1, 0)
97
Figure 3-5 16-Bit Space with Default RAM (1, 0, 0)
99
Figure 3-6 16-Bit Space with Instruction Cache Enabled (1, 0, 1)
100
Figure 3-7 16-Bit Space with Switched Program RAM (1, 1, 0)
101
Figure 3-8 16-Bit Space, Switched Program RAM, Instruction Cache
102
Core Configuration
104
Section 4 Core Configuration
105
Introduction
106
Operating Modes
106
Bootstrap Program
107
Table 4-1 DSP56309 Operating Modes
107
Host Interface (Hi08)
108
Interrupt Sources and Priorities
112
Table 4-2 Interrupt Sources
113
Table 4-3 Interrupt Priority Level Bits
115
Figure 4-1 Interrupt Priority Register C (IPR-C) (X:$FFFFFF)
116
Figure 4-2 Interrupt Priority Register P (IPR-P) (X:$FFFFFE)
116
Table 4-4 Interrupt Source Priorities Within an IPL
117
Dma Request Sources
119
Table 4-5 DMA Request Sources
119
Figure 4-3 DSP56309 Operating Mode Register (OMR)
120
Operating Mode Register (Omr)
120
Device Identification Register (Idr)
121
Figure 4-4 PLL Control (PCTL) Register
121
Pll Control Register
121
Aa Control Registers (Aar0Ðaar3)
122
Figure 4-5 Identification Register Configuration (Revision 0)
122
Figure 4-6 Address Attribute Registers (AAR0ÐAAR3)
123
Jtag Boundary Scan Register (Bsr)
123
Enhanced Synchronous Serial Interface
126
Serial Communication Interface (Sci)
127
Section 6 Host Interface (Hi08)
129
Hi08 Features
130
Introduction
130
Hi08 Host Port Signals
133
Table 6-1 HI08 Signal Definitions for Various Operational Modes
133
Table 6-2 HI08 Data Strobe Signals
133
Table 6-3 HI08 Host Request Signals
133
Figure 6-1 HI08 Block Diagram
134
Hi08 Block Diagram
134
Hi08 Dsp Side Programmerõs Model
135
Figure 6-2 Host Control Register (HCR) (X:$FFFFC2)
136
Table 6-4 Host Command Interrupt Priority List
137
Figure 6-3 Host Status Register (HSR) (X:$FFFFC3)
138
Figure 6-4 Host Base Address Register (HBAR) (X:$FFFFC5)
139
Figure 6-5 Self Chip Select Logic
139
Figure 6-6 Host Port Control Register (HPCR) (X:$FFFFC4)
140
Figure 6-7 Single Strobe Bus
142
Figure 6-8 Dual Strobe Bus
143
Figure 6-10 Host Data Register (HDR) (X:$FFFFC9)
144
Figure 6-9 Host Data Direction Register (HDDR) (X:$FFFFC8)
144
Table 6-5 HDR and HDDR Functionality
145
Table 6-6 DSP Side Registers after Reset
146
Figure 6-11 HSR-HCR Operation
147
Hi08-External Host Programmerõs Model
147
Figure 6-12 Interface Control Register
149
Table 6-7 Host Side Register Map
149
Table 6-8 TREQ and RREQ Modes (HDRQ = 0)
150
Table 6-9 TREQ and RREQ Modes (HDRQ = 1)
150
Figure 6-13 Command Vector Register (CVR)
152
Table 6-10 INIT Command Effects
152
Figure 6-14 Interface Status Register
153
Figure 6-15 Interrupt Vector Register (IVR)
155
Table 6-11 HREQ and HDRQ Settings
155
Table 6-12 Host Side Registers after Reset
157
Servicing the Host Interface
158
Figure 6-16 HI08 Host Request Structure
160
Hi08 Programming Model Quick Reference
161
Figure 7-1 ESSI Block Diagram
170
Table 7-1 ESSI Clock Sources
173
Figure 7-2 ESSI Control Register a (CRA)
174
Figure 7-3 ESSI Control Register B (CRB)
174
Figure 7-4 ESSI Status Register (SSISR)
174
Figure 7-5 ESSI Transmit Slot Mask Register a (TSMA)
175
Figure 7-6 ESSI Transmit Slot Mask Register B (TSMB)
175
Figure 7-7 ESSI Receive Slot Mask Register a (RSMA)
175
Figure 7-8 ESSI Receive Slot Mask Register B (RSMB)
175
Figure 7-9 ESSI Clock Generator Functional Block Diagram
177
Figure 7-10 ESSI Frame Sync Generator Functional Block Diagram
178
Table 7-2 ESSI Word Length Selection
179
Table 7-3 FSL1 and FSL0 Encoding
182
Figure 7-11 CRB FSL0 and FSL1 Bit Operation (FSR = 0)
184
Figure 7-12 CRB SYN Bit Operation
185
Figure 7-14 Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame)
187
Figure 7-15 Network Mode, External Frame Sync (8 Bit, 2 Words in Frame)
188
Table 7-4 Mode and Signal Definition Table
189
Figure 7-16 ESSI Data Path Programming Model (SHFD = 0)
196
Figure 7-17 ESSI Data Path Programming Model (SHFD = 1)
197
Figure 7-18 Port Control Register (PCR) (PCRC X:$FFFFBF)
209
Figure 7-19 Port Direction Register (PRR)(PRRC X:$FFFFBE)
209
Figure 7-20 Port Data Register (PDR) (PDRC X:$FFFFBD)
210
Table 7-5 Port Control Register and Port Direction Register Bits
210
Figure 8-1 SCI Control Register (SCR)
216
Figure 8-2 SCI Status Register (SSR)
216
Figure 8-4 SCI Data Word Formats
217
Table 8-1 Word Formats
219
Figure 8-3 SCI Clock Control Register (SCCR)
226
Figure 8-5 16 X Serial Clock
227
Table 8-2 TCM and RCM Bit Configuration
228
Figure 8-6 SCI Baud Rate Generator
229
Figure 8-7 SCI Programming Model Data Registers
230
Table 8-3 SCI Registers after Reset
234
Figure 8-8 Port E Control Register (PCRE)
238
Figure 8-9 Port E Direction Register (PRRE)
239
Table 8-4 Port Control Register and Port Direction Register Bits
239
Figure 8-10 Port E Data Register (PDRE)
240
Section 9 Triple Timer Module
243
Introduction
244
Triple Timer Module Architecture
244
Figure 9-1 Triple Timer Module Block Diagram
245
Figure 9-2 Timer Module Block Diagram
246
Triple Timer Module Programming Model
246
Figure 9-3 Timer Module Programmerõs Model
247
Figure 9-4 Timer Prescaler Load Register (TPLR)
248
Figure 9-5 Timer Prescaler Count Register (TPCR)
249
Table 9-1 Prescaler Source Selection
249
Figure 9-6 Timer Control/Status Register
250
Table 9-2 Timer Control Bits
251
Table 9-3 Inverter (INV) Bit Operation
253
Timer Operational Modes
257
On-Chip Emulation Module
270
Section 10 On-Chip Emulation Module
271
Jtag Port
271
Figure 10-1 Once Module Block Diagram
272
Introduction
272
Once Module Signals
272
Figure 10-2 Once Module Multiprocessor Configuration
273
Once Controller
273
Figure 10-3 Once Controller Block Diagram
274
Figure 10-4 Once Command Register
274
Table 10-1 EX Bit Definition
275
Table 10-2 GO Bit Definition
275
Table 10-3 R/W Bit Definition
275
Table 10-4 Once Register Select Encoding
275
Figure 10-5 Once Status and Control Register (OSCR)
277
Table 10-5 Core Status Bits Description
278
Once Memory Breakpoint Logic
278
Figure 10-6 Once Memory Breakpoint Logic 0
279
Figure 10-7 Once Breakpoint Control Register (OBCR)
281
Table 10-6 Memory Breakpoint 0 and 1 Select Table
281
Table 10-7 Breakpoint 0 Read/Write Select Table
282
Table 10-8 Breakpoint 0 Condition Select Table
282
Table 10-9 Breakpoint 1 Read/Write Select Table
282
Table 10-10 Breakpoint 1 Condition Select Table
283
Table 10-11 Breakpoint 0 and 1 Event Select Table
283
Figure 10-8 Once Trace Logic Block Diagram
284
Once Trace Logic
284
Methods of Entering Debug Mode
285
Pipeline Information and Ogdb Register
287
Figure 10-9 Once Pipeline Information and GDB Registers
288
Debugging Resources
289
Figure 10-10 Once Trace Buffer
291
10.10 Serial Protocol Description
291
10.11 Target Site Debug System Requirements
292
10.12 Once MODULE EXAMPLES
292
10.13 JTAG Port/Once MODULE INTERACTION
298
Table 10-12 TMS Sequencing for DEBUG_REQUEST
299
Table 10-13 TMS Sequencing for ENABLE_ONCE
300
Table 10-14 TMS Sequencing for Reading Pipeline Registers
300
Section 11 Jtag Port
303
Introduction
304
Figure 11-1 TAP Block Diagram
305
Jtag Signals
305
Figure 11-2 TAP Controller State Machine
307
Tap Controller
307
Figure 11-3 JTAG Instruction Register
308
Table 11-1 JTAG Instructions
309
Figure 11-4 JTAG ID Register
310
Figure 11-5 Bypass Register
312
Dsp56300 Restrictions
313
Dsp56309 Boundary Scan Register
314
Table D-1 Internal I/O Memory Map
373
Table D-2 Interrupt Sources
380
Table D-3 Interrupt Source Priorities Within an IPL
382
Figure D-1 Status Register (SR
384
Figure D-2 Operating Mode Register (OMR
385
Figure D-3 Interrupt Priority Registerðcore (IPRÐC
386
Figure D-4 Interrupt Priority Register Ð Peripherals (IPRÐP
387
Figure D-5 Phase-Locked Loop Control Register (PCTL
388
Figure D-6 Host Receive and Host Transmit Data Registers
389
Figure D-7 Host Control and Host Status Registers
390
Figure D-8 Host Base Address and Host Port Control Registers
391
Figure D-9 Interrupt Control and Interrupt Status Registers
392
Figure D-10 Interrupt Vector and Command Vector Registers
393
Figure D-11 Host Receive and Host Transmit Data Registers
394
Figure D-12 ESSI Control Register a (CRA
395
Figure D-13 ESSI Control Register B (CRB
396
Figure D-14 ESSI Status Register (SSISR
397
Figure D-15 ESSR Transmit and Receive Slot Mask Registers (TSM, RSM
398
Figure D-16 SCI Control Register (SCR
399
Figure D-17 SCI Status and Clock Control Registers (SSR, SCCR
400
Figure D-18 SCI Receive and Transmit Data Registers (SRX, TRX
401
Figure D-19 Timer Prescaler Load/Count Register (TPLR, TPCR
402
Figure D-20 Timer Control/Status Register (TCSR
403
Figure D-21 Timer Load, Compare, Count Registers (TLR, TCPR, TCR
404
Figure D-23 Port C Registers (PCRC, PRRC, PDRC
406
Figure D-24 Port D Registers (PCRD, PRRD, PDRD
407
Table 11-2 DSP56309 BSR Bit Definitions
314
Signal/Connection Descriptions
424
Memory Configuration
425
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