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Epson S1D13706 Manuals
Manuals and User Guides for Epson S1D13706. We have
3
Epson S1D13706 manuals available for free PDF download: Technical Manual, User Manual
Epson S1D13706 Technical Manual (672 pages)
embedded Memory LCD Controller
Brand:
Epson
| Category:
Controller
| Size: 5.78 MB
Table of Contents
Table of Contents
9
Riesstrasse
3
Introduction
17
Overview Description
17
Features
18
Integrated Frame Buffer
18
Display Features
19
Display Modes
19
Figure 3-1: Typical System Diagram (Generic #1 Bus)
20
Figure 3-2: Typical System Diagram (Generic #2 Bus)
20
Typical System Implementation Diagrams
20
Figure 3-3: Typical System Diagram (Hitachi SH-4 Bus)
21
Figure 3-4: Typical System Diagram (Hitachi SH-3 Bus)
21
Figure 3-5: Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000)
22
Figure 3-6: Typical System Diagram (MC68K #2, Motorola 32-Bit 68030)
22
Figure 3-7: Typical System Diagram (Motorola REDCAP2 Bus)
23
Figure 3-8: Typical System Diagram (Motorola MC68EZ328/MC68VZ328 "Dragonball" Bus)
23
Pinout Diagram - TQFP15 - 100Pin
24
Figure 4-1: Pinout Diagram - TQFP15 - 100Pin (S1D13706F00A)
24
Table 4-1: CFLGA Pin Mapping
25
Pinout Diagram - CFLGA - 104Pin
25
Figure 4-2: Pinout Diagram - CFLGA - 104Pin (S1D13706B00A)
25
Pinout Diagram - die Form
26
Figure 4-3: Pinout Diagram - die Form (S1D13706D00A)
26
Table 4-2: Pinout Assignments - die Form (S1D13706D00A)
27
Table 4-3: Host Interface Pin Descriptions
28
Host Interface
28
Table 4-4: LCD Interface Pin Descriptions
32
Table 4-5: Clock Input Pin Descriptions
34
Table 4-6: Miscellaneous Pin Descriptions
34
Table 4-7: Power and Ground Pin Descriptions
34
Table 4-8: Summary of Power-On/Reset Options
35
Summary of Configuration Options
35
Table 4-9: Host Bus Interface Pin Mapping
36
Table 4-10: LCD Interface Pin Mapping
37
Table 5-1: Absolute Maximum Ratings
38
Table 5-2: Recommended Operating Conditions
38
Table 5-3: Electrical Characteristics for VDD = 3.3V Typical
38
D.C. Characteristics
38
Table 6-1: Clock Input Requirements for CLKI When CLKI to BCLK Divide > 1
39
Figure 6-1: Clock Input Requirements
39
A.C. Characteristics
39
Clock Timing
39
Input Clocks
39
Table 6-2: Clock Input Requirements for CLKI When CLKI to BCLK Divide = 1
40
Table 6-3: Clock Input Requirements for CLKI2
40
Internal Clocks
41
Table 6-4: Internal Clock Requirements
41
CPU Interface Timing
42
Figure 6-2: Generic #1 Interface Timing
42
Table 6-5: Generic #1 Interface Timing
43
Figure 6-3: Generic #2 Interface Timing
44
Table 6-6: Generic #2 Interface Timing
45
Figure 6-4: Hitachi SH-4 Interface Timing
46
Table 6-7: Hitachi SH-4 Interface Timing
47
Figure 6-5: Hitachi SH-3 Interface Timing
48
Table 6-8: Hitachi SH-3 Interface Timing
49
Figure 6-6: Motorola MC68K #1 Interface Timing
50
Table 6-9: Motorola MC68K #1 Interface Timing
51
Figure 6-7: Motorola MC68K #2 Interface Timing
52
Table 6-10: Motorola MC68K #2 Interface Timing
53
Figure 6-8: Motorola REDCAP2 Interface Timing
54
Table 6-11: Motorola REDCAP2 Interface Timing
55
Figure 6-9: Motorola Dragonball Interface with DTACK Timing
56
Table 6-12: Motorola Dragonball Interface with DTACK Timing
57
Figure 6-10: Motorola Dragonball Interface Without DTACK# Timing
58
Table 6-13: Motorola Dragonball Interface Without DTACK Timing
59
Figure 6-11: Passive/Tft Power-On Sequence Timing
60
LCD Power Sequencing
60
Table 6-14: Passive/Tft Power-On Sequence Timing
60
Figure 6-12: Passive/Tft Power-Off Sequence Timing
61
Table 6-15: Passive/Tft Power-Off Sequence Timing
61
Figure 6-13: Panel Timing Parameters
62
Display Interface
62
Table 6-16: Panel Timing Parameter Definition and Register Summary
63
Figure 6-14: Generic STN Panel Timing
64
Issue Date: 01/11/13 Page
65
Figure 6-15: Single Monochrome 4-Bit Panel Timing
66
Table 6-17: Single Monochrome 4-Bit Panel A.C. Timing
67
Figure 6-16: Single Monochrome 4-Bit Panel A.C. Timing
67
Figure 6-17: Single Monochrome 8-Bit Panel Timing
68
Table 6-18: Single Monochrome 8-Bit Panel A.C. Timing
69
Figure 6-18: Single Monochrome 8-Bit Panel A.C. Timing
69
Figure 6-19: Single Color 4-Bit Panel Timing
70
Table 6-19: Single Color 4-Bit Panel A.C. Timing
71
Figure 6-20: Single Color 4-Bit Panel A.C. Timing
71
Figure 6-21: Single Color 8-Bit Panel Timing (Format 1)
72
Table 6-20: Single Color 8-Bit Panel A.C. Timing (Format 1)
73
Figure 6-22: Single Color 8-Bit Panel A.C. Timing (Format 1)
73
Single Color 8-Bit Panel Timing (Format 2)
74
Figure 6-23: Single Color 8-Bit Panel Timing (Format 2)
74
Table 6-21: Single Color 8-Bit Panel A.C. Timing (Format 2)
75
Figure 6-24: Single Color 8-Bit Panel A.C. Timing (Format 2)
75
Figure 6-25: Single Color 16-Bit Panel Timing
76
Table 6-22: Single Color 16-Bit Panel A.C. Timing
77
Figure 6-26: Single Color 16-Bit Panel A.C. Timing
77
Figure 6-27: Generic TFT Panel Timing
78
Figure 6-28: 18-Bit TFT Panel Timing
79
Figure 6-29: TFT A.C. Timing
80
Table 6-23: TFT A.C. Timing
81
Figure 6-30: 160X160 Sharp 'Direct' HR-TFT Panel Horizontal Timing
82
X160 Sharp 'Direct' Hr-Tft Panel Timing (E.g. Lq031B1Ddxx)
82
Table 6-24: 160X160 Sharp 'Direct' HR-TFT Horizontal Timing
83
Figure 6-31: 160X160 Sharp 'Direct' HR-TFT Panel Vertical Timing
84
Table 6-25: 160X160 Sharp 'Direct' HR-TFT Panel Vertical Timing
85
Figure 6-32: 320X240 Sharp 'Direct' HR-TFT Panel Horizontal Timing
86
X240 Sharp 'Direct' Hr-Tft Panel Timing (E.g. Lq039Q2Ds)
86
Figure 6-33: 320X240 Sharp 'Direct' HR-TFT Panel Vertical Timing
87
Table 6-26: 320X240 Sharp 'Direct' HR-TFT Panel Horizontal Timing
87
Table 6-27: 320X240 Sharp 'Direct' HR-TFT Panel Vertical Timing
87
Figure 6-34: 160X240 Epson D-TFD Panel Horizontal Timing
88
X240 Epson D-Tfd Panel Timing (E.g. Lf26Scr)
88
Table 6-28: 160X240 Epson D-TFD Panel Horizontal Timing
89
Figure 6-35: 160X240 Epson D-TFD Panel GCP Horizontal Timing
90
Table 6-29: 160X240 Epson D-TFD Panel GCP Horizontal Timing
90
Figure 6-36: 160X240 Epson D-TFD Panel Vertical Timing
91
Table 6-30: 160X240 Epson D-TFD Panel Vertical Timing
91
Figure 6-37: 320X240 Epson D-TFD Panel Horizontal Timing
92
X240 Epson D-Tfd Panel Timing (E.g. Lf37Sqr)
92
Table 6-31: 320X240 Epson D-TFD Panel Horizontal Timing
93
Figure 6-38: 320X240 Epson D-TFD Panel GCP Horizontal Timing
94
Table 6-32: 320X240 Epson D-TFD Panel GCP Horizontal Timing
94
Figure 6-39: 320X240 Epson D-TFD Panel Vertical Timing
95
Table 6-33: 320X240 Epson D-TFD Panel Vertical Timing
95
Table 7-1: BCLK Clock Selection
96
Table 7-2: MCLK Clock Selection
96
Clocks
96
Clock Descriptions
96
Table 7-3: PCLK Clock Selection
97
Pclk
97
Pwmclk
98
Table 7-4: Relationship between MCLK and PCLK
98
Table 7-5: PWMCLK Clock Selection
98
Figure 7-1: Clock Selection
99
Table 7-6: S1D13706 Internal Clock Requirements
100
Clocks Versus Functions
100
Registers
101
Register Mapping
101
Table 8-1: S1D13706 Register Set
101
Register Descriptions
102
Read-Only Configuration Registers
102
Clock Configuration Registers
103
Table 8-2: MCLK Divide Selection
103
Table 8-3: PCLK Divide Selection
104
Table 8-4: PCLK Source Selection
104
Look-Up Table Registers
105
Panel Configuration Registers
107
Table 8-5: Panel Data Width Selection
108
Table 8-6: Active Panel Resolution Selection
108
Table 8-7: LCD Panel Type Selection
108
Display Mode Registers
115
Table 8-8: Inverse Video Mode Select Options
116
Table 8-9: LCD Bit-Per-Pixel Selection
117
Figure 8-1: Display Data Byte/Word Swap
118
Table 8-10: Swivelview TM Mode Select Options
118
Table 8-11: 32-Bit Address Increments for Color Depth
122
Table 8-12: 32-Bit Address Increments for Color Depth
123
Table 8-13: 32-Bit Address Increments for Color Depth
124
Table 8-14: 32-Bit Address Increments for Color Depth
125
Miscellaneous Registers
126
General IO Pins Registers
128
Figure 8-2: PWM Clock/CV Pulse Block Diagram
132
Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers
132
Table 8-15: PWM Clock Control
132
Table 8-16: CV Pulse Control
133
Table 8-17: PWM Clock Divide Select Options
134
Table 8-18: CV Pulse Divide Select Options
134
Table 8-19: PWMOUT Duty Cycle Select Options
135
Frame Rate Calculation
136
Figure 10-1: 4/8/16 Bit-Per-Pixel Display Data Memory Organization
137
Display Data Formats
137
Figure 11-1: 1 Bit-Per-Pixel Monochrome Mode Data Output Path
138
Figure 11-2: 2 Bit-Per-Pixel Monochrome Mode Data Output Path
138
Look-Up Table Architecture
138
Monochrome Modes
138
Figure 11-3: 4 Bit-Per-Pixel Monochrome Mode Data Output Path
139
Figure 11-4: 8 Bit-Per-Pixel Monochrome Mode Data Output Path
139
Figure 11-5: 1 Bit-Per-Pixel Color Mode Data Output Path
140
Color Modes
140
Figure 11-6: 2 Bit-Per-Pixel Color Mode Data Output Path
141
Figure 11-7: 4 Bit-Per-Pixel Color Mode Data Output Path
142
Figure 11-8: 8 Bit-Per-Pixel Color Mode Data Output Path
143
Figure 12-1: Relationship between the Screen Image and the Image Refreshed in 90° Swivelview
144
Concept
144
Register Programming
145
Register Programming
146
Register Programming
148
Figure 13-1: Picture-In-Picture Plus with Swivelview Disabled
149
Figure 13-2: Picture-In-Picture Plus with Swivelview 90° Enabled
150
Figure 13-3: Picture-In-Picture Plus with Swivelview 180° Enabled
150
Figure 13-4: Picture-In-Picture Plus with Swivelview 270° Enabled
151
Big-Endian Bus Interface 14.1 Byte Swapping Bus Data
152
Bpp Color Depth
153
Figure 14-1: Byte-Swapping for 16 Bpp
153
Bpp Color Depth
154
Figure 14-2: Byte-Swapping for 1/2/4/8 Bpp
154
Table 15-1: Power Save Mode Function Summary
155
Figure 16-1: Mechanical Data 100Pin TQFP15 (S1D13706F00A)
156
Figure 16-2: Mechanical Data 104Pin CFLGA (S1D13706B00A)
157
References
158
Sales and Technical Support
159
Table of Contents
163
1 Introduction
169
2 Initialization
170
3 Memory Models
174
Display Buffer Location
174
Memory Organization for One Bit-Per-Pixel (2 Colors/Gray Shades)
174
Memory Organization for Two Bit-Per-Pixel (4 Colors/Gray Shades)
175
Memory Organization for Four Bit-Per-Pixel (16 Colors/Gray Shades)
175
Memory Organization for 8 Bpp (256 Colors/64 Gray Shades)
176
Memory Organization for 16 Bpp (65536 Colors/64 Gray Shades)
176
4 Look-Up Table (LUT)
177
Registers
177
Look-Up Table Write Registers
177
Look-Up Table Read Registers
178
Look-Up Table Organization
179
Gray Shade Modes
180
Color Modes
182
5 Power Save Mode
186
Overview
186
Registers
187
Memory Controller Power Save Status
187
Power Save Mode Enable
187
Enabling Power Save Mode
188
Disabling Power Save Mode
188
6 LCD Power Sequencing
189
Enabling the LCD Panel
190
Disabling the LCD Panel
190
7 Swivelview
191
Registers
192
Examples
193
Limitations
196
Swivelview 0° and 180
196
Swivelview 90° and 270
196
8 Picture-In-Picture Plus
197
Concept
197
Registers
197
Picture-In-Picture-Plus Examples
208
Swivelview 0° (Landscape Mode)
208
Swivelview 90
211
Swivelview 180
214
Swivelview 270
217
Limitations
220
Swivelview 0° and 180
220
Swivelview 90° and 270
220
9 Identifying the S1D13706
221
10 Hardware Abstraction Layer (HAL)
222
API for 13706HAL
222
Initialization
225
General HAL Support
228
Advance HAL Functions
235
Surface Support
236
Register Access
240
Memory Access
242
Color Manipulation
244
Virtual Display
247
Drawing
249
Register/Display Memory
255
Porting LIBSE to a New Target Platform
256
Building the LIBSE Library for SH3 Target Example
257
11 Sample Code
258
Table of Contents
263
13706Cfg
265
S1D13706 Supported Evaluation Platforms
265
Installation
266
Usage
266
13706CFG Configuration Tabs
267
General Tab
267
Preferences Tab
269
Clocks Tab
270
Panel Tab
274
Panel Power Tab
278
Registers Tab
279
13706CFG Menus
280
Open
280
Save
281
Save as
281
Configure Multiple
282
Export
283
Enable Tooltips
284
ERD on the Web
284
About 13706CFG
284
Comments
284
Installation Guide
369
Manual/Software Adjustable LCD Panel Negative Power Supply (Vlcd)
379
List of Figures
381
1 Introduction
383
2 Features
384
3 Installation and Configuration
385
Configuration DIP Switches
385
Configuration Jumpers
387
4 CPU Interface
391
CPU Interface Pin Mapping
391
CPU Bus Connector Pin Mapping
392
5 LCD Interface Pin Mapping
394
6 Technical Description
396
PCI Bus Support
396
Direct Host Bus Interface Support
396
S1D13706 Embedded Memory
396
Manual/Software Adjustable LCD Panel Positive Power Supply (VDDH)
396
Manual/Software Adjustable LCD Panel Negative Power Supply (VLCD)
397
Software Adjustable LCD Backlight Intensity Support Using PWM
398
Passive/Active LCD Panel Support
398
Buffered LCD Connector
398
Extended LCD Connector
398
7 Clock Synthesizer and Clock Options
399
Clock Programming
399
8 References
400
Documents
400
Document Sources
400
9 Parts List
401
10 Schematics
404
11 Board Layout
410
12 Technical Support
411
EPSON LCD Controllers (S1D13706)
411
Table of Contents
415
1 Introduction
419
2 Interfacing to the TMPR3905/12
420
The Toshiba TMPR3905/12 System Bus
420
Card Access Cycles
420
Overview
420
3 S1D13706 Host Bus Interface
422
Host Bus Interface Pin Mapping
422
Host Bus Interface Signals
423
4 Toshiba TMPR3905/12 to S1D13706 Interface
424
Hardware Description
424
S1D13706 Hardware Configuration
426
Memory Mapping and Aliasing
426
5 Software
427
6 References
428
Documents
428
Document Sources
428
7 Technical Support
429
EPSON LCD Controllers (S1D13706)
429
Toshiba MIPS TMPR3905/12 Processor
429
Table of Contents
433
1 Introduction
437
2 Interfacing to the PC Card Bus
438
The PC Card System Bus
438
Memory Access Cycles
438
PC Card Overview
438
3 S1D13706 Host Bus Interface
440
Host Bus Interface Pin Mapping
440
Host Bus Interface Signals
441
4 PC Card to S1D13706 Interface
442
Hardware Connections
442
S1D13706 Hardware Configuration
443
Register/Memory Mapping
443
5 Software
444
6 References
445
Documents
445
Document Sources
445
7 Technical Support
446
EPSON LCD Controllers (S1D13706)
446
PC Card Standard
446
Power Consumption
447
Table of Contents
455
1 Introduction
459
2 Interfacing to the NEC VR4102/VR4111
460
The NEC VR41XX System Bus
460
Overview
460
LCD Memory Access Cycles
461
3 S1D13706 Host Bus Interface
462
Host Bus Interface Pin Mapping
462
Host Bus Interface Signals
463
4 VR4102/VR4111 to S1D13706 Interface
464
Hardware Description
464
S1D13706 Hardware Configuration
465
NEC VR4102/VR4111 Configuration
466
5 Software
467
6 References
468
Documents
468
Document Sources
468
7 Technical Support
469
Epson LCD Controllers (S1D13706)
469
NEC Electronics Inc
469
Table of Contents
473
1 Introduction
477
2 Interfacing to the NEC VR4181A
478
The NEC VR4181A System Bus
478
Overview
478
LCD Memory Access Signals
479
3 S1D13706 Host Bus Interface
480
Host Bus Interface Pin Mapping
480
Host Bus Interface Signals
481
4 VR4181A to S1D13706 Interface
482
Hardware Description
482
S1D13706 Hardware Configuration
483
NEC VR4181A Configuration
484
5 Software
485
6 References
486
Documents
486
Document Sources
486
7 Technical Support
487
Epson LCD Controllers (S1D13706)
487
NEC Electronics Inc
487
Table of Contents
491
1 Introduction
495
2 Interfacing to the MPC821
496
The MPC8XX System Bus
496
MPC8XX Bus Overview
496
Normal (Non-Burst) Bus Transactions
497
Burst Cycles
498
Memory Controller Module
499
General-Purpose Chip Select Module (GPCM)
499
User-Programmable Machine (UPM)
500
3 S1D13706 Host Bus Interface
501
Host Bus Interface Pin Mapping
501
Host Bus Interface Signals
502
4 MPC821 to S1D13706 Interface
503
Hardware Description
503
MPC821ADS Evaluation Board Hardware Connections
504
S1D13706 Hardware Configuration
506
Register/Memory Mapping
506
MPC821 Chip Select Configuration
507
Test Software
508
5 Software
509
6 References
510
Documents
510
Document Sources
510
7 Technical Support
511
EPSON LCD/CRT Controllers (S1D13706)
511
Motorola MPC821 Processor
511
Table of Contents
515
1 Introduction
519
2 Interfacing to the MCF5307
520
The MCF5307 System Bus
520
Normal (Non-Burst) Bus Transactions
520
Overview
520
Burst Cycles
521
Chip-Select Module
522
3 S1D13706 Host Bus Interface
523
Host Bus Interface Pin Mapping
523
Host Bus Interface Signals
524
4 MCF5307 to S1D13706 Interface
525
Hardware Description
525
S1D13706 Hardware Configuration
526
Register/Memory Mapping
527
MCF5307 Chip Select Configuration
527
5 Software
528
6 References
529
Documents
529
Document Sources
529
7 Technical Support
530
EPSON LCD Controllers (S1D13706)
530
Motorola MCF5307 Processor
530
Table of Contents
533
1 Introduction
537
2 Connecting to the Sharp LQ039Q2DS01 HR-TFT
538
External Power Supplies
538
Gray Scale Voltages for Gamma Correction
538
DC Gate Driver Power Supplies
539
Digital/Analog Power Supplies
539
AC Gate Driver Power Supplies
540
HR-TFT MOD Signal
541
S1D13706 to LQ039Q2DS01 Pin Mapping
542
3 Connecting to the Sharp Lq031B1Ddxx HR-TFT
544
External Power Supplies
544
Gray Scale Voltages for Gamma Correction
544
AC Gate Driver Power Supplies
545
DC Gate Driver Power Supplies
545
Digital/Analog Power Supplies
545
HR-TFT MOD Signal
545
S1D13706 to Lq031B1Ddxx Pin Mapping
546
4 Test Software
548
5 References
549
Documents
549
Document Sources
549
6 Technical Support
550
EPSON LCD Controllers (S1D13706)
550
Sharp HR-TFT Panel
550
Table of Contents
553
1 Introduction
557
2 Motorola MC68030 Bus Interface
558
Overview
558
Dynamic Bus Sizing
558
Asynchronous / Synchronous Bus Operation
558
3 S1D13706 Host Bus Interface
560
Host Bus Interface Pin Mapping
560
Host Bus Interface Signals
561
4 MC68030 to S1D13706 Interface
562
Hardware Description
562
S1D13706 Hardware Configuration
563
Register/Memory Mapping
563
5 Software
564
6 References
565
Documents
565
Document Sources
565
7 Technical Support
566
EPSON LCD/CRT Controllers (S1D13706)
566
Motorola MC68030 Processor
566
LCD Pin Mapping for Horizontal Connector (Lf37Sqt and Lf26Sct)
569
1 Introduction
573
2 External Power Supplies
574
VDDH and VDD - Horizontal and Vertical Analog Voltages
574
VEEY - LCD Panel Drive Voltage for Vertical Power Supplies - Brightness Reference
575
VCC - Horizontal Logic Power Supply
577
Swing Power Supply for the Vertical Drive (V0Y) and Logic (VCCY / V5Y) Voltages
578
Level Shift and Clamp Circuit for Vertical Logic Control Signals
579
3 S1D13706 to D-TFD Panel Pin Mapping
580
LCD Pin Mapping for Horizontal Connector (LF37SQT and LF26SCT)
581
LCD Pin Mapping for y Connector (LF37SQT)
582
LCD Pin Mapping for y Connector (LF26SCT)
583
4 Power-On/Off Sequence
584
5 GCP Data Signal
585
GCP Data Structure
585
Programming GCP Data
586
6 Test Software
587
7 References
588
Documents
588
Document Sources
588
8 Technical Support
589
EPSON LCD Controllers (S1D13706)
589
Table of Contents
593
1 Introduction
597
2 Interfacing to the REDCAP2
598
The REDCAP2 System Bus
598
Overview
598
Bus Transactions
598
3 S1D13706 Host Bus Interface
600
Host Bus Interface Pin Mapping
600
Host Bus Interface Signals
601
4 REDCAP2 to S1D13706 Interface
602
Hardware Description
602
Hardware Connections
603
S1D13706 Hardware Configuration
605
Register/Memory Mapping
605
REDCAP2 Chip Select Configuration
606
5 Software
607
6 References
608
Documents
608
Document Sources
608
7 Technical Support
609
EPSON LCD/CRT Controllers (S1D13706)
609
Motorola REDCAP2 Processor
609
Table of Contents
613
1 Introduction
617
2 Interfacing to an 8-Bit Processor
618
The Generic 8-Bit Processor System Bus
618
3 S1D13706 Host Bus Interface
619
Host Bus Interface Pin Mapping
619
Host Bus Interface Signals
620
8 Bit Processor to S1D13706 Interface
621
Hardware Connections
621
S1D13706 Hardware Configuration
622
Register/Memory Mapping
622
5 Software
623
6 References
624
Documents
624
Document Sources
624
7 Technical Support
625
EPSON LCD Controllers (S1D13706)
625
Section 16
629
1 Introduction
633
2 Interfacing to the MC68VZ328
634
The MC68VZ328 System Bus
634
Chip-Select Module
634
3 S1D13706 Host Bus Interface
635
Host Bus Interface Pin Mapping
635
Host Bus Interface Signals
636
4 MC68VZ328 to S1D13706 Interface
637
Hardware Description
637
S1D13706 Hardware Configuration
638
MC68VZ328 Chip Select and Pin Configuration
639
Register/Memory Mapping
639
5 Software
640
6 References
641
Documents
641
Document Sources
641
7 Technical Support
642
EPSON LCD/CRT Controllers (S1D13706)
642
Motorola MC68VZ328 Processor
642
Introduction
647
Package Description
648
Routing
649
Perimeter Pads
649
Inner Pads
650
References
651
Document Sources
651
Documents
651
Technical Support
652
EPSON LCD Controllers (S1D13706)
652
Section 17
655
1 Introduction
659
2 Interfacing to the Strongarm SA-1110 Bus
660
The Strongarm SA-1110 System Bus
660
Strongarm SA-1110 Overview
660
Variable-Latency IO Access Overview
660
Variable-Latency IO Access Cycles
661
3 S1D13706 Host Bus Interface
663
Host Bus Interface Pin Mapping
663
Host Bus Interface Signal Descriptions
664
4 Strongarm SA-1110 to S1D13706 Interface
665
Hardware Description
665
S1D13706 Hardware Configuration
666
Strongarm SA-1110 Register Configuration
667
Register/Memory Mapping
668
5 Software
669
6 References
670
Documents
670
Document Sources
670
7 Technical Support
671
EPSON LCD Controllers (S1D13706)
671
Intel Strongarm SA-1110 Processor
671
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Epson S1D13706 User Manual (29 pages)
Brand:
Epson
| Category:
Motherboard
| Size: 0.38 MB
Table of Contents
User Manual
1
Table of Contents
3
1 Introduction
5
2 Features
6
3 Installation and Configuration
7
Configuration DIP Switches
7
Configuration Jumpers
9
4 CPU Interface
11
CPU Interface Pin Mapping
11
CPU Bus Connector Pin Mapping
12
5 LCD Interface Pin Mapping
14
6 Technical Description
16
PCI Bus Support
16
Direct Host Bus Interface Support
16
S1D13706 Embedded Memory
16
Software Adjustable LCD Backlight Intensity Support Using PWM
16
Passive/Active LCD Panel Support
17
Buffered LCD Connector
17
Extended LCD Connector
17
External Oscillator Support for CLKI and CLKI2
17
7 References
18
Documents
18
Document Sources
18
8 Parts List
19
9 Schematics
22
10 Board Layout
27
11 Technical Support
28
EPSON LCD Controllers (S1D13706)
28
Epson S1D13706 User Manual (28 pages)
Brand:
Epson
| Category:
Motherboard
| Size: 0.53 MB
Table of Contents
Table of Contents
3
Introduction
5
Features
6
Installation and Configuration
7
Configuration DIP Switches
7
Configuration Jumpers
9
CPU Interface
11
CPU Interface Pin Mapping
11
CPU Bus Connector Pin Mapping
12
LCD Interface Pin Mapping
14
Technical Description
16
PCI Bus Support
16
Direct Host Bus Interface Support
16
S1D13706 Embedded Memory
16
Software Adjustable LCD Backlight Intensity Support Using PWM
16
Passive/Active LCD Panel Support
17
Buffered LCD Connector
17
Extended LCD Connector
17
External Oscillator Support for CLKI and CLKI2
17
Parts List
18
Schematics
21
Board Layout
26
Change Record
27
Sales and Technical Support
28
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