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EPSON
3 T
YPICAL
The following figures show typical system implementations of the S1D13503. All of the following
block diagrams are shown without SRAM or LCD display. Refer to the interface specific Applica-
tion Notes for complete details.
16-Bit MC68000 MPU
MC68000
A20 to A23
FC0 to FC1
A1 to A19
D0 to D15
DTACK#
1-4
S
YSTEM
A14 to A16
A10 to A19
UDS#
LDS#
AS#
R/W#
Figure 3-1 16-Bit 68000 Series
(example implementation only - actual may vary)
B
D
LOCK
IAGRAMS
Decoder
Decoder
S1D13503
MEMCS#
IOCS#
AB1 to AB19
DB0 to DB15
READY
AB0
BHE#
IOR#
IOW#
S18A-A-011-01
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