Page 1 User’s Manual 78K0/KF1 8-Bit Single-Chip Microcontrollers µ µ µ µ PD780143 PD780143(A) PD780143(A1) PD780143(A2) µ µ µ µ PD780144 PD780144(A) PD780144(A1) PD780144(A2) µ µ µ µ PD780146 PD780146(A) PD780146(A1) PD780146(A2) µ µ µ µ PD780148 PD780148(A) PD780148(A1) PD780148(A2) µ µ...
Page 2 [MEMO] User’s Manual U15947EJ2V0UD...
Page 3 NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 Major Revisions in This Edition (1/3) Page Description Throughout Addition of products µ PD78F0148(A1), 780143(A2), 780144(A2), 780146(A2), 780148(A2) Under development → Under mass production µ PD780143, 780144, 780146, 780148, 78F0148, 780143(A), 780144(A), 780146(A), 780148(A), 78F0148(A), 780143(A1), 780144(A1), 780146(A1), 780148(A1) Modification of names of the following special function registers (SFRs) •...
Page 7 Major Revisions in This Edition (2/3) Page Description p.148 Addition of Cautions 2 and 3 to Figure 6-6 Format of Oscillation Stabilization Time Counter Status Register (OSTC) pp.150 to 152 Modification of Figure 6-8 Examples of External Circuit of X1 Oscillator, Figure 6-9 Examples of External Circuit of Subsystem Clock Oscillator, and Figure 6-10 Examples of Incorrect Resonator Connection p.157...
Page 8 Major Revisions in This Edition (3/3) Page Description p.467 Modification of mask flag register 1H (MK1H) in Table 22-1 Hardware Statuses After Reset Acknowledgment p.469 Modification of Figure 23-1 Block Diagram of Clock Monitor p.471 Addition of operation mode to Table 23-2 Operation Status of Clock Monitor (When CLME = 1) pp.474, 475 Addition of (6) Clock monitor status after X1 input clock oscillation is stopped by software and (7) Clock monitor status after Ring-OSC clock oscillation is stopped by software to Figure 23-3 Timing of...
Page 9 This manual is intended to give users an understanding of the functions described in the Organization below. Organization The 78K0/KF1 manual is separated into two parts: this manual and the instructions edition (common to the 78K/0 Series). 78K0/KF1 78K/0 Series User’s Manual...
Page 10 The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. 78K0/KF1 User’s Manual This manual 78K/0 Series Instructions User’s Manual U12326E Documents Related to Development Tools (Software) (User’s Manuals) Document Name Document No.
Page 11 Document No. SEMICONDUCTOR SELECTION GUIDE − Products and Packages − X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the “Semiconductor Device Mount Manual”...
Page 12: Table Of Contents
Applications ..........................34 Ordering Information ........................ 35 Pin Configuration (Top View)....................38 K1 Family Lineup ........................40 1.5.1 78K0/Kx1 product lineup ......................40 1.5.2 V850ES/Kx1 product lineup ......................42 Block Diagram........................... 44 Outline of Functions ......................... 45 CHAPTER 2 PIN FUNCTIONS ....................... 47 Pin Function List........................
Page 13 Processor Registers......................... 74 3.2.1 Control registers..........................74 3.2.2 General-purpose registers ......................78 3.2.3 Special function registers (SFRs)....................79 Instruction Address Addressing..................... 84 3.3.1 Relative addressing........................84 3.3.2 Immediate addressing........................85 3.3.3 Table indirect addressing ......................86 3.3.4 Register addressing ........................86 Operand Address Addressing....................87 3.4.1 Implied addressing ........................87 3.4.2 Register addressing ........................88 3.4.3...
Page 14 CHAPTER 6 CLOCK GENERATOR ....................141 Functions of Clock Generator ....................141 Configuration of Clock Generator..................141 Registers Controlling Clock Generator ................143 System Clock Oscillator......................150 6.4.1 X1 oscillator..........................150 6.4.2 Subsystem clock oscillator ......................150 6.4.3 When subsystem clock is not used .................... 153 6.4.4 Ring-OSC oscillator........................
Page 15 CHAPTER 9 8-BIT TIMERS H0 AND H1 ..................230 Functions of 8-Bit Timers H0 and H1..................230 Configuration of 8-Bit Timers H0 and H1 ................230 Registers Controlling 8-Bit Timers H0 and H1 ..............234 Operation of 8-Bit Timers H0 and H1..................239 9.4.1 Operation as interval timer/square-wave output................239 9.4.2...
Page 16 13.4.2 Input voltage and conversion results ..................288 13.4.3 A/D converter operation mode....................289 13.5 How to Read A/D Converter Characteristics Table ............. 292 13.6 Cautions for A/D Converter....................294 CHAPTER 14 SERIAL INTERFACE UART0 ..................299 14.1 Functions of Serial Interface UART0 ..................299 14.2 Configuration of Serial Interface UART0 ................
Page 17 18.4.1 Multiplication operation .......................424 18.4.2 Division operation........................426 CHAPTER 19 INTERRUPT FUNCTIONS .................... 428 19.1 Interrupt Function Types ....................... 428 19.2 Interrupt Sources and Configuration..................428 19.3 Registers Controlling Interrupt Functions ................432 19.4 Interrupt Servicing Operations....................439 19.4.1 Maskable interrupt request acknowledgement ................439 19.4.2 Software interrupt request acknowledgment ................441 19.4.3 Multiple interrupt servicing ......................442 19.4.4 Interrupt request hold ........................445...
Page 18 25.4 Operation of Low-Voltage Detector ..................484 25.5 Cautions for Low-Voltage Detector..................488 CHAPTER 26 REGULATOR ......................... 492 26.1 Outline of Regulator ....................... 492 CHAPTER 27 MASK OPTIONS ......................494 µ CHAPTER 28 PD78F0148........................495 28.1 Internal Memory Size Switching Register ................496 28.2 Internal Expansion RAM Size Switching Register...............
Page 19 Language Processing Software .................... 603 Control Software........................604 Flash Memory Writing Tools ....................604 Debugging Tools (Hardware) ....................605 A.5.1 When using in-circuit emulators IE-78K0-NS and IE-78K0-NS-A ..........605 A.5.2 When using in-circuit emulator IE-78K0K1-ET ................606 Debugging Tools (Software)....................607 Embedded Software ....................... 608 APPENDIX B NOTES ON TARGET SYSTEM DESIGN..............
Page 20 LIST OF FIGURES (1/10) Figure No. Title Page Pin I/O Circuit List .............................59 µ Memory Map ( PD780143)........................62 µ Memory Map ( PD780144)........................63 µ Memory Map ( PD780146)........................64 µ Memory Map ( PD780148)........................65 µ Memory Map ( PD78F0148) ........................66 µ Correspondence Between Data Memory and Addressing ( PD780143) ..........69 µ...
Page 21 LIST OF FIGURES (2/10) Figure No. Title Page 4-23 Block Diagram of P142 ........................... 120 4-24 Block Diagram of P143 ........................... 121 4-25 Block Diagram of P144 and P145......................122 4-26 Format of Port Mode Register ........................ 123 4-27 Format of Port Register .......................... 126 4-28 Format of Pull-up Resistor Option Register ....................
Page 22 LIST OF FIGURES (3/10) Figure No. Title Page Format of 16-Bit Timer Mode Control Register 01 (TMC01) ..............176 Format of Capture/Compare Control Register 00 (CRC00) ..............177 Format of Capture/Compare Control Register 01 (CRC01) ..............178 7-10 Format of 16-Bit Timer Output Control Register 00 (TOC00)..............179 7-11 Format of 16-Bit Timer Output Control Register 01 (TOC01)..............180 7-12...
Page 23 LIST OF FIGURES (4/10) Figure No. Title Page 7-41 Operation Timing of OVF0n Flag......................210 7-42 Capture Register Data Retention Timing ....................210 Block Diagram of 8-Bit Timer/Event Counter 50 ..................212 Block Diagram of 8-Bit Timer/Event Counter 51 ..................213 Format of 8-Bit Timer Counter 5n (TM5n)....................
Page 24 LIST OF FIGURES (5/10) Figure No. Title Page 11-1 Block Diagram of Watchdog Timer ......................264 11-2 Format of Watchdog Timer Mode Register (WDTM)................265 11-3 Format of Watchdog Timer Enable Register (WDTE) ................266 11-4 Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock).......269 11-5 Operation in STOP Mode (CPU Clock: X1 Input Clock, WDT Operation Clock: Ring-OSC Clock)..269 11-6...
Page 25 LIST OF FIGURES (6/10) Figure No. Title Page 14-5 Format of Port Mode Register 1 (PM1)....................307 14-6 Format of Normal UART Transmit/Receive Data..................310 14-7 Example of Normal UART Transmit/Receive Data Waveform..............310 14-8 Transmission Completion Interrupt Request Timing................312 14-9 Reception Completion Interrupt Request Timing ..................
Page 26 LIST OF FIGURES (7/10) Figure No. Title Page 16-5 Format of Serial Clock Selection Register 10 (CSIC10)................363 16-6 Format of Serial Clock Selection Register 11 (CSIC11)................365 16-7 Format of Port Mode Register 0 (PM0) ....................366 16-8 Format of Port Mode Register 1 (PM1) ....................366 16-9 Timing in 3-Wire Serial I/O Mode ......................372 16-10...
Page 27 LIST OF FIGURES (8/10) Figure No. Title Page 18-1 Block Diagram of Multiplier/Divider......................419 18-2 Format of Remainder Data Register 0 (SDR0) ..................420 18-3 Format of Multiplication/Division Data Register A0 (MDA0H, MDA0L) ........... 421 18-4 Format of Multiplication/Division Data Register B0 (MDB0)..............422 18-5 Format of Multiplier/Divider Control Register 0 (DMUC0) ...............
Page 28 LIST OF FIGURES (9/10) Figure No. Title Page 24-1 Block Diagram of Power-on-Clear Circuit ....................477 24-2 Timing of Internal Reset Signal Generation in Power-on-Clear Circuit ...........477 24-3 Example of Software Processing After Release of Reset ...............478 25-1 Block Diagram of Low-Voltage Detector ....................480 25-2 Format of Low-Voltage Detection Register (LVIM) .................482 25-3...
Page 29 LIST OF FIGURES (10/10) Figure No. Title Page Connection Conditions of Target System (When Using NP-H80GK-TQ) ..........613 User’s Manual U15947EJ2V0UD...
Page 30 LIST OF TABLES (1/3) Table No. Title Page Flash Memory Versions Corresponding to Mask Options of Mask ROM Versions ........37 Pin I/O Buffer Power Supplies ........................47 Pin I/O Circuit Types ..........................57 Set Values of Internal Memory Size Switching Register (IMS) and Internal Expansion RAM Size Switching Register (IXS)..............61 Internal ROM Capacity..........................67 Vector Table .............................67...
Page 31 LIST OF TABLES (2/3) Table No. Title Page 10-5 Interval Timer Interval Time ........................260 11-1 Loop Detection Time of Watchdog Timer ....................262 11-2 Mask Option Setting and Watchdog Timer Operation Mode ..............263 11-3 Configuration of Watchdog Timer ......................264 12-1 Clock Output/Buzzer Output Controller Configuration ................
Page 32 LIST OF TABLES (3/3) Table No. Title Page 19-5 Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing ........................442 20-1 Assignment of Key Interrupt Detection Pins....................446 20-2 Configuration of Key Interrupt .........................446 21-1 Relationship Between Operation Clocks in Each Operation Status ............448 21-2 Operating Statuses in HALT Mode ......................452 21-3...
Page 33: Chapter 1 Outline
CHAPTER 1 OUTLINE Features µ Minimum instruction execution time can be changed from high speed (0.2 s: @ 10 MHz operation with X1 input µ clock) to ultra low-speed (122 s: @ 32.768 kHz operation with subsystem clock) General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks) ROM, RAM capacities Item Program Memory...
Page 34: Applications
CHAPTER 1 OUTLINE Supply voltage: V = 2.7 to 5.5 V (standard product, (A) grade product) = 3.3 to 5.5 V ((A1) grade product, (A2) grade product) = −40 to +85°C (standard product, (A) grade product) Operating ambient temperature: T = −40 to +105°C (flash memory version of (A1) grade product) = −40 to +110°C (mask ROM version of (A1) grade product) = −40 to +125°C (mask ROM version of (A2) grade product)
Page 35: Ordering Information
CHAPTER 1 OUTLINE Ordering Information (1) Mask ROM versions Part Number Package Quality Grade µ 80-pin plastic TQFP (fine pitch) (12 × 12) PD780143GK-×××-9EU Standard µ 80-pin plastic QFP (14 × 14) PD780143GC-×××-8BT Standard µ 80-pin plastic TQFP (fine pitch) (12 × 12) PD780144GK-×××-9EU Standard µ...
Page 36 CHAPTER 1 OUTLINE (2) Flash memory versions Part Number Package Quality Grade µ 80-pin plastic TQFP (fine pitch) (12 × 12) PD78F0148M1GK-9EU Standard µ 80-pin plastic QFP (14 × 14) PD78F0148M1GC-8BT Standard µ 80-pin plastic TQFP (fine pitch) (12 × 12) PD78F0148M2GK-9EU Standard µ...
Page 37 CHAPTER 1 OUTLINE µ Mask ROM versions ( PD780143, 780144, 780146, and 780148) include mask options. When ordering, it is possible to select “Power-on-clear (POC) circuit can be used/cannot be used”, “Ring-OSC clock can be stopped/cannot be stopped by software” and “Pull-up resistor incorporated/not incorporated in 1-bit units (P60 to P63)”.
Page 38: Pin Configuration (Top View)
CHAPTER 1 OUTLINE Pin Configuration (Top View) • 80-pin plastic TQFP (fine pitch) (12 × 12) • 80-pin plastic QFP (14 × 14) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P44/AD4 P45/AD5 P120/INTP0...
Page 39 CHAPTER 1 OUTLINE Pin Identification A8 to A15: Address bus REGC: Regulator capacitance AD0 to AD7: Address/data bus RESET: Reset ANI0 to ANI7: Analog input RxD0, RxD6: Receive data Read strobe ASTB: Address strobe Note Analog reference voltage SCK10, SCK11 Analog ground SCKA0: Serial clock input/output...
Page 40: K1 Family Lineup
PD780122 µ Mask ROM: 8 KB, RAM: 512 bytes PD780121 78K0/KE1: 64-pin (10 × 10 mm 0.5 mm pitch, 12 × 12 mm 0.65 mm pitch, 14 × 14 mm 0.8 mm pitch) µ µ PD78F0134 Flash memory: 32 KB, RAM: 1 KB...
Page 41 CHAPTER 1 OUTLINE The list of functions in the 78K0/Kx1 is shown below. Part Number 78K0/KB1 78K0/KC1 78K0/KD1 78K0/KE1 78K0/KF1 Item Package 30 pins 44 pins 52 pins 64 pins 80 pins − − − − − − Internal Mask ROM...
Page 42: V850Es/Kx1 Product Lineup
CHAPTER 1 OUTLINE 1.5.2 V850ES/Kx1 product lineup 80-pin plastic QFP (14 × 14) V850ES/KF1 80-pin plastic TQFP (fine pitch) (12 × 12) µ PD703208 Mask ROM: 64 KB, RAM: 4 KB µ PD703208Y C products µ PD703209 Mask ROM: 96 KB, RAM: 4 KB µ...
Page 43 CHAPTER 1 OUTLINE The list of functions in the V850ES/Kx1 is shown below. Function Timer Serial Interface Other Part No. 8-Bit 16-Bit TMH Watch WDT CSIA UART µ PD703208 2 ch 2 ch 2 ch 1 ch 2 ch 2 ch 1 ch 2 ch –...
Page 44: Block Diagram
CHAPTER 1 OUTLINE Block Diagram TO00/TI010/P01 16-bit timer/ Port 0 P00 to P06 event counter 00 TI000/P00 Port 1 P10 to P17 Note Note TO01 /TI011 /P06 Note 16-bit timer/ Note event counter 01 TI001 /P05 Port 2 P20 to P27 TOH0/P15 Port 3 8-bit timer H0...
Page 45: Outline Of Functions
CHAPTER 1 OUTLINE Outline of Functions (1/2) µ µ µ µ µ PD780143 PD780144 PD780146 PD780148 PD78F0148 Item Note Internal memory 24 KB 32 KB 48 KB 60 KB 60 KB (flash memory) High-speed 1 KB − Note Expansion RAM 1 KB 1 KB Buffer RAM...
Page 46 CHAPTER 1 OUTLINE (2/2) µ µ µ µ µ PD780143 PD780144 PD780146 PD780148 PD78F0148 Item 10-bit resolution × 8 channels A/D converter Serial interface • UART mode supporting LIN-bus: 1 channel • 3-wire serial I/O mode: 1 channel µ (None in the PD780143, 780144) •...
Page 47: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS Pin Function List There are three types of pin I/O buffer power supplies: AV , EV , and V . The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins P20 to P27...
Page 48 CHAPTER 2 PIN FUNCTIONS (1) Port pins (2/2) Pin Name Function After Reset Alternate Function P50 to P57 Port 5. Input A8 to A15 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.
Page 49 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/2) Pin Name Function After Reset Alternate Function INTP0 Input External interrupt request input for which the valid edge (rising Input P120 edge, falling edge, or both rising and falling edges) can be INTP1 to INTP3 P30 to P32 specified...
Page 50 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (2/2) Pin Name Function After Reset Alternate Function Output Clock output (for trimming of X1 input clock, subsystem clock) Input P140/INTP6 Output Buzzer output Input P141/INTP7/BUSY0 AD0 to AD7 Lower address/data bus for external memory expansion Input P40 to P47 A8 to A15...
Page 51: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS Description of Pin Functions 2.2.1 P00 to P06 (port 0) P00 to P06 function as a 7-bit I/O port. These pins also function as timer I/O, serial interface data I/O, clock I/O, and chip select input. The following operation modes can be specified in 1-bit units.
Page 52: P10 To P17 (Port 1)
CHAPTER 2 PIN FUNCTIONS 2.2.2 P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P10 to P17 function as an 8-bit I/O port.
Page 53: P30 To P33 (Port 3)
CHAPTER 2 PIN FUNCTIONS 2.2.4 P30 to P33 (port 3) P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P30 to P33 function as a 4-bit I/O port.
Page 54: P60 To P67 (Port 6)
CHAPTER 2 PIN FUNCTIONS 2.2.7 P60 to P67 (port 6) P60 to P67 function as an 8-bit I/O port. These pins also function as control pins in external memory expansion mode. The following operation modes can be specified. (1) Port mode P60 to P67 function as an 8-bit I/O port.
Page 55: P140 To P145 (Port 14)
CHAPTER 2 PIN FUNCTIONS 2.2.11 P140 to P145 (port 14) P140 to P145 function as a 6-bit I/O port. These pins also function as external interrupt request input, clock output, buzzer output, serial interface data I/O, clock I/O, busy input, and strobe output pins. The following operation modes can be specified in 1-bit units.
Page 56: Reset
V in the normal operation mode. 2.2.21 IC (mask ROM versions only) The IC (Internally Connected) pin is provided to set the test mode to check the 78K0/KF1 at shipment. Connect it directly to EV or V pin with the shortest possible wire in the normal operation mode.
Page 57: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. See Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-2.
Page 58 CHAPTER 2 PIN FUNCTIONS Table 2-2. Pin I/O Circuit Types (2/2) Pin Name I/O Circuit Type Recommended Connection of Unused Pins P130 Output Leave open. P140/PCL/INTP6 Input: Independently connect to EV or EV via a resistor. Output: Leave open. P141/BUZ/BUSY0/INTP7 P142/SCKA0 P143/SIA0 P144/SOA0...
Page 59 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 8-A Pullup P-ch enable Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output N-ch disable Type 3-C Type 9-C Comparator P-ch N-ch P-ch – Data (threshold voltage) N-ch Input enable...
Page 60 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 13-S Type 13-W IN/OUT   Mask   Data  option  N-ch IN/OUT Output disable Data N-ch Output disable Input enable Middle-voltage input buffer Type 13-V Type 16 Feedback ...
Page 61: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE Memory Space 78K0/KF1 products can each access a 64 KB memory space. Figures 3-1 to 3-5 show the memory maps. Caution Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of all 78K0/KF1 products are fixed (IMS = CFH, IXS = 0CH).
Page 62 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-1. Memory Map ( PD780143) FFFFH Special function registers (SFR) 256 × 8 bits FF00H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits 5FFFH FB00H FAFFH Reserved Program area FA20H...
Page 63 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-2. Memory Map ( PD780144) FFFFH Special function registers (SFR) 256 × 8 bits FF00H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits 7FFFH FB00H FAFFH Program area Reserved FA20H...
Page 64 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-3. Memory Map ( PD780146) FFFFH Special function registers (SFR) 256 × 8 bits FF00H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits FB00H FAFFH Reserved FA20H BFFFH FA1FH...
Page 65 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-4. Memory Map ( PD780148) FFFFH Special function registers (SFR) 256 × 8 bits FF00H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits FB00H FAFFH Reserved FA20H EFFFH FA1FH...
Page 66 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-5. Memory Map ( PD78F0148) FFFFH Special function registers (SFR) 256 × 8 bits FF00H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits FB00H FAFFH Reserved FA20H EFFFH FA1FH...
Page 67: Internal Program Memory Space
The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/KF1 products incorporate internal ROM (mask ROM or flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number...
Page 68: Internal Data Memory Space
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). 3.1.2 Internal data memory space 78K0/KF1 products incorporate the following RAMs. (1) Internal high-speed RAM The internal high-speed RAM is allocated to the area FB00H to FEFFH in a 1024 × 8 bits configuration.
Page 69: Data Memory Addressing
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/KF1, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are available for use.
Page 70 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-7. Correspondence Between Data Memory and Addressing ( PD780144) FFFFH Special function registers (SFR) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH...
Page 71 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-8. Correspondence Between Data Memory and Addressing ( PD780146) FFFFH Special function registers (SFR) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH...
Page 72 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-9. Correspondence Between Data Memory and Addressing ( PD780148) FFFFH Special function registers (SFR) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH...
Page 73 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-10. Correspondence Between Data Memory and Addressing ( PD78F0148) FFFFH Special function registers (SFR) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH...
Page 74: Processor Registers
CHAPTER 3 CPU ARCHITECTURE Processor Registers The 78K0/KF1 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP).
Page 75 CHAPTER 3 CPU ARCHITECTURE (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored.
Page 76 CHAPTER 3 CPU ARCHITECTURE Figure 3-14. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) FEE0H FEE0H FEDFH...
Page 77 CHAPTER 3 CPU ARCHITECTURE Figure 3-15. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) RET instruction (when SP = FEDEH) FEE0H FEE0H FEDFH PC15 to PC8...
Page 78: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).
Page 79: Special Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit manipulation instructions.
Page 80 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (1/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF00H Port register 0 √ √ − FF01H Port register 1 √...
Page 81 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (2/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF2CH Port mode register 12 PM12 √ √ −...
Page 82 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (3/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF6BH 8-bit timer mode control register 50 TMC50 √...
Page 83 Notes 1. PD780146, 780148, and 78F0148 only. The default value of IMS and IXS are fixed (IMS = CFH, IXS = 0CH) in all 78K0/KF1 products regardless of the internal memory capacity. Therefore, set the following value to each product.
Page 84: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 85: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.
Page 86: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.
Page 87: Operand Address Addressing
Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed. Of the 78K0/KF1 instruction words, the following instructions employ implied addressing. Instruction Register to Be Specified by Implied Addressing MULU...
Page 88: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code. Register addressing is carried out when an instruction with the following operand format is executed.
Page 89: Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code OP code [Illustration]...
Page 90: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 91: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 92: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all the memory spaces.
Page 93: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 94: Based Indexed Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 95: Stack Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed.
Page 96: Chapter 4 Port Functions
P20 to P27 Port pins other than P20 to P27 78K0/KF1 products are provided with the ports shown in Figure 4-1, which enable variety of control operations. The functions of each port are shown in Table 4-2. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS.
Page 97 CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions (1/2) Pin Name Function After Reset Alternate Function Port 0. Input TI000 7-bit I/O port. TI010/TO00 Input/output can be specified in 1-bit units. Note SO11 Use of an on-chip pull-up resistor can be specified by a Note SI11 software setting.
Page 98: Port Configuration
CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions (2/2) Pin Name Function After Reset Alternate Function − P60 to P63 Port 6. N-ch open-drain I/O port. Input 8-bit I/O port. Use of an on-chip pull-up Input/output can be specified resistor can be specified by a in 1-bit units.
Page 99: Port 0
CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is a 7-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).
Page 100 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P01 and P06 PU01, PU06 P-ch Alternate function PORT Output latch P01/TI010/TO00, (P01, P06) Note Note P06/TI011 /TO01 PM01, PM06 Alternate function µ Note Available only in the PD780146, 780148, and 78F0148. PU0: Pull-up resistor option register 0 PM0: Port mode register 0...
Page 101 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P02 PU02 P-ch PORT Output latch Note (P02) P02/SO11 PM02 Alternate function µ Note Available only in the PD780146, 780148, and 78F0148. PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal User’s Manual U15947EJ2V0UD...
Page 102 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P04 PU04 P-ch Alternate function PORT Output latch Note P04/SCK11 (P04) PM04 Alternate function µ Note Available only in the PD780146, 780148, and 78F0148. PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal User’s Manual U15947EJ2V0UD...
Page 103: Port 1
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).
Page 104 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P11 and P14 PU11, PU14 P-ch Alternate function PORT Output latch P11/SI10/RxD0, (P11, P14) P14/RxD6 PM11, PM14 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U15947EJ2V0UD...
Page 105 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P12 and P15 PU12, PU15 P-ch PORT Output latch P12/SO10 (P12, P15) P15/TOH0 PM12, PM15 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U15947EJ2V0UD...
Page 106 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P13 PU13 P-ch PORT Output latch (P13) P13/TxD6 PM13 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U15947EJ2V0UD...
Page 107 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P16 and P17 PU16, PU17 P-ch Alternate function PORT Output latch P16/TOH1/INTP5, (P16, P17) P17/TI50/TO50 PM16, PM17 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U15947EJ2V0UD...
Page 108: Port 2
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an 8-bit input-only port. This port can also be used for A/D converter analog input. Figure 4-11 shows a block diagram of port 2. Figure 4-11. Block Diagram of P20 to P27 A/D converter P20/ANI0 to P27/ANI7 Read signal...
Page 109: Port 3
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).
Page 110 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P33 PU33 P-ch Alternate function PORT Output latch P33/INTP4/TI51/TO51 (P33) PM33 Alternate function PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal User’s Manual U15947EJ2V0UD...
Page 111: Port 4
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 Port 4 is an 8-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor option register 4 (PU4).
Page 112: Port 5
CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 5 Port 5 is an 8-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified in 1-bit units using pull-up resistor option register 5 (PU5).
Page 113: Port 6
CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 6 Port 6 is an 8-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). This port has the following functions for pull-up resistors. These functions differ depending on the higher 4 bits/lower 4 bits of the port, and whether the product is a mask ROM version or a flash memory version.
Page 114 CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P64, P65, and P67 PU64, PU65, PU67 P-ch Selector PORT Output latch P64/RD, (P64, P65, P67) Selector P65/WR, P67/ASTB Alternate function PM64, PM65, PM67 Memory expansion mode register (MEM) PU6: Pull-up resistor option register 6 PM6: Port mode register 6 Read signal WR××: Write signal...
Page 115 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of P66 PU66 P-ch Alternate function Selector PORT Output latch Selector P66/WAIT (P66) Memory expansion mode register (MEM) PM66 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 Read signal WR××: Write signal User’s Manual U15947EJ2V0UD...
Page 116: Port 7
CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 7 Port 7 is an 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7).
Page 117: Port 12
CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 12 Port 12 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
Page 118: Port 13
CHAPTER 4 PORT FUNCTIONS 4.2.10 Port 13 Port 13 is a 1-bit output-only port. Figure 4-21 shows a block diagram of port 13. Figure 4-21. Block Diagram of P130 PORT Output latch P130 (P130) Read signal WR××: Write signal Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level immediately after reset is released, the output signal of P130 can be dummy-output as the reset signal to the CPU.
Page 119: Port 14
CHAPTER 4 PORT FUNCTIONS 4.2.11 Port 14 Port 14 is a 6-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 to P145 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14).
Page 120: Block Diagram Of P142
CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of P142 PU14 PU142 P-ch Alternate function PORT Output latch P142/SCKA0 (P142) PM14 PM142 Alternate function PU14: Pull-up resistor option register 14 PM14: Port mode register 14 Read signal WR××: Write signal User’s Manual U15947EJ2V0UD...
Page 121: Block Diagram Of P143
CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of P143 PU14 PU143 P-ch Alternate function PORT Output latch P143/SIA0 (P143) PM14 PM143 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 Read signal WR××: Write signal User’s Manual U15947EJ2V0UD...
Page 122: Block Diagram Of P144 And P145
CHAPTER 4 PORT FUNCTIONS Figure 4-25. Block Diagram of P144 and P145 PU14 PU144, PU145 P-ch PORT Output latch (P144, P145) P144/SOA0, P145/STB0 PM14 PM144, PM145 Alternate function PU14: Pull-up resistor option register 14 PM14: Port mode register 14 Read signal WR××: Write signal User’s Manual U15947EJ2V0UD...
Page 123: Registers Controlling Port Function
CHAPTER 4 PORT FUNCTIONS Registers Controlling Port Function Port functions are controlled by the following three types of registers. • Port mode registers (PM0, PM1, PM3 to PM7, PM12, PM14) • Port registers (P0 to P7, P12 to P14) • Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU12, PU14) (1) Port mode registers (PM0, PM1, PM3 to PM7, PM12, and PM14) These registers specify input or output mode for the port in 1-bit units.
Page 124 CHAPTER 4 PORT FUNCTIONS Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (1/2) PM×× P×× Pin Name Alternate Function Function Name × TI000 Input × TI010 Input TO00 Output Note 1 SO11 Output × Note 1 SI11 Input...
Page 125 CHAPTER 4 PORT FUNCTIONS Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2) PM×× P×× Pin Name Alternate Function Function Name × P70 to P77 KR0 to KR7 Input × P120 INTP0 Input P140 Output ×...
Page 126: Format Of Port Register
CHAPTER 4 PORT FUNCTIONS (2) Port registers (P0 to P7, P12 to P14) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output latch is read.
Page 127: Format Of Pull-Up Resistor Option Register
CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU12, and PU14) These registers specify whether the on-chip pull-up resistors of P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, or P140 to P145 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified.
Page 128: Port Function Operations
CHAPTER 4 PORT FUNCTIONS Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit.
Page 129: Chapter 5 External Bus Interface
CHAPTER 5 EXTERNAL BUS INTERFACE External Bus Interface The external bus interface connects external devices to areas other than the internal ROM, RAM, and SFR areas. Connection of external devices uses ports 4 to 6. Ports 4 to 6 control address/data, read/write strobe, wait, address strobe, etc.
Page 130: Memory Map When Using External Bus Interface
CHAPTER 5 EXTERNAL BUS INTERFACE The memory maps when the external bus interface is used are as follows. Figure 5-1. Memory Map When Using External Bus Interface (1/2) µ µ µ µ (a) Memory map of PD780143 and of PD78F0148 (b) Memory map of PD780144 and of PD78F0148...
Page 131 CHAPTER 5 EXTERNAL BUS INTERFACE Figure 5-1. Memory Map When Using External Bus Interface (2/2) µ µ µ µ (c) Memory map of PD780146 and of PD78F0148 (d) Memory map of PD780148 and of PD78F0148 when internal ROM (flash memory) size is 48 KB when internal ROM (flash memory) size is 60 KB FFFFH FFFFH...
Page 132: Registers Controlling External Bus Interface
CHAPTER 5 EXTERNAL BUS INTERFACE Registers Controlling External Bus Interface The external bus interface is controlled by the following two registers. • Memory expansion mode register (MEM) • Memory expansion wait setting register (MM) (1) Memory expansion mode register (MEM) MEM sets the external expansion area.
Page 133: Pins Specified For Address (With Μ Pd780143)
CHAPTER 5 EXTERNAL BUS INTERFACE Note When the CPU accesses the external memory expansion area, the lower bits of the address to be accessed are output to the specified pins (except in the full-address mode). µ Figure 5-3. Pins Specified for Address (with PD780143) External Address...
Page 134: Format Of Memory Expansion Wait Setting Register (Mm)
CHAPTER 5 EXTERNAL BUS INTERFACE (2) Memory expansion wait setting register (MM) MM sets the number of waits. MM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets MM to 10H. Figure 5-4. Format of Memory Expansion Wait Setting Register (MM) Address: FFF8H After reset: 10H Symbol...
Page 135: External Bus Interface Function Timing
CHAPTER 5 EXTERNAL BUS INTERFACE External Bus Interface Function Timing Timing control signal output pins in the external memory expansion mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin. The read strobe signal is output in data read and instruction fetch from external memory.
Page 136: Instruction Fetch From External Memory
CHAPTER 5 EXTERNAL BUS INTERFACE Figure 5-5. Instruction Fetch from External Memory (a) No wait (PW1, PW0 = 0, 0) setting ASTB Lower address Instruction code AD0 to AD7 Higher address A8 to A15 (b) Wait (PW1, PW0 = 0, 1) setting ASTB Lower address Instruction code...
Page 137: External Memory Read Timing
CHAPTER 5 EXTERNAL BUS INTERFACE Figure 5-6. External Memory Read Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB Lower address Read data AD0 to AD7 Higher address A8 to A15 (b) Wait (PW1, PW0 = 0, 1) setting ASTB AD0 to AD7 Lower address...
Page 138: External Memory Write Timing
CHAPTER 5 EXTERNAL BUS INTERFACE Figure 5-7. External Memory Write Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB Hi-Z Lower address Write data AD0 to AD7 Higher address A8 to A15 (b) Wait (PW1, PW0 = 0, 1) setting ASTB Hi-Z Lower...
Page 139: External Memory Read Modify Write Timing
CHAPTER 5 EXTERNAL BUS INTERFACE Figure 5-8. External Memory Read Modify Write Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB Hi-Z Lower AD0 to AD7 Read data Write data address A8 to A15 Higher address (b) Wait (PW1, PW0 = 0, 1) setting ASTB Hi-Z Lower...
Page 140: Example Of Connection With Memory
CHAPTER 5 EXTERNAL BUS INTERFACE Example of Connection with Memory µ An example of connecting the PD780144 with external memory (in this example, SRAM) is shown in Figure 5-9. In addition, the external bus interface function is used in the full-address mode, and the addresses from 0000H to 7FFFH (32 KB) are allocated to internal ROM, and the addresses after 8000H to SRAM.
Page 141: Chapter 6 Clock Generator
CHAPTER 6 CLOCK GENERATOR Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three system clock oscillators are available. • X1 oscillator The X1 oscillator oscillates a clock of f = 2.0 to 10.0 MHz.
Page 142: Block Diagram Of Clock Generator
CHAPTER 6 CLOCK GENERATOR Figure 6-1. Block Diagram of Clock Generator Internal bus Oscillation Main OSC Processor clock Main clock stabilization time control mode register control register select register register (PCC) (MCM) (OSTS) (MOC) MCM0 OSTS2 OSTS1 OSTS0 CSS PCC2 PCC1 PCC0 MSTOP X1 oscillation...
Page 143: Registers Controlling Clock Generator
CHAPTER 6 CLOCK GENERATOR Registers Controlling Clock Generator The following six registers are used to control the clock generator. • Processor clock control register (PCC) • Ring-OSC mode register (RCM) • Main clock mode register (MCM) • Main OSC control register (MOC) •...
Page 144: Format Of Processor Clock Control Register (Pcc)
CHAPTER 6 CLOCK GENERATOR Figure 6-2. Format of Processor Clock Control Register (PCC) Note 1 Address: FFFBH After reset: 00H Symbol <7> <6> <5> <4> PCC2 PCC1 PCC0 Note 2 Control of X1 oscillator operation Oscillation possible Oscillation stopped Subsystem clock feedback resistor selection On-chip feedback resistor used Note 3 On-chip feedback resistor not used...
Page 145: Format Of Ring-Osc Mode Register (Rcm)
5. f : Subsystem clock oscillation frequency The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KF1. Therefore, the relationship between the CPU clock (f ) and minimum instruction execution time is as shown in the Table 6-2.
Page 146: Format Of Main Clock Mode Register (Mcm)
CHAPTER 6 CLOCK GENERATOR (3) Main clock mode register (MCM) This register sets the CPU clock (X1 input clock/Ring-OSC clock). MCM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 6-4. Format of Main Clock Mode Register (MCM) Note Address: FFA1H After reset: 00H...
Page 147: Format Of Main Osc Control Register (Moc)
CHAPTER 6 CLOCK GENERATOR (4) Main OSC control register (MOC) This register selects the operation mode of the X1 input clock. This register is used to stop the X1 oscillator operation when the CPU is operating with the Ring-OSC clock. Therefore, this register is valid only when the CPU is operating with the Ring-OSC clock.
Page 148: Format Of Oscillation Stabilization Time Counter Status Register (Ostc)
CHAPTER 6 CLOCK GENERATOR (5) Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 input clock oscillation stabilization time counter. If the Ring-OSC clock is used as the CPU clock, the X1 input clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
Page 149: Format Of Oscillation Stabilization Time Select Register (Osts)
CHAPTER 6 CLOCK GENERATOR (6) Oscillation stabilization time select register (OSTS) This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released with the X1 input clock selected as CPU clock.
Page 150: System Clock Oscillator
CHAPTER 6 CLOCK GENERATOR System Clock Oscillator 6.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (Standard: 8.38 MHz, 10 MHz when REGC pin is connected directly to V ) connected to the X1 and X2 pins. An external clock can be input to the X1 oscillator when the REGC pin is connected directly to V .
Page 151: Examples Of Incorrect Resonator Connection
CHAPTER 6 CLOCK GENERATOR Cautions 1. When using the X1 oscillator and subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the Figure 6-10 to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. •...
Page 152 CHAPTER 6 CLOCK GENERATOR Figure 6-10. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively.
Page 153: When Subsystem Clock Is Not Used
6.4.4 Ring-OSC oscillator Ring-OSC oscillator is incorporated in the 78K0/KF1. “Can be stopped by software” or “Cannot be stopped” can be selected by a mask option. The Ring-OSC clock always oscillates after RESET release (240 kHz (TYP.)).
Page 154: Clock Generator Operation
• Clock to peripheral hardware The CPU starts operation when the on-chip Ring-OSC oscillator starts outputting after reset release in the 78K0/KF1, thus enabling the following. (1) Enhancement of security function When the X1 input clock is set as the CPU clock by the default setting, the device cannot operate if the X1 input clock is damaged or badly connected and therefore does not operate after reset is released.
Page 155: Timing Diagram Of Cpu Default Start Using Ring-Osc
CHAPTER 6 CLOCK GENERATOR Figure 6-12. Timing Diagram of CPU Default Start Using Ring-OSC X1 input clock Ring-OSC clock Subsystem clock RESET Switched by software X1 input clock Ring-OSC clock CPU clock Operation stopped: 17/f Note X1 oscillation stabilization time: 2 to 2 Note Check using the oscillation stabilization time counter status register (OSTC).
Page 156: Status Transition Diagram
CHAPTER 6 CLOCK GENERATOR A status transition diagram of this product is shown in Figure 6-13, and the relationship between the operation clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown in Tables 6-3 and 6-4, respectively.
Page 157 CHAPTER 6 CLOCK GENERATOR Figure 6-13. Status Transition Diagram (2/4) (2) When “Ring-OSC can be stopped by software” is selected by mask option (when subsystem clock is used) Status 6 CPU clock: f : Oscillation stopped : Oscillating/ oscillation stopped Interrupt MCC = 0 MCC = 1...
Page 158 CHAPTER 6 CLOCK GENERATOR Figure 6-13. Status Transition Diagram (3/4) (3) When “Ring-OSC cannot be stopped” is selected by mask option (when subsystem clock is not used) HALT HALT HALT instruction Interrupt Interrupt instruction Interrupt HALT instruction Status 3 Status 1 Status 2 Note 2 MCM0 = 0...
Page 159 CHAPTER 6 CLOCK GENERATOR Figure 6-13. Status Transition Diagram (4/4) (4) When “Ring-OSC cannot be stopped” is selected by mask option (when subsystem clock is used) Status 5 CPU clock: f : Oscillation stopped : Oscillating Interrupt MCC = 0 MCC = 1 HALT instruction Status 4...
Page 160 CHAPTER 6 CLOCK GENERATOR Table 6-3. Relationship Between Operation Clocks in Each Operation Status Status X1 Oscillator Ring-OSC Oscillator Subsystem CPU Clock Prescaler Clock Clock After Supplied to Peripherals MSTOP = 0 MSTOP = 1 Note 1 Note 2 Operation Oscillator Release MCC = 0...
Page 161: Time Required To Switch Between Ring-Osc Clock And X1 Input Clock
CHAPTER 6 CLOCK GENERATOR Time Required to Switch Between Ring-OSC Clock and X1 Input Clock Bit 0 (MCM0) of the main clock mode register (MCM) is used to switch between the Ring-OSC clock and X1 input clock. In the actual switching operation, switching does not occur immediately after MCM0 rewrite; several instructions are executed using the pre-switch clock after switching MCM0 (see Table 6-5).
Page 162: Time Required For Cpu Clock Switchover
CHAPTER 6 CLOCK GENERATOR Time Required for CPU Clock Switchover The CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC). The actual switchover operation is not performed immediately after rewriting to the PCC; operation continues on the pre-switchover clock for several instructions (see Table 6-6).
Page 163: Clock Switching Flowchart And Register Setting
CHAPTER 6 CLOCK GENERATOR Clock Switching Flowchart and Register Setting 6.8.1 Switching from Ring-OSC clock to X1 input clock Figure 6-14. Switching from Ring-OSC Clock to X1 Input Clock (Flowchart) After reset release PCC = 00H RCM = 00H ; Ring-OSC oscillation MCM = 00H Register initial ;...
Page 164: Switching From X1 Input Clock To Ring-Osc Clock
CHAPTER 6 CLOCK GENERATOR 6.8.2 Switching from X1 input clock to Ring-OSC clock Figure 6-15. Switching from X1 Input Clock to Ring-OSC Clock (Flowchart) Register setting PCC.7 (MCC) = 0 ; X1 oscillation in X1 input PCC.4 (CSS) = 0 ;...
Page 165: Switching From X1 Input Clock To Subsystem Clock
CHAPTER 6 CLOCK GENERATOR 6.8.3 Switching from X1 input clock to subsystem clock Figure 6-16. Switching from X1 Input Clock to Subsystem Clock (Flowchart) Register setting PCC.7 (MCC) = 0 ; X1 oscillation in X1 input PCC.4 (CSS) = 0 ;...
Page 166: Switching From Subsystem Clock To X1 Input Clock
CHAPTER 6 CLOCK GENERATOR 6.8.4 Switching from subsystem clock to X1 input clock Figure 6-17. Switching from Subsystem Clock to X1 Input Clock (Flowchart) PCC.4 (CSS) = 1 ; Subsystem clock operation MCM = 03H No: X1 oscillating MCC = 1? ;...
Page 167: Register Settings
CHAPTER 6 CLOCK GENERATOR 6.8.5 Register settings The table below shows the statuses of the setting flags and status flags when each mode is set. Table 6-7. Clock and Register Setting Mode Setting Flag Status Flag PCC Register Register Register Register Register Register...
Page 168: Chapter 7 16-Bit Timer/Event Counters 00 And 01
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 µ µ PD780143 and 780144 incorporate 16-bit timer/event counter 00, and the PD780146, 780148, and 78F0148 incorporate 16-bit timer/event counters 00 and 01. Functions of 16-Bit Timer/Event Counters 00 and 01 Note 16-bit timer/event counters 00 and 01 have the following functions.
Page 169: Configuration Of 16-Bit Timer/Event Counters 00 And 01
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Configuration of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01 consist of the following hardware. Table 7-1. Configuration of 16-Bit Timer/Event Counters 00 and 01 Item Configuration Timer counter 16 bits (TM0n) Register 16-bit timer capture/compare register: 16 bits (CR00n, CR01n)
Page 170: Pd780146, 780148, And 78F0148 Only)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 µ Figure 7-2. Block Diagram of 16-Bit Timer/Event Counter 01 ( PD780146, 780148, and 78F0148 Only) Internal bus Capture/compare control register 01 (CRC01) CRC012CRC011 CRC010 INTTM001 Noise 16-bit timer capture/compare TI011/TO01/P06 elimi- register 001 (CR001) nator Match...
Page 171: Format Of 16-Bit Timer Counter 0N (Tm0N)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (1) 16-bit timer counter 0n (TM0n) TM0n is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. Figure 7-3. Format of 16-Bit Timer Counter 0n (TM0n) Address: FF10H, FF11H (TM00), FFB0H, FFB1H (TM01) After reset: 0000H Symbol...
Page 172 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Table 7-2. CR00n Capture Trigger and Valid Edges of TI00n and TI01n Pins (1) TI00n pin valid edge selected as capture trigger (CRC0n1 = 1, CRC0n0 = 1) CR00n Capture Trigger TI00n Pin Valid Edge ES0n1 ES0n0 Falling edge...
Page 173: Format Of 16-Bit Timer Capture/Compare Register 01N (Cr01N)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) 16-bit timer capture/compare register 01n (CR01n) CR01n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC0n2) of capture/compare control register 0n (CRC0n).
Page 174: Registers Controlling 16-Bit Timer/Event Counters 00 And 01
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 The following six registers are used to control 16-bit timer/event counters 00 and 01. • 16-bit timer mode control register 0n (TMC0n) • Capture/compare control register 0n (CRC0n) •...
Page 175: Format Of 16-Bit Timer Mode Control Register 00 (Tmc00)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-6. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FFBAH After reset: 00H Symbol <0> TMC00 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 TMC001 Operating mode and clear TO00 inversion timing selection Interrupt request generation mode selection Operation stop...
Page 176: Format Of 16-Bit Timer Mode Control Register 01 (Tmc01)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-7. Format of 16-Bit Timer Mode Control Register 01 (TMC01) Address: FFB6H After reset: 00H Symbol <0> TMC01 TMC013 TMC012 TMC011 OVF01 TMC013 TMC012 TMC011 Operating mode and clear TO01 inversion timing selection Interrupt request generation mode selection Operation stop...
Page 177: Format Of Capture/Compare Control Register 00 (Crc00)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Capture/compare control register 0n (CRC0n) This register controls the operation of the 16-bit timer capture/compare registers (CR00n, CR01n). CRC0n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CRC0n to 00H. µ...
Page 178: Format Of Capture/Compare Control Register 01 (Crc01)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-9. Format of Capture/Compare Control Register 01 (CRC01) Address: FFB8H After reset: 00H Symbol CRC01 CRC012 CRC011 CRC010 CRC012 CR011 operating mode selection Operates as compare register Operates as capture register CRC011 CR001 capture trigger selection Captures on valid edge of TI011...
Page 179: Format Of 16-Bit Timer Output Control Register 00 (Toc00)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-10. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H Symbol <6> <5> <3> <2> <0> TOC00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger control via software No one-shot pulse trigger One-shot pulse trigger OSPE00...
Page 180: Format Of 16-Bit Timer Output Control Register 01 (Toc01)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-11. Format of 16-Bit Timer Output Control Register 01 (TOC01) Address: FFB9H After reset: 00H Symbol <6> <5> <3> <2> <0> TOC01 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01 OSPT01 One-shot pulse output trigger control via software No one-shot pulse trigger One-shot pulse trigger OSPE01...
Page 181 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Prescaler mode register 0n (PRM0n) This register is used to set the 16-bit timer counter 0n (TM0n) count clock and TI00n and TI01n input valid edges. PRM0n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears PRM0n to 00H.
Page 182: Format Of Prescaler Mode Register 00 (Prm00)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-12. Format of Prescaler Mode Register 00 (PRM00) Address: FFBBH After reset: 00H Symbol PRM00 ES101 ES100 ES001 ES000 PRM001 PRM000 ES101 ES100 TI010 valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES001...
Page 183: Format Of Prescaler Mode Register 01 (Prm01)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-13. Format of Prescaler Mode Register 01 (PRM01) Address: FFB7H After reset: 00H Symbol PRM01 ES111 ES110 ES011 ES010 PRM011 PRM010 ES111 ES110 TI011 valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES011...
Page 184: Format Of Port Mode Register 0 (Pm0)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. Note Note When using the P01/TO00/TI010 and P06/TO01 /TI011 pins for timer output, clear PM01 and PM06 and the output latches of P01 and P06 to 0.
Page 185: Operation Of 16-Bit Timer/Event Counters 00 And 01
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Operation of 16-Bit Timer/Event Counters 00 and 01 7.4.1 Interval timer operation Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 7-15 allows operation as an interval timer. Setting The basic operation setting procedure is as follows.
Page 186: Control Register Settings For Interval Timer Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-15. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0...
Page 187: Interval Timer Configuration Diagram
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-16. Interval Timer Configuration Diagram 16-bit timer capture/compare register 00n (CR00n) INTTM00n Note 1 Note 1 Note 2 16-bit timer counter 0n OVF0n Note 1 (TM0n) Noise TI000/P00 eliminator Note 1 (TI001/P05) Clear circuit...
Page 188: Ppg Output Operations
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.2 PPG output operations Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 7-18 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic operation setting procedure is as follows.
Page 189: Control Register Settings For Ppg Output Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-18. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0...
Page 190: Configuration Diagram Of Ppg Output
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-19. Configuration Diagram of PPG Output 16-bit timer capture/compare register 00n (CR00n) Note Note Clear 16-bit timer counter 0n Note circuit (TM0n) TI000/P00 Noise Note eliminator (TI001/P05) TO00/TI010/P01 ( TO01/TI011/P06 ) 16-bit timer capture/compare register 01n (CR01n) Note Frequencies and pin names without parentheses are for 16-bit timer/event counter 00, and those in...
Page 191: Pulse Width Measurement Operations
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00n pin and TI01n pin using 16-bit timer counter 0n (TM0n). There are two measurement methods: measuring with TM0n used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00n pin.
Page 192: And One Capture Register (When Ti00N And Cr01N Are Used)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 0n (TM0n) is operated in free-running mode, and the edge specified by prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an external interrupt request signal (INTTM01n) is set.
Page 193: Configuration Diagram For Pulse Width Measurement With Free-Running Counter
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-23. Configuration Diagram for Pulse Width Measurement with Free-Running Counter Note 16-bit timer counter 0n Note OVF0n (TM0n) Note 16-bit timer capture/compare TI00n register 01n (CR01n) INTTM01n Internal bus Note Frequencies without parentheses are for 16-bit timer/event counter 00, and those in parentheses are for 16- bit timer/event counter 01.
Page 194: Control Register Settings For Measurement Of Two Pulse Widths With Free-Running Counter
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 0n (TM0n) is operated in free-running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the TI00n pin and the TI01n pin. When the edge specified by bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an interrupt request signal (INTTM01n) is set.
Page 195: (With Both Edges Specified)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-26. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) Count clock 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 D2 + 2 TM0n count value TI00n pin input CR01n capture value...
Page 196: Two Capture Registers (With Rising Edge Specified)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 0n (TM0n) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the TI00n pin. When the rising or falling edge specified by bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an interrupt request signal (INTTM01n) is set.
Page 197: And Two Capture Registers (With Rising Edge Specified)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-28. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TM0n count value 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1...
Page 198: (With Rising Edge Specified)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-29. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts at valid edge of TI00n pin. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1...
Page 199: External Event Counter Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.4 External event counter operation Setting The basic operation setting procedure is as follows. <1> Set the CRC0n register (see Figure 7-31 for the set value). <2> Set the count clock by using the PRM0n register. <3>...
Page 200: Control Register Settings In External Event Counter Mode (With Rising Edge Specified)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-31. Control Register Settings in External Event Counter Mode (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1...
Page 201: Configuration Diagram Of External Event Counter
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-32. Configuration Diagram of External Event Counter Internal bus 16-bit timer capture/compare register 00n (CR00n) Match INTTM00n Clear Noise eliminator Note OVF0n 16-bit timer counter 0n (TM0n) Valid edge of TI00n Note OVF0n is set to 1 only when CR00n is set to FFFFH.
Page 202: Square-Wave Output Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.5 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM0n register. <2> Set the CRC0n register (see Figure 7-34 for the set value). <3>...
Page 203: Square-Wave Output Operation Timing
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-34. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 LVS0n LVR0n TOC0n1 TOE0n TOC0n Enables TO0n output. Inverts output on match between TM0n and CR00n. Specifies initial value of TO0n output F/F (setting “11”...
Page 204: One-Shot Pulse Output Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.6 One-shot pulse output operation 16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI00n pin input). Setting The basic operation setting procedure is as follows. <1>...
Page 205: Control Register Settings For One-Shot Pulse Output With Software Trigger
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-36. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Free-running mode (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CRC0n CR00n as compare register...
Page 206: Timing Of One-Shot Pulse Output Operation With Software Trigger
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-37. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC0n to 0CH (TM0n count starts) Count clock TM0n count 0000H 0001H N + 1 0000H N – 1 M – 1 M + 1 M + 2 CR01n set value CR00n set value...
Page 207: (With Rising Edge Specified)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-38. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts at valid edge of TI00n pin.
Page 208: Timing Of One-Shot Pulse Output Operation With External Trigger (With Rising Edge Specified)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-39. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC0n is set to 08H (TM0n count starts) Count clock − − TM0n count value 0000H 0001H 0000H N + 1 N + 2...
Page 209: Cautions For 16-Bit Timer/Event Counters 00 And 01
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Cautions for 16-Bit Timer/Event Counters 00 and 01 (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 0n (TM0n) is started asynchronously to the count clock.
Page 210 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (6) Operation of OVF0n flag <1> The OVF0n flag is also set to 1 in the following case. When any of the following modes is selected: the mode in which clear & start occurs on a match between TM0n and CR00n, the mode in which clear &...
Page 211 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (8) Timer operation <1> Even if 16-bit timer counter 0n (TM0n) is read, the value is not captured by 16-bit timer capture/compare register 01n (CR01n). <2> Regardless of the CPU’s operation mode, when the timer stops, the input signals to the TI00n/TI01n pins are not acknowledged.
Page 212: Chapter 8 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. • Interval timer • External event counter • Square-wave output • PWM output Figures 8-1 and 8-2 show the block diagrams of 8-bit timer/event counters 50 and 51. Figure 8-1.
Page 213 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-2. Block Diagram of 8-Bit Timer/Event Counter 51 Internal bus 8-bit timer compare Selector INTTM51 register 51 (CR51) TI51/TO51/P33/INTP4 Match Note 1 8-bit timer TO51/TI51/ counter 51 (TM51) P33/INTP4 Clear Note 2 Output latch PM33 (P33)
Page 214: Configuration Of 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 consist of the following hardware. Table 8-1. Configuration of 8-Bit Timer/Event Counters 50 and 51 Item Configuration Timer register 8-bit timer counter 5n (TM5n) Register 8-bit timer compare register 5n (CR5n)
Page 215 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer compare register 5n (CR5n) CR5n can be read and written by an 8-bit memory manipulation instruction. Except in PWM mode, the value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count value, and an interrupt request (INTTM5n) is generated if they match.
Page 216: Registers Controlling 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. • Timer clock selection register 5n (TCL5n) • 8-bit timer mode control register 5n (TMC5n) •...
Page 217 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH After reset: 00H Symbol TCL51 TCL512 TCL511 TCL510 TCL512 TCL511 TCL510 Count clock selection TI51 falling edge TI51 rising edge (10 MHz) /2 (5 MHz) (625 kHz)
Page 218 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3>...
Page 219 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Address: FF43H After reset: 00H Symbol <7> <3> <2> <0> TMC51 TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 TCE51 TM51 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start TMC516...
Page 220 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port mode registers 1 and 3 (PM1, PM3) These registers set port 1 and 3 input/output in 1-bit units. When using the P17/TO50/TI50 and P33/TO51/TI51 pins for timer output, clear PM17 and PM33 and the output latches of P17 and P33 to 0.
Page 221: Operations Of 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Operations of 8-Bit Timer/Event Counters 50 and 51 8.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated.
Page 222 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-11. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H Count clock TM5n CR5n TCE5n INTTM5n Interval time (c) When CR5n = FFH Count clock TM5n CR5n TCE5n INTTM5n Interrupt acknowledged Interrupt acknowledged Interval time...
Page 223: Operation As External Event Counter
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to TI5n by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the rising or falling edge can be selected.
Page 224: Square-Wave Output Operation
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1.
Page 225: Pwm Output Operation
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-13. Square-Wave Output Operation Timing Count clock N − 1 N − 1 TM5n count value Count start CR5n Note TO5n Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n).
Page 226 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) PWM output basic operation Setting <1> Set each register. • Clear the port output latch (P17 or P33) Note Note and port mode register (PM17 or PM33) to 0. • TCL5n: Select the count clock. •...
Page 227 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-14. PWM Output Operation Timing (a) Basic operation (active level = H) Count clock TM5n 00H 01H FFH 00H 01H 02H N N + 1 FFH 00H 01H 02H CR5n TCE5n INTTM5n TO5n <5>...
Page 228 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation with CR5n changed Figure 8-15. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH → Value is transferred to CR5n at overflow immediately after change. Count clock TM5n N N + 1 N + 2...
Page 229: Cautions For 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Cautions for 8-Bit Timer/Event Counters 50 and 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock.
Page 230: Chapter 9 8-Bit Timers H0 And H1
CHAPTER 9 8-BIT TIMERS H0 AND H1 Functions of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 have the following functions. • Interval timer • PWM output mode • Square-wave output • Carrier generator mode (8-bit timer H1 only) Configuration of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 consist of the following hardware.
Page 231 Figure 9-1. Block Diagram of 8-Bit Timer H0 Internal bus 8-bit timer H mode control register 0 (TMHMD0) TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 8-bit timer H 8-bit timer H compare register compare register 00 (CMP00) 10 (CMP10) Decoder TOH0/P15 Selector...
Page 232 Figure 9-2. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode control 8-bit timer H carrier register 1 (TMHMD1) control register 1 (TMCYC1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 8-bit timer H 8-bit timer H RMC1 NRZB1 NRZ1 compare compare...
Page 233 CHAPTER 9 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register 0n (CMP0n) This register can be read or written by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 9-3. Format of 8-Bit Timer H Compare Register 0n (CMP0n) Address: FF18H (CMP00), FF1AH (CMP01) After reset: 00H Symbol...
Page 234: Registers Controlling 8-Bit Timers H0 And H1
CHAPTER 9 8-BIT TIMERS H0 AND H1 Registers Controlling 8-Bit Timers H0 and H1 The following four registers are used to control 8-bit timers H0 and H1. • 8-bit timer H mode register n (TMHMDn) • 8-bit timer H carrier control register 1 (TMCYC1) Note •...
Page 235 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Address: FF69H After reset: 00H <7> <1> <0> TMHMD0 TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 TMHE0 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) CKS02 CKS01...
Page 236 CHAPTER 9 8-BIT TIMERS H0 AND H1 Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 8-bit timer H0 is not guaranteed.
Page 237 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF6CH After reset: 00H <7> <1> <0> TMHMD1 TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHE1 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) CKS12 CKS11...
Page 238 CHAPTER 9 8-BIT TIMERS H0 AND H1 Remarks 1. f : X1 input clock oscillation frequency 2. f : Ring-OSC clock oscillation frequency 3. Figures in parentheses apply to operation at f = 10 MHz, f = 240 kHz (TYP.). (2) 8-bit timer H carrier control register 1 (TMCYC1) This register controls the remote control output and carrier pulse output status of 8-bit timer H1.
Page 239: Operation Of 8-Bit Timers H0 And H1
CHAPTER 9 8-BIT TIMERS H0 AND H1 Operation of 8-Bit Timers H0 and H1 9.4.1 Operation as interval timer/square-wave output When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode.
Page 240 CHAPTER 9 8-BIT TIMERS H0 AND H1 (2) Timing chart The timing of the interval timer/square-wave output operation is shown below. Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation Count clock Count start 01H 00H 8-bit timer counter Hn Clear Clear CMP0n...
Page 241 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP0n = FFH Count clock Count start 8-bit timer counter Hn Clear Clear CMP0n TMHEn INTTMHn TOHn Interval time (c) Operation when CMP0n = 00H Count clock Count start 8-bit timer counter Hn...
Page 242: Operation As Pwm Output Mode
CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited.
Page 243 CHAPTER 9 8-BIT TIMERS H0 AND H1 <4> When 8-bit timer counter Hn and the CMP1n register match, TOHn output becomes inactive and the compare register to be compared with 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n register.
Page 244 CHAPTER 9 8-BIT TIMERS H0 AND H1 (2) Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H ≤...
Page 245 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP0n CMP1n...
Page 246 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 01H 00H 01H 00H 00H 01H 00H 01H 8-bit timer counter Hn CMP0n CMP1n TMHEn INTTMHn...
Page 247 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 01H → 03H, CMP0n = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H CMP0n...
Page 248: Carrier Generator Mode Operation (8-Bit Timer H1 Only)
CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.3 Carrier generator mode operation (8-bit timer H1 only) The carrier clock generated by 8-bit timer H1 is output in the cycle set by 8-bit timer/event counter 51. In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by 8-bit timer/event counter 51, and the carrier pulse is output from the TOH1 output.
Page 249 CHAPTER 9 8-BIT TIMERS H0 AND H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and output as the INTTM5H1 signal.
Page 250 CHAPTER 9 8-BIT TIMERS H0 AND H1 (3) Usage Outputs an arbitrary carrier clock from the TOH1 pin. <1> Set each register. Figure 9-14. Register Setting in Carrier Generator Mode Setting 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11...
Page 251 CHAPTER 9 8-BIT TIMERS H0 AND H1 If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is f , the carrier clock output cycle and duty are as follows. Carrier clock output cycle = (N + M + 2)/f Duty = High-level width : Carrier clock output width = ( M + 1) : (N + M + 2) Cautions 1.
Page 252 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = N, CMP11 = N 8-bit timer Hn count clock 8-bit timer counter N 00H N 00H N 00H N 00H N 00H Hn count value CMPn0...
Page 253 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = N, CMP11 = M 8-bit timer Hn count clock 8-bit timer counter N 00H 01H M 00H N 00H 01H M 00H Hn count value CMPn0...
Page 254 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter 00H 01H 00H 01H H1 count value CMP01 <3> <3>’ CMP11 M (L) TMHE1 INTTMH1...
Page 255: Chapter 10 Watch Timer
CHAPTER 10 WATCH TIMER 10.1 Functions of Watch Timer The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. Figure 10-1 shows the watch timer block diagram. Figure 10-1.
Page 256 CHAPTER 10 WATCH TIMER (1) Watch timer When the X1 input clock or subsystem clock is used, interrupt requests (INTWT) are generated at preset intervals. Table 10-1. Watch Timer Interrupt Time Interrupt Time When Operated at f = 32.768 kHz When Operated at f = 10 MHz µ...
Page 257: Configuration Of Watch Timer
CHAPTER 10 WATCH TIMER 10.2 Configuration of Watch Timer The watch timer consists of the following hardware. Table 10-3. Watch Timer Configuration Item Configuration 5 bits × 1 Counter 11 bits × 1 Prescaler Control register Watch timer operation mode register (WTM) 10.3 Register Controlling Watch Timer The watch timer is controlled by the watch timer operation mode register (WTM).
Page 258 CHAPTER 10 WATCH TIMER Figure 10-2. Format of Watch Timer Operation Mode Register (WTM) Address: FF6FH After reset: 00H Symbol <1> <0> WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 WTM7 Watch timer count clock selection (78.125 kHz) (32.768 kHz) WTM6 WTM5 WTM4...
Page 259: Watch Timer Operations
CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation The watch timer generates an interrupt request (INTWT) at a specific time interval by using the X1 input clock or subsystem clock. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count operation starts.
Page 260: Interval Timer Operation
CHAPTER 10 WATCH TIMER 10.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests (INTWTI) repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register (WTM).
Page 261: Cautions For Watch Timer
CHAPTER 10 WATCH TIMER 10.5 Cautions for Watch Timer When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request (INTWT) is generated after the register is set does not exactly match the specification made with bit 3 (WTM3) of WTM.
Page 262: Chapter 11 Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.1 Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 22 RESET FUNCTION.
Page 263 CHAPTER 11 WATCHDOG TIMER Table 11-2. Mask Option Setting and Watchdog Timer Operation Mode Mask Option Ring-OSC Cannot Be Stopped Ring-OSC Can Be Stopped by Software • Selectable by software (f Note 1 or stopped) Watchdog timer clock Fixed to f •...
Page 264: Configuration Of Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.2 Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 11-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) Figure 11-1. Block Diagram of Watchdog Timer Clock Output 16-bit...
Page 265: Registers Controlling Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.3 Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. • Watchdog timer mode register (WDTM) • Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock of the watchdog timer. This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be written only once after reset is released.
Page 266: Format Of Watchdog Timer Enable Register (Wdte)
CHAPTER 11 WATCHDOG TIMER Cautions 1. If data is written to WDTM, a wait cycle is generated. Do not write data to WDTM when the CPU is operating on the subsystem clock and the X1 input clock is stopped. For details, see CHAPTER 35 CAUTIONS FOR WAIT. 2.
Page 267: Operation Of Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.4 Operation of Watchdog Timer 11.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by mask option The operation clock of watchdog timer is fixed to the Ring-OSC. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
Page 268: Watchdog Timer Operation When "Ring-Osc Can Be Stopped By Software" Is Selected By Mask Option
CHAPTER 11 WATCHDOG TIMER 11.4.2 Watchdog timer operation when “Ring-OSC can be stopped by software” is selected by mask option The operation clock of the watchdog timer can be selected as either the Ring-OSC clock or the X1 input clock. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
Page 269: Watchdog Timer Operation In Stop Mode (When "Ring-Osc Can Be Stopped By Software" Is Selected By Mask Option)
CHAPTER 11 WATCHDOG TIMER 11.4.3 Watchdog timer operation in STOP mode (when “Ring-OSC can be stopped by software” is selected by mask option) The watchdog timer stops counting during STOP instruction execution regardless of whether the X1 input clock or Ring-OSC clock is being used.
Page 270: Operation In Stop Mode (Cpu Clock: Ring-Osc Clock, Wdt Operation Clock: X1 Input Clock)
CHAPTER 11 WATCHDOG TIMER (3) When the CPU clock is the Ring-OSC clock (f ) and the watchdog timer operation clock is the X1 input clock (f ) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is stopped until the timing of <1>...
Page 271: Watchdog Timer Operation In Halt Mode (When "Ring-Osc Can Be Stopped By Software" Is Selected By Mask Option)
CHAPTER 11 WATCHDOG TIMER (4) When CPU clock and watchdog timer operation clock are the Ring-OSC clocks (f ) during STOP instruction execution When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is started again using the operation clock before the operation was stopped.
Page 272: Chapter 12 Clock Output/Buzzer Output Controller
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs. The clock selected with the clock output selection register (CKS) is output. In addition, the buzzer output is intended for square-wave output of buzzer frequency selected with CKS.
Page 273: Configuration Of Clock Output/Buzzer Output Controller
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller consists of the following hardware. Table 12-1. Clock Output/Buzzer Output Controller Configuration Item Configuration Control registers Clock output selection register (CKS) Port mode register 14 (PM14) Port register 14 (P14) 12.3 Register Controlling Clock Output/Buzzer Output Controller The following two registers are used to control the clock output/buzzer output controller.
Page 274: Format Of Clock Output Selection Register (Cks)
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 12-2. Format of Clock Output Selection Register (CKS) Address: FF40H After reset: 00H Symbol <7> <4> BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0 BZOE BUZ output enable/disable specification Clock division circuit operation stopped. BUZ fixed to low level. Clock division circuit operation enabled.
Page 275: Format Of Port Mode Register 14 (Pm14)
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (2) Port mode register 14 (PM14) This register sets port 14 input/output in 1-bit units. When using the P140/INTP6/PCL pin for clock output and the P141/BUSY0/INTP7/BUZ pin for buzzer output, clear PM140, PM141 and the output latch of P140, P141 to 0. PM14 is set by a 1-bit or 8-bit memory manipulation instruction.
Page 276: Clock Output/Buzzer Output Controller Operations
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.4 Clock Output/Buzzer Output Controller Operations 12.4.1 Clock output operation The clock pulse is output as the following procedure. <1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register (CKS) (clock pulse output in disabled status).
Page 277: Chapter 13 A/D Converter
CHAPTER 13 A/D CONVERTER 13.1 Functions of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to eight channels (ANI0 to ANI7) with a resolution of 10 bits. The A/D converter has the following two functions. (1) 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI7.
Page 278: Configuration Of A/D Converter
CHAPTER 13 A/D CONVERTER 13.2 Configuration of A/D Converter The A/D converter consists of the following hardware. Table 13-1. Registers of A/D Converter Used on Software Item Configuration Registers Successive approximation register (SAR) A/D conversion result register (ADCR) A/D converter mode register (ADM) Analog input channel specification register (ADS) Power-fail comparison mode register (PFM) Power-fail comparison threshold register (PFT)
Page 279 CHAPTER 13 A/D CONVERTER (8) AV This pin inputs an analog power/reference voltage to the A/D converter. Always use this pin at the same potential as that of the V pin even when the A/D converter is not used. The signal input to ANI0 to ANI7 is converted into a digital signal, based on the voltage applied across AV In the standby mode, the current flowing through the series resistor string can be reduced by lowering the voltage input to the AV pin to the AV...
Page 280: Registers Used In A/D Converter
CHAPTER 13 A/D CONVERTER 13.3 Registers Used in A/D Converter The A/D converter uses the following five registers. • A/D converter mode register (ADM) • Analog input channel specification register (ADS) • A/D conversion result register (ADCR) • Power-fail comparison mode register (PFM) •...
Page 281: Format Of A/D Converter Mode Register (Adm)
CHAPTER 13 A/D CONVERTER (1) A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. ADM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 13-2.
Page 282: Timing Chart When Boost Reference Voltage Generator Is Used
CHAPTER 13 A/D CONVERTER Table 13-2. Settings of ADCS and ADCE ADCS ADCE A/D Conversion Operation Stop status (DC power consumption path does not exist) Conversion waiting mode (only reference voltage generator consumes power) Note Conversion mode (reference voltage generator operation stopped Conversion mode (reference voltage generator operates) Note Data of first conversion cannot be used.
Page 283: Format Of Analog Input Channel Specification Register (Ads)
CHAPTER 13 A/D CONVERTER (2) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 13-4.
Page 284: Format Of A/D Conversion Result Register (Adcr)
CHAPTER 13 A/D CONVERTER (3) A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The lower six bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is stored in ADCR in order starting from the most significant bit (MSB).
Page 285: Format Of Power-Fail Comparison Mode Register (Pfm)
CHAPTER 13 A/D CONVERTER (4) Power-fail comparison mode register (PFM) The power-fail comparison mode register (PFM) is used to compare the A/D conversion result (value of the ADCR register) and the value of the power-fail comparison threshold register (PFT). PFM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 286: A/D Converter Operations
CHAPTER 13 A/D CONVERTER 13.4 A/D Converter Operations 13.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion using the analog input channel specification register (ADS). µ <2> Set ADCE to 1 and wait for 14 s or longer. <3>...
Page 287: Basic Operation Of A/D Converter
CHAPTER 13 A/D CONVERTER Figure 13-8. Basic Operation of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.
Page 288: Input Voltage And Conversion Results
CHAPTER 13 A/D CONVERTER 13.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the theoretical A/D conversion result (stored in the A/D conversion result register (ADCR)) is shown by the following expression. ×...
Page 289: A/D Converter Operation Mode
CHAPTER 13 A/D CONVERTER 13.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI7 by the analog input channel specification register (ADS) and A/D conversion is executed. In addition, the following two functions can be selected by setting of bit 7 (PFEN) of the power-fail comparison mode register (PFM).
Page 290: Power-Fail Detection (When Pfen = 1 And Pfcm = 0)
CHAPTER 13 A/D CONVERTER (2) Power-fail detection function (when PFEN = 1) By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail comparison mode register (PFM) to 1, the A/D conversion operation of the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) is started.
Page 291 CHAPTER 13 A/D CONVERTER The setting methods are described below. • When used as A/D conversion operation <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Select the channel and conversion time using bits 2 to 0 (ADS2 to ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.
Page 292: How To Read A/D Converter Characteristics Table
CHAPTER 13 A/D CONVERTER 13.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 293: Zero-Scale Error
CHAPTER 13 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale − 3/2LSB) when the digital output changes from 1..110 to 1..111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.
Page 294: Cautions For A/D Converter
CHAPTER 13 A/D CONVERTER 13.6 Cautions for A/D Converter (1) Operating current in standby mode The A/D converter stops operating in the standby mode. At this time, the operating current can be reduced by clearing bit 7 (ADCS) of the A/D converter mode register (ADM) to 0. Figure 13-18 shows the circuit configuration of the series resistor string.
Page 295: Analog Input Pin Connection
CHAPTER 13 A/D CONVERTER (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AV pin and pins ANI0 to ANI7. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in Figure 13-19, to reduce noise.
Page 296: Timing Of A/D Conversion End Interrupt Request Generation
CHAPTER 13 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite.
Page 297: Timing Of A/D Converter Sampling And A/D Conversion Start Delay
CHAPTER 13 A/D CONVERTER (11) A/D converter sampling time and A/D conversion start delay time The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM). The delay time exists until actual sampling is started after A/D converter operation is enabled. When using a set in which the A/D conversion time must be strictly observed, care is required for the contents shown in Figure 13-21 and Table 13-3.
Page 298: Internal Equivalent Circuit Of Anin Pin
CHAPTER 13 A/D CONVERTER (13) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 13-22. Internal Equivalent Circuit of ANIn Pin ANIn Table 13-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) 2.7 V 12 kΩ...
Page 299: Chapter 14 Serial Interface Uart0
CHAPTER 14 SERIAL INTERFACE UART0 14.1 Functions of Serial Interface UART0 Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
Page 300: Configuration Of Serial Interface Uart0
CHAPTER 14 SERIAL INTERFACE UART0 14.2 Configuration of Serial Interface UART0 Serial interface UART0 consists of the following hardware. Table 14-1. Configuration of Serial Interface UART0 Item Configuration Registers Receive buffer register 0 (RXB0) Receive shift register 0 (RXS0) Transmit shift register 0 (TXS0) Control registers Asynchronous serial interface operation mode register 0 (ASIM0) Asynchronous serial interface reception error status register 0 (ASIS0)
Page 301: Block Diagram Of Serial Interface Uart0
Figure 14-1. Block Diagram of Serial Interface UART0 Filter SI10/P11 Receive shift register 0 (RXS0) Asynchronous serial Asynchronous serial INTSR0 Reception control Receive buffer register 0 Baud rate interface operation mode interface reception error (RXB0) generator register 0 (ASIM0) status register 0 (ASIS0) Reception unit Internal bus 8-bit timer/...
Page 302 CHAPTER 14 SERIAL INTERFACE UART0 (1) Receive buffer register 0 (RXB0) This 8-bit register stores parallel data converted by receive shift register 0 (RXS0). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (RXS0).
Page 303: Registers Controlling Serial Interface Uart0
CHAPTER 14 SERIAL INTERFACE UART0 14.3 Registers Controlling Serial Interface UART0 Serial interface UART0 is controlled by the following five registers. • Asynchronous serial interface operation mode register 0 (ASIM0) • Asynchronous serial interface reception error status register 0 (ASIS0) •...
Page 304 CHAPTER 14 SERIAL INTERFACE UART0 Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2) PS01 PS00 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity.
Page 305: Format Of Asynchronous Serial Interface Reception Error Status Register 0 (Asis0)
CHAPTER 14 SERIAL INTERFACE UART0 (2) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register is read-only by an 8-bit memory manipulation instruction. RESET input clears this register to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0.
Page 306: Format Of Baud Rate Generator Control Register 0 (Brgc0)
CHAPTER 14 SERIAL INTERFACE UART0 (3) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter. BRGC0 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to 1FH.
Page 307: Format Of Port Mode Register 1 (Pm1)
CHAPTER 14 SERIAL INTERFACE UART0 Remarks 1. f : Frequency of base clock selected by the TPS01 and TPS00 bits XCLK0 2. f X1 input clock oscillation frequency 3. k: Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31) 4.
Page 308: Operation Of Serial Interface Uart0
CHAPTER 14 SERIAL INTERFACE UART0 14.4 Operation of Serial Interface UART0 Serial interface UART0 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 14.4.1 Operation stop mode In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pins can be used as ordinary port pins in this mode.
Page 309: Asynchronous Serial Interface (Uart) Mode
CHAPTER 14 SERIAL INTERFACE UART0 14.4.2 Asynchronous serial interface (UART) mode In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 310: Format Of Normal Uart Transmit/Receive Data
CHAPTER 14 SERIAL INTERFACE UART0 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 14-6 and 14-7 show the format and waveform example of the normal transmit/receive data. Figure 14-6. Format of Normal UART Transmit/Receive Data 1 data frame Start Parity...
Page 311 CHAPTER 14 SERIAL INTERFACE UART0 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 312: Transmission Completion Interrupt Request Timing
CHAPTER 14 SERIAL INTERFACE UART0 (c) Transmission The T D0 pin outputs a high level when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1. If bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit shift register 0 (TXS0).
Page 313: Reception Completion Interrupt Request Timing
CHAPTER 14 SERIAL INTERFACE UART0 (d) Reception Reception is enabled and the R D0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1. The 5-bit counter of the baud rate generator starts counting when the falling edge of the R D0 pin input is detected.
Page 314: Noise Filter Circuit
CHAPTER 14 SERIAL INTERFACE UART0 (e) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a reception error interrupt request (INTSR0) is generated.
Page 315: Dedicated Baud Rate Generator
CHAPTER 14 SERIAL INTERFACE UART0 14.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of UART0. Separate 5-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
Page 316 CHAPTER 14 SERIAL INTERFACE UART0 (2) Generation of serial clock A serial clock can be generated by using baud rate generator control register 0 (BRGC0). Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0. Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value of the 5-bit counter.
Page 317 CHAPTER 14 SERIAL INTERFACE UART0 (3) Example of setting baud rate Table 14-4. Set Data of Baud Rate Generator Baud Rate = 10.0 MHz = 8.38 MHz = 4.19 MHz [bps] TPS01, Calculated ERR[%] TPS01, Calculated ERR[%] TPS01, Calculated ERR[%] TPS00 Value TPS00...
Page 318: Permissible Baud Rate Range During Reception
CHAPTER 14 SERIAL INTERFACE UART0 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
Page 319 CHAPTER 14 SERIAL INTERFACE UART0 k − 2 21k + 2 Minimum permissible data frame length: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. −1 BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows.
Page 320: Chapter 15 Serial Interface Uart6
CHAPTER 15 SERIAL INTERFACE UART6 15.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
Page 321: Lin Transmission Operation
CHAPTER 15 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master.
Page 322: Lin Reception Operation
CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-2. LIN Reception Operation Wakeup Synchronous Synchronous Indent Data field Data field Checksum signal frame break field field field field Sleep Data Data Data Note 5 reception reception reception reception reception Note 2 13 bits reception Disable Enable...
Page 323: Port Configuration For Lin Reception Operation
CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-3. Port Configuration for LIN Reception Operation Selector P14/RxD6 RXD6 input Port mode (PM14) Output latch (P14) Selector Selector P120/INTP0 INTP0 input Port mode Port input (PM120) switch control (ISC0) Output latch <ISC0> (P120) 0: Select INTP0 (P120) 1: Select RxD6 (P14) Selector...
Page 324: Configuration Of Serial Interface Uart6
CHAPTER 15 SERIAL INTERFACE UART6 15.2 Configuration of Serial Interface UART6 Serial interface UART6 consists of the following hardware. Table 15-1. Configuration of Serial Interface UART6 Item Configuration Registers Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers Asynchronous serial interface operation mode register 6 (ASIM6)
Page 325: Block Diagram Of Serial Interface Uart6
Figure 15-4. Block Diagram of Serial Interface UART6 Note TI000, INTP0 Filter INTSR6 Reception control INTSRE6 Receive shift register 6 (RXS6) Asynchronous serial Asynchronous serial Asynchronous serial interface Baud rate Receive buffer register 6 interface operation mode interface reception error control register 6 (ASICL6) generator (RXB6)
Page 326 CHAPTER 15 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (RXS6).
Page 327: Registers Controlling Serial Interface Uart6
CHAPTER 15 SERIAL INTERFACE UART6 15.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. • Asynchronous serial interface operation mode register 6 (ASIM6) • Asynchronous serial interface reception error status register 6 (ASIS6) •...
Page 328 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) RXE6 Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception PS61 PS60 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity.
Page 329: Format Of Asynchronous Serial Interface Reception Error Status Register 6 (Asis6)
CHAPTER 15 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. RESET input clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0.
Page 330: Format Of Asynchronous Serial Interface Transmission Status Register 6 (Asif6)
CHAPTER 15 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
Page 331: Format Of Clock Selection Register 6 (Cksr6)
CHAPTER 15 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 332: Format Of Baud Rate Generator Control Register 6 (Brgc6)
CHAPTER 15 SERIAL INTERFACE UART6 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 333: Format Of Asynchronous Serial Interface Control Register 6 (Asicl6)
CHAPTER 15 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 334: Format Of Input Switch Control Register (Isc)
CHAPTER 15 SERIAL INTERFACE UART6 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The input signal is switched by setting ISC. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 335: Operation Of Serial Interface Uart6
CHAPTER 15 SERIAL INTERFACE UART6 15.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 15.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode.
Page 336: Asynchronous Serial Interface (Uart) Mode
CHAPTER 15 SERIAL INTERFACE UART6 15.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 337 CHAPTER 15 SERIAL INTERFACE UART6 The relationship between the register settings and pins is shown below. Table 15-2. Relationship Between Register Settings and Pins POWER6 TXE6 RXE6 PM13 PM14 UART6 Pin Function Operation TxD6/P13 RxD6/P14 Note Note Note Note × ×...
Page 338: Format Of Normal Uart Transmit/Receive Data
CHAPTER 15 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 15-13 and 15-14 show the format and waveform example of the normal transmit/receive data. Figure 15-13. Format of Normal UART Transmit/Receive Data 1.
Page 339: Example Of Normal Uart Transmit/Receive Data Waveform
CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-14. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity...
Page 340 CHAPTER 15 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 341: Normal Transmission Completion Interrupt Request Timing
CHAPTER 15 SERIAL INTERFACE UART6 (c) Normal transmission The T D6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1. If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6).
Page 342 CHAPTER 15 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized.
Page 343: Example Of Continuous Transmission Processing Flow
CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-16 shows an example of the continuous transmission processing flow. Figure 15-16. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Read ASIF6 TXBF6 = 0? Write TXB6. Transmission completion interrupt occurs?
Page 344: Timing Of Starting Continuous Transmission
CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-17 shows the timing of starting continuous transmission, and Figure 15-18 shows the timing of ending continuous transmission. Figure 15-17. Timing of Starting Continuous Transmission Start Data (1) Parity Stop Start Data (2) Parity Stop Start INTST6...
Page 345: Timing Of Ending Continuous Transmission
CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-18. Timing of Ending Continuous Transmission Data (n − 1) Start Start Parity Data (n) Parity Stop Stop Stop INTST6 Data (n − 1) TXB6 Data (n) Data (n − 1) TXS6 Data (n) TXBF6 TXSF6 POWER6 or TXE6...
Page 346: Reception Completion Interrupt Request Timing
CHAPTER 15 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the R D6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the R D6 pin input is detected.
Page 347: Reception Error Interrupt
CHAPTER 15 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.
Page 348: Noise Filter Circuit
CHAPTER 15 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RXD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data.
Page 349: Example Of Setting Procedure Of Sbf Transmission (Flowchart)
CHAPTER 15 SERIAL INTERFACE UART6 If the number of bits set by BRGC6 runs short, adjust the number of bits by setting the base clock of UART6. Figure 15-22. Example of Setting Procedure of SBF Transmission (Flowchart) Start Read BRGC6 register and save current set value of BRGC6 register to general- purpose register.
Page 350: Sbf Reception
CHAPTER 15 SERIAL INTERFACE UART6 SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 15-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
Page 351: Dedicated Baud Rate Generator
CHAPTER 15 SERIAL INTERFACE UART6 15.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
Page 352: Configuration Of Baud Rate Generator
CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-25. Configuration of Baud Rate Generator POWER6 Baud rate generator POWER6, TXE6 (or RXE6) Selector 8-bit counter XCLK6 Match detector Baud rate 8-bit timer/ event counter 50 output CKSR6: TPS63 to TPS60 BRGC6: MDL67 to MDL60 Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6...
Page 353 CHAPTER 15 SERIAL INTERFACE UART6 (2) Generation of serial clock A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control register 6 (BRGC6). Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6. Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter.
Page 354 CHAPTER 15 SERIAL INTERFACE UART6 (3) Example of setting baud rate Table 15-4. Set Data of Baud Rate Generator Baud Rate = 10.0 MHz = 8.38 MHz = 4.19 MHz [bps] TPS63 to Calculated ERR[%] TPS63 to Calculated ERR[%] TPS63 to Calculated ERR[%] TPS60...
Page 355: Permissible Baud Rate Range During Reception
CHAPTER 15 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
Page 356 CHAPTER 15 SERIAL INTERFACE UART6 k − 2 21k + 2 Minimum permissible data frame length: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. −1 BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows.
Page 357: Data Frame Length During Continuous Transmission
CHAPTER 15 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected.
Page 358: Chapter 16 Serial Interfaces Csi10 And Csi11
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 µ µ PD780143 and 780144 incorporate serial interface CSI10, and the PD780146, 780148, and 78F0148 incorporate serial interfaces CSI10 and CSI11. 16.1 Functions of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 have the following two modes. •...
Page 359: Configuration Of Serial Interfaces Csi10 And Csi11
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.2 Configuration of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 consist of the following hardware. Table 16-1. Configuration of Serial Interfaces CSI10 and CSI11 Item Configuration Registers Transmit buffer register 1n (SOTB1n) Serial I/O shift register 1n (SIO1n) Transmit controller Clock start/stop controller &...
Page 360: Pd780146, 780148, And 78F0148 Only)
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 µ Figure 16-2. Block Diagram of Serial Interface CSI11 ( PD780146, 780148, and 78F0148 Only) Internal bus Serial I/O shift Transmit buffer Output SI11/P03 register 11 (SIO11) register 11 (SOTB11) SO11/P02 selector Output latch Transmit data Output latch (P02)
Page 361: Registers Controlling Serial Interfaces Csi10 And Csi11
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.3 Registers Controlling Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 are controlled by the following four registers. • Serial operation mode register 1n (CSIM1n) • Serial clock selection register 1n (CSIC1n) •...
Page 362: Format Of Serial Operation Mode Register 11 (Csim11)
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-4. Format of Serial Operation Mode Register 11 (CSIM11) Note 1 Address: FF88H After reset: 00H R/W Symbol <7> CSIM11 CSIE11 TRMD11 SSE11 DIR11 CSOT11 CSIE11 Operation control in 3-wire serial I/O mode Note 2 Note 3 Disables operation...
Page 363: Format Of Serial Clock Selection Register 10 (Csic10)
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (2) Serial clock selection register 1n (CSIC1n) This register specifies the timing of the data transmission/reception and sets the serial clock. CSIC1n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 364 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Cautions 1. When the Ring-OSC clock is selected as the clock supplied to the CPU, the clock of the Ring- OSC oscillator is divided and supplied as the serial clock. At this time, the operation of serial interface CSI10 is not guaranteed.
Page 365: Format Of Serial Clock Selection Register 11 (Csic11)
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-6. Format of Serial Clock Selection Register 11 (CSIC11) Address: FF89H After reset: 00H R/W Symbol CSIC11 CKP11 DAP11 CKS112 CKS111 CKS110 CKP11 DAP11 Specification of data transmission/reception timing Type SCK11 SO11 D7 D6 D5 D4 D3 D2 D1 D0 SI11 input timing SCK11...
Page 366: Format Of Port Mode Register 0 (Pm0)
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (3) Port mode registers 0 and 1 (PM0, PM1) These registers set port 0 and 1 input/output in 1-bit units. Note When using P10/SCK10 and P04/SCK11 as the clock output pins of the serial interface, and P12/SO10 and Note P02/SO11 as the data output pins, clear PM10, PM04, PM12, PM02, and the output latches of P10, P04, P12,...
Page 367: Operation Of Serial Interfaces Csi10 And Csi11
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.4 Operation of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 can be used in the following two modes. • Operation stop mode • 3-wire serial I/O mode 16.4.1 Operation stop mode Serial communication is not executed in this mode.
Page 368: 3-Wire Serial I/O Mode
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK1n), serial output (SO1n), and serial input (SI1n) lines.
Page 369 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 The relationship between the register settings and pins is shown below. Table 16-2. Relationship Between Register Settings and Pins (1/2) (a) Serial interface CSI10 CSIE10 TRMD10 PM11 PM12 PM10 CSI10 Pin Function Operation SI10/RxD0/ SO10/P12 SCK10/...
Page 370 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Table 16-2. Relationship Between Register Settings and Pins (2/2) µ (b) Serial interface CSI11 ( PD780146, 780148, 78F0148 only) CSIE11 TRMD11 SSE11 PM03 P03 PM02 P02 PM04 P04 PM05 P05 CSI11 Pin Function Operation SI11/ SO11/...
Page 371 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1. Transmission/reception is started when a value is written to transmit buffer register 1n (SOTB1n).
Page 372: Timing In 3-Wire Serial I/O Mode
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-9. Timing in 3-Wire Serial I/O Mode (1/2) Note (1) Transmission/reception timing (Type 1; TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 0, SSE11 = 1 Note SSI11 SCK1n Read/write trigger SOTB1n 55H (communication data)
Page 373 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-9. Timing in 3-Wire Serial I/O Mode (2/2) Note (2) Transmission/reception timing (Type 2; TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 1, SSE11 = 1 Note SSI11 SCK1n Read/write trigger SOTB1n 55H (communication data)
Page 374: Timing Of Clock/Data Phase
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-10. Timing of Clock/Data Phase (a) Type 1; CKP1n = 0, DAP1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n CSOT1n (b) Type 2; CKP1n = 0, DAP1n = 1 SCK1n SI1n capture SO1n...
Page 375: Output Operation Of First Bit
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (3) Timing of output to SO1n pin (first bit) When communication is started, the value of transmit buffer register 1n (SOTB1n) is output from the SO1n pin. The output operation of the first bit at this time is described below. Figure 16-11.
Page 376: Output Value Of So1N Pin (Last Bit)
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (4) Output value of SO1n pin (last bit) After communication has been completed, the SO1n pin holds the output value of the last bit. Figure 16-12. Output Value of SO1n Pin (Last Bit) (1) Type 1;...
Page 377 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (5) SO1n output The status of the SO1n output is as follows if bit 7 (CSIE1n) of serial operation mode register 1n (CSIM1n) is cleared to 0. Table 16-3. SO1n Output Status TRMD1n DAP1n DIR1n SO1n Output...
Page 378: Chapter 17 Serial Interface Csia0
CHAPTER 17 SERIAL INTERFACE CSIA0 17.1 Functions of Serial Interface CSIA0 Serial interface CSIA0 has the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption.
Page 379: Configuration Of Serial Interface Csia0
CHAPTER 17 SERIAL INTERFACE CSIA0 17.2 Configuration of Serial Interface CSIA0 Serial interface CSIA0 consists of the following hardware. Table 17-1. Configuration of Serial Interface CSIA0 Item Configuration Registers Serial I/O shift register 0 (SIOA0) Automatic data transfer address count register 0 (ADTC0) Control registers Serial operation mode specification register 0 (CSIMA0) Serial status register 0 (CSIS0)
Page 380: Block Diagram Of Serial Interface Csia0
Figure 17-1. Block Diagram of Serial Interface CSIA0 Automatic data Automatic data transfer address transfer address Buffer RAM point specification count register 0 register 0 (ADTP0) (ADTC0) Internal bus ATE0 Serial trigger register 0 (CSIT0) DIR0 RXAE ATM0 Divisor selection Serial I/O shift register 0 ATSTP0 ATSTA0...
Page 381: Registers Controlling Serial Interface Csia0
CHAPTER 17 SERIAL INTERFACE CSIA0 (1) Serial I/O shift register 0 (SIOA0) This is an 8-bit register used to store transmit/receive data in 1-byte transfer mode (bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 0). Writing transmit data to SIOA0 starts the communication.
Page 382: Format Of Serial Operation Mode Specification Register 0 (Csima0)
CHAPTER 17 SERIAL INTERFACE CSIA0 (1) Serial operation mode specification register 0 (CSIMA0) This is an 8-bit register used to control the serial communication operation. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 17-3.
Page 383: Format Of Serial Status Register 0 (Csis0)
CHAPTER 17 SERIAL INTERFACE CSIA0 (2) Serial status register 0 (CSIS0) This is an 8-bit register used to control the communication operation and indicate status of CSIA0. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 384 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-4. Format of Serial Status Register 0 (CSIS0) (2/2) Note ERRE0 Bit error detection enable/disable Error detection disabled Error detection enabled ERRF0 Bit error detection flag • Bit 7 (CSIAE0) of serial operation mode specification register 0 (CSIMA0) = 0 •...
Page 385: Format Of Serial Trigger Register 0 (Csit0)
CHAPTER 17 SERIAL INTERFACE CSIA0 (3) Serial trigger register 0 (CSIT0) This is an 8-bit register used to control execution/stop of automatic data transfer between buffer RAM and serial I/O shift register 0 (SIOA0). This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 386: Format Of Divisor Selection Register 0 (Brgca0)
This register can be set by an 8-bit memory manipulation instruction. However, when bit 0 (TSF0) of serial status register 0 (CSIS0) is 1, rewriting ADTP0 is prohibited. In the 78K0/KF1, 00H to 1FH can be specified because 32 bytes of buffer RAM are incorporated. Example When ADTP0 is set to 07H 8 bytes of FA00H to FA07H are transferred.
Page 387 CHAPTER 17 SERIAL INTERFACE CSIA0 The relationship between buffer RAM address values and ADTP0 setting values is shown below. Table 17-2. Relationship Between Buffer RAM Address Values and ADTP0 Setting Values Buffer RAM Address Value ADTP0 Setting Value Buffer RAM Address Value ADTP0 Setting Value FA00H FA10H...
Page 388: Format Of Automatic Data Transfer Interval Specification Register 0 (Adti0)
CHAPTER 17 SERIAL INTERFACE CSIA0 (6) Automatic data transfer interval specification register 0 (ADTI0) This is an 8-bit register used to specify the interval time between 1-byte communications during automatic data transfer (bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 1). Set this register when in master mode (bit 4 (MASTER0) of CSIMA0 = 1) (setting is unnecessary in slave mode).
Page 389: Format Of Port Mode Register 14 (Pm14)
CHAPTER 17 SERIAL INTERFACE CSIA0 (7) Port mode register 14 (PM14) This register sets port 14 input/output in 1-bit units. When using P142/SCKA0, P144/SOA0, and P145/STB0 pins as the clock output, data output, or strobe output of the serial interface, clear PM142, PM144, PM145, and the output latches of P142, P144, and P145 to 0.
Page 390: Operation Of Serial Interface Csia0
CHAPTER 17 SERIAL INTERFACE CSIA0 17.4 Operation of Serial Interface CSIA0 Serial interface CSIA0 has the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 17.4.1 Operation stop mode Serial communication is not executed in this mode.
Page 391: 3-Wire Serial I/O Mode
CHAPTER 17 SERIAL INTERFACE CSIA0 17.4.2 3-wire serial I/O mode The one-byte data transmission/reception is executed in the mode in which bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is cleared to 0. The 3-wire serial I/O mode is useful for connecting peripheral ICs and display controllers with a clocked serial interface.
Page 392 CHAPTER 17 SERIAL INTERFACE CSIA0 The relationship between the register settings and pins is shown below. Table 17-3. Relationship Between Register Settings and Pins CSIAE0 ATE0 MASTER0 PM143 P143 PM144 P144 PM142 P142 Serial I/O Serial Clock Pin Function Shift Counter SIA0/ SOA0/...
Page 393: 3-Wire Serial I/O Mode Timing
CHAPTER 17 SERIAL INTERFACE CSIA0 (2) 1-byte transmission/reception communication operation (a) 1-byte transmission/reception When bit 7 (CSIAE0) and bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 1, 0, respectively, if communication data is written to serial I/O shift register 0 (SIOA0), the data is output via the SOA0 pin in synchronization with the SCKA0 falling edge, and then input via the SIA0 pin in synchronization with SCKA0 falling edge, and stored in the SIOA0 register in synchronization with the rising edge 1 clock later.
Page 394: Format Of Transmit/Receive Data
CHAPTER 17 SERIAL INTERFACE CSIA0 (b) Data format In the data format, data is changed in synchronization with the SCKA0 falling edge as shown below. The data length is fixed to 8 bits and the data communication direction can be switched by the specification of bit 1 (DIR0) of serial operation mode specification register 0 (CSIMA0).
Page 395: Transfer Bit Order Switching Circuit
CHAPTER 17 SERIAL INTERFACE CSIA0 (c) Switching MSB/LSB as start bit Figure 17-12 shows the configuration of serial I/O shift register 0 (SIOA0) and the internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form. Switching MSB/LSB as the start bit can be specified using bit 1 (DIR0) of serial operation mode specification register 0 (CSIMA0).
Page 396: 3-Wire Serial I/O Mode With Automatic Transmit/Receive Function
CHAPTER 17 SERIAL INTERFACE CSIA0 17.4.3 3-wire serial I/O mode with automatic transmit/receive function Up to 32 bytes of data can be transmitted/received without using software in the mode in which bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is set to 1. After communication is started, only data of the set number of bytes stored in RAM in advance can be transmitted, and only data of the set number of bytes can be received and stored in RAM.
Page 397 Table 17-4. Relationship Between Register Settings and Pins CSIAE0 ATE0 MASTER0 STBE0 BUSYE0 ERRE0 PM143 P143 PM144 P144 PM142 P142 PM145 P145 PM141 P141 Serial I/O Serial Clock Pin Function Shift Register Counter SIA0/ SOA10/ SCKA0/ STB0/ BUSY0/ 0 Operation Operation Control P143 P144...
Page 398 CHAPTER 17 SERIAL INTERFACE CSIA0 (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FA00H of buffer RAM (up to FA1FH at maximum). The transmit data should be in the order from lower address to higher address. <2>...
Page 399: Automatic Transmission/Reception Mode Operation Timings
CHAPTER 17 SERIAL INTERFACE CSIA0 At this time, an interrupt request signal (INTACSI) is generated except when the CSIAE0 bit = 0. If a transfer is terminated in the middle, transfer starting from the remaining data is not possible. Read automatic data transfer address count register 0 (ADTC0) to confirm how much of the data has already been transferred and re-execute transfer by performing (a) and (b) in (2) Automatic transmit/receive data setting.
Page 400: Automatic Transmission/Reception Mode Flowchart
CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-14. Automatic Transmission/Reception Mode Flowchart Start Write transmit data in internal buffer RAM Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the automatic transmission/reception mode Set ATSTA0 to 1 Write transmit data from...
Page 401: (In Automatic Transmission/Reception Mode) (1/2
CHAPTER 17 SERIAL INTERFACE CSIA0 In 6-byte transmission/reception (ATM0 = 0, RXEA0 = 1, TXEA0 = 1) in automatic transmission/reception mode, internal buffer RAM operates as follows. (i) Starting transmission/reception (see Figure 17-15 (a).) When bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1, transmit data 1 (T1) is transferred from the internal buffer RAM to SIOA0.
Page 402 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-15. Internal Buffer RAM Operation in 6-Byte Transmission/Reception (in Automatic Transmission/Reception Mode) (2/2) (b) 4th byte transmission/reception FA1FH FA05H Transmit data 6 (T6) Receive data 4 (R4) SIOA0 Transmit data 5 (T5) ADTP0 Transmit data 4 (T4) Receive data 3 (R3) ADTC0 Receive data 2 (R2)
Page 403: Automatic Transmission Mode Operation Timing
CHAPTER 17 SERIAL INTERFACE CSIA0 (b) Automatic transmission mode In this mode, the specified number of 8-bit unit data is transmitted. Serial communication is started when bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1 while bit 7 (CSIAE0), bit 6 (ATE0), and bit 3 (TXEA0) of serial operation mode specification register 0 (CSIMA0) are set to 1.
Page 404: Automatic Transmission Mode Flowchart
CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-17. Automatic Transmission Mode Flowchart Start Write transmit data in internal buffer RAM Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the automatic transmission mode Set ATSTA0 to 1 Write transmit data from...
Page 405: Internal Buffer Ram Operation In 6-Byte Transmission (In Automatic Transmission Mode)
CHAPTER 17 SERIAL INTERFACE CSIA0 In 6-byte transmission (ATM0 = 0, RXEA0 = 0, TXEA0 = 1, ATE0 = 1) in automatic transmission mode, internal buffer RAM operates as follows. (i) Starting transmission (see Figure 17-18 (a).) When bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1, transmit data 1 (T1) is transferred from the internal buffer RAM to SIOA0.
Page 406 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-18. Internal Buffer RAM Operation in 6-Byte Transmission (in Automatic Transmission Mode) (2/2) (b) 4th byte transmission point FA1FH FA05H Transmit data 6 (T6) SIOA0 Transmit data 5 (T5) ADTP0 Transmit data 4 (T4) Transmit data 3 (T3) ADTC0 Transmit data 2 (T2)
Page 407: Repeat Transmission Mode Operation Timing
CHAPTER 17 SERIAL INTERFACE CSIA0 (c) Repeat transmission mode In this mode, data stored in the internal buffer RAM is transmitted repeatedly. Serial communication is started when bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1 while bit 7 (CSIAE0), bit 6 (ATE0), bit 5 (ATM0), and bit 3 (TXEA0) of serial operation mode specification register 0 (CSIMA0) are set to 1.
Page 408: Repeat Transmission Mode Flowchart
CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-20. Repeat Transmission Mode Flowchart Start Write transmit data in internal buffer RAM Set ADTP0 to the value (point value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the repeat transmission mode Set ATSTA0 to 1 Write transmit data from...
Page 409: Internal Buffer Ram Operation In 6-Byte Transmission (In Repeat Transmission Mode)
CHAPTER 17 SERIAL INTERFACE CSIA0 In 6-byte transmission (ATM0 = 1, RXEA0 = 0, TXEA0 = 1, ATE0 = 1) in repeat transmission mode, internal buffer RAM operates as follows. (i) Starting transmission (see Figure 17-21 (a).) When bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1, transmit data 1 (T1) is transferred from the internal buffer RAM to SIOA0.
Page 410 CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-21. Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) (2/2) (b) Upon completion of transmission of 6 bytes FA1FH FA05H Transmit data 6 (T6) SIOA0 Transmit data 5 (T5) ADTP0 Transmit data 4 (T4) Transmit data 3 (T3) ADTC0 Transmit data 2 (T2)
Page 411: Format Of Csia0 Transmit/Receive Data
CHAPTER 17 SERIAL INTERFACE CSIA0 (d) Data format In the data format, data is changed in synchronization with the SCKA0 falling edge as shown below. The data length is fixed to 8 bits and the data transfer direction can be switched by the specification of bit 1 (DIR0) of serial operation mode specification register 0 (CSIMA0).
Page 412: Automatic Transmission/Reception Suspension And Restart
CHAPTER 17 SERIAL INTERFACE CSIA0 (e) Automatic transmission/reception suspension and restart Automatic transmission/reception can be temporarily suspended by setting bit 1 (ATSTP0) of serial trigger register 0 (CSIT0) to 1. During 8-bit data communication, the transmission/reception is not suspended. It is suspended upon completion of 8-bit data communication.
Page 413: System Configuration When Busy Control Option Is Used
• Bit 4 (BUSYE0) of serial status register 0 (CSIS0) is set to 1. Figure 17-24 shows the system configuration of the master device and slave device when the busy control option is used. Figure 17-24. System Configuration When Busy Control Option Is Used Master device (78K0/KF1) Slave device SCKA0 SCKA SOA0...
Page 414: Operation Timing When Busy Control Option Is Used (When Busylv0 = 1)
CHAPTER 17 SERIAL INTERFACE CSIA0 Figure 17-25. Operation Timing When Busy Control Option Is Used (When BUSYLV0 = 1) SCKA0 SOA0 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY0 Wait...
Page 415: Operation Timing When Busy & Strobe Control Options Are Used (When Busylv0 = 1)
CHAPTER 17 SERIAL INTERFACE CSIA0 (b) Busy & strobe control option Strobe control is a function used to synchronize data transmission/reception between the master and slave devices. The master device outputs the strobe signal from the STB0/P145 pin when 8-bit transmission/reception has been completed.
Page 416: Operation Timing Of Bit Shift Detection Function By Busy Signal (When Busylv0 = 0)
CHAPTER 17 SERIAL INTERFACE CSIA0 (c) Bit shift detection by busy signal During automatic transmission/reception, a bit shift of the serial clock of the slave device may occur because noise is superimposed on the serial clock signal output by the master device. Unless the strobe control option is used at this time, the bit shift affects transmission of the next byte.
Page 417: Automatic Transmit/Receive Interval Time
CHAPTER 17 SERIAL INTERFACE CSIA0 (5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the internal buffer RAM are performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next transmit/receive operation. Since the read/write operations from/to the buffer RAM are performed in parallel with the CPU processing when using the automatic transmit/receive function by the internal clock, the interval depends on the value which is set in automatic data transfer interval specification register 0 (ADTI0) and bits 5 and 4 (STBE0,...
Page 418: Chapter 18 Multiplier/Divider
CHAPTER 18 MULTIPLIER/DIVIDER 18.1 Functions of Multiplier/Divider The multiplier/divider has the following functions. • 16 bits × 16 bits = 32 bits (multiplication) • 32 bits ÷ 16 bits = 32 bits, 16-bit remainder (division) 18.2 Configuration of Multiplier/Divider The multiplier/divider consists of the following hardware. Table 18-1.
Page 419 Figure 18-1. Block Diagram of Multiplier/Divider Internal bus Multiplier/divider control register 0 (DMUC0) Multiplication/division data register B0 Remainder data register 0 Multiplication/division data register A0 DMUSEL0 DMUE (MDB0 (MDB0H+MDB0L) (SDR0 (SDR0H+SDR0L) (MDA0H (MDA0HH + MDA0HL) + MDA0L (MDA0LH + MDA0LL)) Start MDA000 INTDMU...
Page 420 CHAPTER 18 MULTIPLIER/DIVIDER (1) Remainder data register 0 (SDR0) SDR0 is a 16-bit register that stores a remainder. This register stores 0 in the multiplication mode and the remainder of an operation result in the division mode. This register can be read by an 8-bit or 16-bit memory manipulation instruction. RESET input clears this register to 0000H.
Page 421 CHAPTER 18 MULTIPLIER/DIVIDER (2) Multiplication/division data register A0 (MDA0H, MDA0L) MDA0 is a 32-bit register that sets a 16-bit multiplier A in the multiplication mode and a 32-bit dividend in the division mode, and stores the 32-bit result of the operation (higher 16 bits: MDA0H, lower 16 bits: MDA0L). Figure 18-3.
Page 422 CHAPTER 18 MULTIPLIER/DIVIDER The functions of MDA0 when an operation is executed are shown in the table below. Table 18-2. Functions of MDA0 During Operation Execution DMUSEL0 Operation Mode Setting Operation Result Division mode Dividend Division result (quotient) Multiplication mode Higher 16 bits: 0, Lower 16 Multiplication result bits: Multiplier A...
Page 423: Register Controlling Multiplier/Divider
CHAPTER 18 MULTIPLIER/DIVIDER 18.3 Register Controlling Multiplier/Divider The multiplier/divider is controlled by multiplier/divider control register 0 (DMUC0). (1) Multiplier/divider control register 0 (DMUC0) DMUC0 is an 8-bit register that controls the operation of the multiplier/divider. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 424: Operations Of Multiplier/Divider
CHAPTER 18 MULTIPLIER/DIVIDER 18.4 Operations of Multiplier/Divider 18.4.1 Multiplication operation • Initial setting 1. Set operation data to multiplication/division data register A0L (MDA0L) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 1. Operation will start.
Page 425 Figure 18-6. Timing Chart of Multiplication Operation (00DAH × 0093H) Operation clock DMUE DMUSEL0 Internal clock Counter XXXX 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SDR0 0000 0049 0024 005B 0077 003B 0067...
Page 426: Division Operation
CHAPTER 18 MULTIPLIER/DIVIDER 18.4.2 Division operation • Initial setting 1. Set operation data to multiplication/division data register A0 (MDA0L and MDA0H) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 0 and 1, respectively.
Page 427 Figure 18-7. Timing Chart of Division Operation (DCBA2586H ÷ 0018H) Operation clock DMUE DMUSEL0 “0” Internal clock 1B 1C 1D 1E Counter XXXX 0000 0001 0003 0006 000D 0003 0007 000E 0004 000B 0016 0014 0010 0008 0011 000B 0016 SDR0 B974 72E8...
Page 428: Chapter 19 Interrupt Functions
CHAPTER 19 INTERRUPT FUNCTIONS 19.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L, PR1H). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated.
Page 429 CHAPTER 19 INTERRUPT FUNCTIONS Table 19-1. Interrupt Source List (1/2) Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority External Table Configuration Name Trigger Note 2 Address Type Note 3 Maskable INTLVI Low-voltage detection Internal 0004H INTP0 Pin input edge detection External 0006H INTP1...
Page 430 CHAPTER 19 INTERRUPT FUNCTIONS Table 19-1. Interrupt Source List (2/2) Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority External Table Configuration Name Trigger Note 2 Address Type Maskable INTKR Key interrupt detection External 002CH INTWT Watch timer overflow Internal 002EH INTP6...
Page 431 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus Vector table Priority controller Interrupt address generator request Standby release signal (B) External maskable interrupt (INTP0 to INTP7) Internal bus External interrupt edge enable register (EGP, EGN) Vector table...
Page 432: Registers Controlling Interrupt Functions
CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt (INTKR) Internal bus Interrupt Vector table Priority controller request address generator interrupt detector 1 when KRMn = 1 (n = 0 to 7) Standby release signal (D) Software interrupt Internal bus Interrupt...
Page 433 CHAPTER 19 INTERRUPT FUNCTIONS Table 19-2. Flags Corresponding to Interrupt Request Sources Interrupt Source Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Register Register Register INTLVI LVIIF IF0L LVIMK MK0L LVIPR PR0L INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2...
Page 434 CHAPTER 19 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon RESET input.
Page 435 CHAPTER 19 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set by a 16-bit memory manipulation instruction.
Page 436 CHAPTER 19 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory manipulation instruction.
Page 437 CHAPTER 19 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP7. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H.
Page 438 CHAPTER 19 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW.
Page 439: Interrupt Servicing Operations
CHAPTER 19 INTERRUPT FUNCTIONS 19.4 Interrupt Servicing Operations 19.4.1 Maskable interrupt request acknowledgement A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
Page 440 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-7. Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority Any high-priority interrupt request among those interrupt request among simultaneously generated with ××PR = 0?
Page 441: Software Interrupt Request Acknowledgment
CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction jump to interrupt program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/f : CPU clock) Figure 19-9.
Page 442: Multiple Interrupt Servicing
CHAPTER 19 INTERRUPT FUNCTIONS 19.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1). Also, when an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0).
Page 443 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0) RETI...
Page 444 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0) INTxx RETI (PR = 0) IE = 1 IE = 0...
Page 445: Interrupt Request Hold
CHAPTER 19 INTERRUPT FUNCTIONS 19.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
Page 446: Chapter 20 Key Interrupt Function
CHAPTER 20 KEY INTERRUPT FUNCTION 20.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling edge to the key interrupt input pins (KR0 to KR7). Table 20-1. Assignment of Key Interrupt Detection Pins Flag Description KRM0...
Page 447: Register Controlling Key Interrupt
CHAPTER 20 KEY INTERRUPT FUNCTION 20.3 Register Controlling Key Interrupt (1) Key return mode register (KRM) This register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals, respectively. This register is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 448: Chapter 21 Standby Function
CHAPTER 21 STANDBY FUNCTION 21.1 Standby Function and Configuration 21.1.1 Standby function Table 21-1. Relationship Between Operation Clocks in Each Operation Status Status X1 Oscillator Ring-OSC Oscillator Subsystem CPU Clock Prescaler Clock Clock After Supplied to Peripherals Oscillator Release MSTOP = 0 MSTOP = 1 Note 1 Note 2...
Page 449 CHAPTER 21 STANDBY FUNCTION (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the X1 oscillator stops, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released, select the HALT mode if it is necessary to start processing immediately upon interrupt request generation.
Page 450: Registers Controlling Standby Function
CHAPTER 21 STANDBY FUNCTION 21.1.2 Registers controlling standby function The standby function is controlled by the following two registers. • Oscillation stabilization time counter status register (OSTC) • Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, see CHAPTER 6 CLOCK GENERATOR. (1) Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 input clock oscillation stabilization time counter.
Page 451 CHAPTER 21 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released when the X1 input clock is selected as the CPU clock.
Page 452: Standby Function Operation
CHAPTER 21 STANDBY FUNCTION 21.2 Standby Function Operation 21.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the X1 input clock, Ring-OSC clock, or subsystem clock. The operating statuses in the HALT mode are shown below.
Page 453 CHAPTER 21 STANDBY FUNCTION Table 21-2. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock When X1 Input Clock Oscillation Continues When X1 Input Clock Oscillation Stopped When Ring-OSC When Ring-OSC When Ring-OSC When Ring-OSC...
Page 454 CHAPTER 21 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed.
Page 455 CHAPTER 21 STANDBY FUNCTION (b) Release by RESET input When the RESET signal is input, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 21-4.
Page 456 CHAPTER 21 STANDBY FUNCTION Figure 21-4. HALT Mode Release by RESET Input (2/2) (3) When subsystem clock is used as CPU clock HALT instruction RESET signal Operating Reset Operation Status of CPU mode period stopped HALT mode Operating mode (17/f (Ring-OSC clock) Subsystem clock...
Page 457: Stop Mode
CHAPTER 21 STANDBY FUNCTION 21.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set when the CPU clock before the setting was the X1 input clock or Ring-OSC clock. Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set.
Page 458 CHAPTER 21 STANDBY FUNCTION (2) STOP mode release Figure 21-5. Operation Timing When STOP Mode Is Released STOP mode release STOP mode X1 input clock Ring-OSC clock X1 input clock is selected as CPU clock HALT status X1 input clock when STOP instruction (oscillation stabilization time set by OSTS) is executed...
Page 459 CHAPTER 21 STANDBY FUNCTION (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 21-6.
Page 460 CHAPTER 21 STANDBY FUNCTION (b) Release by RESET input When the RESET signal is input, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 21-7. STOP Mode Release by RESET Input (1) When X1 input clock is used as CPU clock STOP instruction...
Page 461: Chapter 22 Reset Function
CHAPTER 22 RESET FUNCTION The following five operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by clock monitor X1 clock oscillation stop detection (4) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (5) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences.
Page 462 Figure 22-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF CLMRF LVIRF Watchdog timer reset signal Clear Clear Clear Clock monitor reset signal Reset signal RESET Reset signal to LVIM/LVIS register Power-on-clear circuit reset signal Reset signal Low-voltage detector reset signal Caution An LVI circuit internal reset does not reset the LVI circuit.
Page 463 CHAPTER 22 RESET FUNCTION Figure 22-2. Timing of Reset by RESET Input Ring-OSC clock X1 input clock Operation stop Normal operation Reset period CPU clock Normal operation (17/f (Reset processing, Ring-OSC clock) (Oscillation stop) RESET Internal reset signal Delay Delay Note Hi-Z Port pin...
Page 464 CHAPTER 22 RESET FUNCTION Figure 22-4. Timing of Reset in STOP Mode by RESET Input Ring-OSC clock X1 input clock STOP instruction execution Operation stop Normal Normal operation Reset period Stop status CPU clock (17/f operation (Reset processing, Ring-OSC clock) (Oscillation stop) (Oscillation stop) RESET...
Page 465 CHAPTER 22 RESET FUNCTION Table 22-1. Hardware Statuses After Reset Acknowledgment (1/3) Hardware Status After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined...
Page 466 CHAPTER 22 RESET FUNCTION Table 22-1. Hardware Statuses After Reset Acknowledgment (2/3) Hardware Status After Reset Acknowledgment Watchdog timer Mode register (WDTM) Enable register (WDTE) A/D converter Conversion result register (ADCR) Undefined Mode register (ADM) Analog input channel specification register (ADS) Power-fail comparison mode register (PFM) Power-fail comparison threshold register (PFT) Serial interface UART0...
Page 467 CHAPTER 22 RESET FUNCTION Table 22-1. Hardware Statuses After Reset Acknowledgment (3/3) Hardware Status After Reset Acknowledgment Note Reset function Reset control flag register (RESF) Note Low-voltage detector Low-voltage detection register (LVIM) Note Low-voltage detection level selection register (LVIS) Interrupt Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H) Mask flag registers 0L, 0H, 1L (MK0L, MK0H, MK1L) Mask flag register 1H (MK1H)
Page 468: Register For Confirming Reset Source
CHAPTER 22 RESET FUNCTION 22.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/KF1. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction.
Page 469: Chapter 23 Clock Monitor
CHAPTER 23 CLOCK MONITOR 23.1 Functions of Clock Monitor The clock monitor samples the X1 input clock using the on-chip Ring-OSC, and generates an internal reset signal when the X1 input clock is stopped. When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set to 1.
Page 470: Registers Controlling Clock Monitor
CHAPTER 23 CLOCK MONITOR 23.3 Registers Controlling Clock Monitor Clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) This register sets the operation mode of the clock monitor. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 471: Operation Of Clock Monitor
CHAPTER 23 CLOCK MONITOR 23.4 Operation of Clock Monitor This section explains the functions of the clock monitor. The monitor start and stop conditions are as follows. <Monitor start condition> When bit 0 (CLME) of the clock monitor mode register (CLM) is set to operation enabled (1). <Monitor stop condition>...
Page 472 CHAPTER 23 CLOCK MONITOR Figure 23-3. Timing of Clock Monitor (1/4) (1) When internal reset is executed by oscillation stop of X1 input clock 4 clocks of Ring-OSC clock X1 input clock Ring-OSC clock Internal reset signal CLME CLMRF (2) Clock monitor status after RESET input (CLME = 1 is set after RESET input and during X1 input clock oscillation stabilization time) Clock supply Normal...
Page 473 CHAPTER 23 CLOCK MONITOR Figure 23-3. Timing of Clock Monitor (2/4) (3) Clock monitor status after RESET input (CLME = 1 is set after RESET input and at the end of X1 input clock oscillation stabilization time) Normal Clock supply operation CPU operation Reset...
Page 474 CHAPTER 23 CLOCK MONITOR Figure 23-3. Timing of Clock Monitor (3/4) (5) Clock monitor status after STOP mode is released (CLME = 1 is set when CPU clock operates on Ring-OSC clock and before entering STOP mode) Clock supply Normal stopped Normal operation operation...
Page 475 CHAPTER 23 CLOCK MONITOR Figure 23-3. Timing of Clock Monitor (4/4) (7) Clock monitor status after Ring-OSC clock oscillation is stopped by software Normal operation (X1 input clock or subsystem clock) CPU operation X1 input clock Ring-OSC clock Oscillation stopped Note RSTOP CLME...
Page 476: Chapter 24 Power-On-Clear Circuit
CHAPTER 24 POWER-ON-CLEAR CIRCUIT 24.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. • Generates internal reset signal at power on. • Compares supply voltage (V ) and detection voltage (V ), and generates internal reset signal when V <...
Page 477: Configuration Of Power-On-Clear Circuit
CHAPTER 24 POWER-ON-CLEAR CIRCUIT 24.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 24-1. Figure 24-1. Block Diagram of Power-on-Clear Circuit Mask option Internal reset signal − Detection voltage source 24.3 Operation of Power-on-Clear Circuit In the power-on-clear circuit, the supply voltage (V ) and detection voltage (V ) are compared, and when V...
Page 478: Cautions For Power-On-Clear Circuit
CHAPTER 24 POWER-ON-CLEAR CIRCUIT 24.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POC detection voltage (V ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
Page 479 CHAPTER 24 POWER-ON-CLEAR CIRCUIT Figure 24-3. Example of Software Processing After Release of Reset (2/2) • Checking reset cause Check reset cause WDTRF of RESF register = 1? Reset processing by watchdog timer CLMRF of RESF register = 1? Reset processing by clock monitor LVIRF of RESF register = 1?
Page 480: Chapter 25 Low-Voltage Detector
CHAPTER 25 LOW-VOLTAGE DETECTOR 25.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has following functions. • Compares supply voltage (V ) and detection voltage (V ), and generates an internal interrupt signal or internal reset signal when V < V •...
Page 481: Registers Controlling Low-Voltage Detector
CHAPTER 25 LOW-VOLTAGE DETECTOR 25.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. • Low-voltage detection register (LVIM) • Low-voltage detection level selection register (LVIS) (1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 482: Format Of Low-Voltage Detection Register (Lvim)
CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-2. Format of Low-Voltage Detection Register (LVIM) Note 1 Address: FFBEH After reset: 00H <7> <4> <1> <0> Symbol LVION LVIE LVIMD LVIF LVIM Notes 2, 3 LVION Enables low-voltage detection operation Disables operation Enables operation Notes 2, 4, 5 LVIE Specifies reference voltage generator...
Page 483: Format Of Low-Voltage Detection Level Selection Register (Lvis)
CHAPTER 25 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. RESET input clears LVIS to 00H. Figure 25-3. Format of Low-Voltage Detection Level Selection Register (LVIS) Address: FFBFH After reset: 00H Symbol...
Page 484: Operation Of Low-Voltage Detector
CHAPTER 25 LOW-VOLTAGE DETECTOR 25.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. • Used as reset Compares the supply voltage (V ) and detection voltage (V ), and generates an internal reset signal when <...
Page 485: Timing Of Low-Voltage Detector Internal Reset Signal Generation
CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-4. Timing of Low-Voltage Detector Internal Reset Signal Generation Supply voltage (V LVI detection voltage POC detection voltage 2.7 V Time <2> LVIMK flag (set by software) Note 1 <1> LVIE flag Not cleared Not cleared (set by software) <3>...
Page 486 CHAPTER 25 LOW-VOLTAGE DETECTOR (2) When used as interrupt • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection register (LVIS).
Page 487: Timing Of Low-Voltage Detector Interrupt Signal Generation
CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-5. Timing of Low-Voltage Detector Interrupt Signal Generation Supply voltage (V LVI detection voltage POC detection voltage 2.7 V Time <2> LVIMK flag (set by software) Note 1 <1> <9> Cleared by software LVIE flag (set by software) <3>...
Page 488: Cautions For Low-Voltage Detector
CHAPTER 25 LOW-VOLTAGE DETECTOR 25.5 Cautions for Low-Voltage Detector In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVI detection voltage ), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status.
Page 489: Example Of Software Processing After Release Of Reset
CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-6. Example of Software Processing After Release of Reset (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage ; The Ring-OSC clock is set as the CPU clock when the reset signal is generated Reset Checking cause The cause of reset (power-on-clear, WDT, LVI, or clock monitor)
Page 490 CHAPTER 25 LOW-VOLTAGE DETECTOR Figure 25-6. Example of Software Processing After Release of Reset (2/2) • Checking reset cause Check reset cause WDTRF of RESF register = 1? Reset processing by watchdog timer CLMRF of RESF register = 1? Reset processing by clock monitor LVIRF of RESF register = 1?
Page 491 CHAPTER 25 LOW-VOLTAGE DETECTOR (2) When used as interrupt Check that “supply voltage (V ) > detection voltage (V )” in the servicing routine of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 0 (LVIIF) of interrupt request flag register 0L (IF0L) to 0 and enable interrupts (EI).
Page 492: Chapter 26 Regulator
CHAPTER 26 REGULATOR 26.1 Outline of Regulator The 78K0/KF1 includes a circuit to realize constant-voltage operation inside the device. To stabilize the regulator µ output voltage, connect the REGC pin to V via a capacitor (1 F: recommended). The output voltage of the regulator is 3.5 V (TYP.).
Page 493: Regc Pin Connection
CHAPTER 26 REGULATOR Figure 26-2. REGC Pin Connection (a) When REGC = V Input voltage = 2.7 to 5.5 V Voltage supply to oscillator/internal logic = 2.7 to 5.5 V REGC (b) When connecting REGC pin to V via a capacitor Input voltage = 4.0 to 5.5 V Voltage supply to oscillator/internal logic = 3.5 V REGC...
Page 494: Chapter 27 Mask Options
CHAPTER 27 MASK OPTIONS Mask ROM versions are provided with the following mask options. Power-on-clear (POC) circuit • POC cannot be used • POC used (detection voltage: V = 2.85 V ±0.15 V) Note • POC used (detection voltage: V = 3.5 V ±0.2 V) Ring-OSC •...
Page 495: Chapter 28 Pd78F0148
µ CHAPTER 28 PD78F0148 µ PD78F0148 is provided as the flash memory version of the 78K0/KF1. µ µ PD78F0148 replaces the internal mask ROM of the PD780148 with flash memory to which a program can be written, erased, and overwritten while mounted on the board. Table 28-1 lists the differences between the µ...
Page 496: Internal Memory Size Switching Register
µ CHAPTER 28 PD78F0148 28.1 Internal Memory Size Switching Register µ PD78F0148 allows users to select the internal memory capacity using the internal memory size switching register (IMS) so that the same memory map as that of the mask ROM versions with a different internal memory capacity can be achieved.
Page 497: Internal Expansion Ram Size Switching Register
µ CHAPTER 28 PD78F0148 28.2 Internal Expansion RAM Size Switching Register This register is used to set the internal expansion RAM capacity via software. This register is set by an 8-bit memory manipulation instruction. RESET input sets IXS to 0CH. Caution Be sure to set the value of the relevant mask ROM version at initialization.
Page 498: Writing With Flash Programmer
µ CHAPTER 28 PD78F0148 28.3 Writing with Flash Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) On-board programming µ The contents of the flash memory can be rewritten after the PD78F0148 has been mounted on the target system.
Page 499 µ CHAPTER 28 PD78F0148 µ Table 28-4. Wiring Between PD78F0148 and Dedicated Flash Programmer (2/2) (2) UART (UART0, UART6) Pin Configuration of Dedicated Flash Programmer With UART0 With UART0 + HS With UART6 Signal Name Pin Function Pin Name Pin No. Pin Name Pin No.
Page 500: Example Of Wiring Adapter For Flash Memory Writing In 3-Wire Serial I/O (Csi10) Mode
µ CHAPTER 28 PD78F0148 Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 28-3. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode Note 1 (2.7 to 5.5 V) LVDD (VDD2) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Note 2...
Page 501: Example Of Wiring Adapter For Flash Memory Writing In 3-Wire Serial I/O (Csi10 + Hs) Mode
µ CHAPTER 28 PD78F0148 Figure 28-4. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10 + HS) Mode Note 1 (2.7 to 5.5 V) LVDD (VDD2) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Note 2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 /RESET V...
Page 502: Example Of Wiring Adapter For Flash Memory Writing In Uart (Uart0) Mode
µ CHAPTER 28 PD78F0148 Figure 28-5. Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode Note 1 (2.7 to 5.5 V) LVDD (VDD2) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Note 2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 /RESET V...
Page 503: Example Of Wiring Adapter For Flash Memory Writing In Uart (Uart0 + Hs) Mode
µ CHAPTER 28 PD78F0148 Figure 28-6. Example of Wiring Adapter for Flash Memory Writing in UART (UART0 + HS) Mode Note 1 (2.7 to 5.5 V) LVDD (VDD2) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Note 2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 /RESET V...
Page 504: Example Of Wiring Adapter For Flash Memory Writing In Uart (Uart6) Mode
µ CHAPTER 28 PD78F0148 Figure 28-7. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode Note 1 (2.7 to 5.5 V) LVDD (VDD2) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Note 2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 /RESET V...
Page 505: Programming Environment
µ CHAPTER 28 PD78F0148 28.4 Programming Environment µ The environment required for writing a program to the flash memory of the PD78F0148 is illustrated below. Figure 28-8. Environment for Writing Program to Flash Memory RS-232C Axxxx Bxxxxx Cxxxxxx STATVE PG-FP4 Note RESET µ...
Page 506: Communication With Dedicated Flash Programmer (Csi10 + Hs)
µ CHAPTER 28 PD78F0148 (2) CSI communication mode supporting handshake Transfer rate: 200 kHz to 2 MHz Figure 28-10. Communication with Dedicated Flash Programmer (CSI10 + HS) Axxxx Bxxxxx /RESET RESET Cxxxxxx STATVE PG-FP4 SI/RxD SO10 µ SO/TxD SI10 PD78F0148 Dedicated flash programmer SCK10...
Page 507: Communication With Dedicated Flash Programmer (Uart0 + Hs)
µ CHAPTER 28 PD78F0148 (4) UART communication mode supporting handshake Transfer rate: 4800 to 38400 bps Figure 28-12. Communication with Dedicated Flash Programmer (UART0 + HS) Axxxx Bxxxxx /RESET RESET Cxxxxxx STATVE PG-FP4 SI/RxD TxD0 µ Dedicated flash SO/TxD RxD0 PD78F0148 programmer (5) UART6...
Page 508 µ CHAPTER 28 PD78F0148 If Flashpro III/Flashpro IV is used as the dedicated flash programmer, Flashpro III/Flashpro IV generates the µ following signal for the PD78F0148. For details, refer to the Flashpro III/Flashpro IV Manual. Table 28-5. Pin Connection µ PD78F0148 Flashpro III/Flashpro IV Connection...
Page 509: Processing Of Pins On Board
µ CHAPTER 28 PD78F0148 28.6 Processing of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.
Page 510: Serial Interface Pins
µ CHAPTER 28 PD78F0148 28.6.2 Serial interface pins The pins used by each serial interface are listed below. Table 28-6. Pins Used by Each Serial Interface Serial Interface Pins Used CSI10 SO10, SI10, SCK10 CSI10 + HS SO10, SI10, SCK10, HS/P15 UART0 TxD0, RxD0 UART0 + HS...
Page 511: Malfunction Of Other Device
µ CHAPTER 28 PD78F0148 (2) Malfunction of other device If the dedicated flash programmer (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input), a signal may be output to the other device, causing the device to malfunction.
Page 512: Reset Pin
µ CHAPTER 28 PD78F0148 28.6.3 RESET pin If the reset signal of the dedicated flash programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator.
Page 513: Programming Method
µ CHAPTER 28 PD78F0148 28.7 Programming Method 28.7.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 28-18. Flash Memory Manipulation Procedure Start Flash memory programming pulse supply mode is set Selecting communication mode Manipulate flash memory End? User’s Manual U15947EJ2V0UD...
Page 514: Flash Memory Programming Mode
µ CHAPTER 28 PD78F0148 28.7.2 Flash memory programming mode µ To rewrite the contents of the flash memory by using the dedicated flash programmer, set the PD78F0148 in the flash memory programming mode. To set the mode, set the V pin and clear the reset signal.
Page 515: Communication Commands
µ CHAPTER 28 PD78F0148 28.7.4 Communication commands µ PD78F0148 communicates with the dedicated flash programmer by using commands. The signals sent from µ µ the flash programmer to the PD78F0148 are called commands, and the commands sent from the PD78F0148 to the dedicated flash programmer are called response commands.
Page 516: Chapter 29 Instruction Set
CHAPTER 29 INSTRUCTION SET This chapter lists each instruction set of the 78K0/KF1 in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E). 29.1 Conventions Used in Operation List 29.1.1 Operand identifiers and specification methods...
Page 517: Description Of Operation Column
CHAPTER 29 INSTRUCTION SET 29.1.2 Description of operation column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 518: Operation List
CHAPTER 29 INSTRUCTION SET 29.2 Operation List Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − r ← byte 8-bit data r, #byte (saddr) ← byte transfer saddr, #byte − sfr ← byte sfr, #byte −...
Page 519 CHAPTER 29 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − rp ← word 16-bit data MOVW rp, #word (saddrp) ← word transfer saddrp, #word − sfrp ← word sfrp, #word AX ←...
Page 520 CHAPTER 29 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A, CY ← A − byte × × × 8-bit A, #byte (saddr), CY ← (saddr) − byte × × ×...
Page 521 CHAPTER 29 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A ← A ∨ byte × 8-bit A, #byte (saddr) ← (saddr) ∨ byte × operation saddr, #byte − A ← A ∨ r ×...
Page 522 CHAPTER 29 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − AX, CY ← AX + word × × × 16-bit ADDW AX, #word − AX, CY ← AX − word ×...
Page 523 CHAPTER 29 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 CY ← CY ∧ (saddr.bit) × AND1 CY, saddr.bit − CY ← CY ∧ sfr.bit × manipulate CY, sfr.bit − CY ← CY ∧ A.bit ×...
Page 524 CHAPTER 29 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) Call/return CALL !addr16 PC ← addr16, SP ← SP − 2 −...
Page 525 CHAPTER 29 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1 Conditional saddr.bit, $addr16 − PC ← PC + 4 + jdisp8 if sfr.bit = 1 branch sfr.bit, $addr16 −...
Page 526: Instructions Listed By Addressing Type
CHAPTER 29 INSTRUCTION SET 29.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Note Second Operand #byte saddr !addr16 [DE]...
Page 527 CHAPTER 29 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note Second Operand #word sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp MOVW...
Page 528 CHAPTER 29 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand CALL Basic instruction CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP User’s Manual U15947EJ2V0UD...
Page 529: Chapter 30 Electrical Specifications
CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) µ Target products: PD780143, 780144, 780146, 780148, 78F0148, 780143(A), 780144(A), 780146(A), 780148(A), 78F0148(A) Absolute Maximum Ratings (T = 25°C) (1/2) Parameter Symbol Conditions Ratings Unit −0.3 to +6.5 Supply voltage −0.3 to +6.5 −0.3 to +6.5 REGC −0.3 to +0.3...
Page 530 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit Output current, low Per pin P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P60 to P63...
Page 531 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) X1 Oscillator Characteristics = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) Resonator Recommended Circuit Parameter Conditions MIN.
Page 532 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) Ring-OSC Oscillator Characteristics = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) Resonator Parameter Conditions MIN.
Page 533 The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KF1 so that the internal operation conditions are within the specifications of the DC and AC characteristics.
Page 534 The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KF1 so that the internal operation conditions are within the specifications of the DC and AC characteristics.
Page 535 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) DC Characteristics (1/4) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 536 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) DC Characteristics (2/4) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 537 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) µ DC Characteristics (3/4): PD78F0148, 78F0148(A) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions...
Page 538 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) µ DC Characteristics (4/4): PD780143, 780144, 780146, 780148, 780143(A), 780144(A), 780146(A), 780148(A) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V)
Page 539 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) AC Characteristics (1) Basic operation = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions...
Page 540 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) vs. V (X1 Input Clock Operation) µ (a) When REGC pin is connected to V via capacitor (1 F: recommended) 20.0 16.0 10.0 Guaranteed operation range 0.238 Supply voltage V (b) When REGC pin is connected directly to V 20.0 16.0 10.0...
Page 541 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (2) Read/write operation = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) (1/2) Parameter Symbol Conditions MIN.
Page 542 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (2) Read/write operation = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) (2/2) Parameter Symbol Conditions MIN.
Page 543 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (3) Serial interface = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) (a) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions...
Page 544 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (e) 3-wire serial I/O mode with automatic transmit/receive function (SCKA0... internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.0 V ≤ V ≤ 5.5 V SCKA0 cycle time KCY3 2.7 V ≤...
Page 545 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8V 0.8V Test points 0.2V 0.2V Clock Timing (MIN.) X1 input (MAX.) (MIN.) XT1 input (MAX.) TI Timing TIL0 TIH0 Note Note TI00, TI010, TI001 , TI011 TIL5 TIH5...
Page 546 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) RESET Input Timing RESET Read/Write Operation External fetch (no wait): A8 to A15 Higher 8-bit address ADD1 Hi-Z AD0 to AD7 Instruction code Lower 8-bit address RDAD RDD1 RDADH ASTH RDAST ASTB ASTRD RDL1...
Page 547 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) External data access (no wait): A8 to A15 Higher 8-bit address ADD2 Hi-Z Hi-Z AD0 to AD7 Lower 8-bit address Read data Write data RDAD RDD2 ASTH ASTB RDWD ASTRD RDL2 WRADH WRWD ASTWR...
Page 548 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) Serial Transfer Timing 3-wire serial I/O mode: KCYm SCK1n SIKm KSIm SI1n Input data KSOm SO1n Output data Remark m = 1, 2 µ n = 0: PD780143, 780144, 780143(A), 780144(A) µ...
Page 549 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) 3-wire serial I/O mode with automatic transmit/receive function: SOA0 SIA0 KSI3, 4 SIK3, 4 KH3, 4 KSO3, 4 SCKA0 KL3, 4 KCY3, 4 STB0 3-wire serial I/O mode with automatic transmit/receive function (busy processing): Note Note Note...
Page 550 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) A/D Converter Characteristics = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 551 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) = −40 to +85°C) LVI Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage LVI0 LVI1 LVI2 LVI3 LVI4 3.15 3.45 LVI5 2.95 3.25 LVI6 Note 1 Response time Minimum pulse width Reference voltage stabilization wait LWAIT0...
Page 552 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) µ Flash Memory Programming Characteristics: PD78F0148, 78F0148(A) = +10 to +60°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = EV = EV = AV = 0 V) (1) Write erase characteristics Parameter Symbol...
Page 553 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (2) Serial write operation characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit µ ↑ to V ↑ Set time from V µ ↑ to RESET↑ t Release time from V pulse input start time from RESET↑...
Page 554: Chapter 31 Electrical Specifications ((A1) Grade Products)
CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) µ Target products: PD780143(A1), 780144(A1), 780146(A1), 780148(A1), 78F0148(A1) Cautions 1. Be sure to connect the REGC pin of (A1) grade products directly to V 2. The external bus interface function cannot be used with (A1) grade products. Absolute Maximum Ratings (T = 25°C) (1/2) Parameter...
Page 555 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit Output current, low Per pin P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P60 to P63 Total of...
Page 556 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) X1 Oscillator Characteristics = −40 to +110°C , 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V Note 1 = EV = EV = AV = 0 V) Resonator Recommended Circuit Parameter Conditions...
Page 557 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Ring-OSC Oscillator Characteristics = −40 to +110°C , 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V Note = EV = EV = AV = 0 V) Resonator Parameter Conditions MIN.
Page 558 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) µ DC Characteristics (1/6): PD78F0148(A1) = −40 to +105°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 559 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) µ DC Characteristics (2/6): PD78F0148(A1) = −40 to +105°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 560 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) µ DC Characteristics (3/6): PD78F0148(A1) = −40 to +105°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 561 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) µ DC Characteristics (4/6): PD780143(A1), 780144(A1), 780146(A1), and 780148(A1) = −40 to +110°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions...
Page 562 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) µ DC Characteristics (5/6): PD780143(A1), 780144(A1), 780146(A1), and 780148(A1) = −40 to +110°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions...
Page 563 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) µ DC Characteristics (6/6): PD780143(A1), 780144(A1), 780146(A1), and 780148(A1) = −40 to +110°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions...
Page 564 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) AC Characteristics (1) Basic operation = −40 to +110°C , 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V Note 1 = EV = EV = AV = 0 V) Parameter Symbol Conditions...
Page 565 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) vs. V (X1 Input Clock Operation) 20.0 16.0 10.0 Guaranteed operation range 0.238 Supply voltage V User’s Manual U15947EJ2V0UD...
Page 566 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (2) Serial interface = −40 to +110°C , 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V Note = EV = EV = AV = 0 V) µ = −40 to +110°C: Note T PD780143(A1), 780144(A1), 780146(A1), 780148(A1) = −40 to +105°C:...
Page 567 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (e) 3-wire serial I/O mode with automatic transmit/receive function (SCKA0... internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.5 V ≤ V ≤ 5.5 V SCKA0 cycle time KCY3 3.3 V ≤ V <...
Page 568 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8V 0.8V Test points 0.2V 0.2V Clock Timing (MIN.) X1 input (MAX.) (MIN.) XT1 input (MAX.) TI Timing TIL0 TIH0 Note Note TI00, TI010, TI001 , TI011 TIL5 TIH5 TI50, TI51...
Page 569 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) RESET Input Timing RESET Serial Transfer Timing 3-wire serial I/O mode: KCYm SCK1n SIKm KSIm SI1n Input data KSOm SO1n Output data Remark m = 1, 2 µ n = 0: PD780143(A1), 780144(A1) µ...
Page 570 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) 3-wire serial I/O mode with automatic transmit/receive function: SOA0 SIA0 KSI3, 4 SIK3, 4 KH3, 4 KSO3, 4 SCKA0 KL3, 4 KCY3, 4 STB0 3-wire serial I/O mode with automatic transmit/receive function (busy processing): Note Note Note...
Page 571 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) A/D Converter Characteristics = −40 to +110°C , 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V Note 1 = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 572 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) = −40 to +110°C Note 1 LVI Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage 4.52 LVI0 4.32 LVI1 4.12 LVI2 3.92 LVI3 3.72 LVI4 Note 2 Response time Minimum pulse width Reference voltage stabilization wait LWAIT0...
Page 573 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) µ Flash Memory Programming Characteristics: PD78F0148(A1) = +10 to +60°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) (1) Write erase characteristics Parameter Symbol Conditions...
Page 574 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (2) Serial write operation characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit µ ↑ to V ↑ Set time from V µ ↑ to RESET↑ t Release time from V pulse input start time from RESET↑...
Page 575: Chapter 32 Electrical Specifications ((A2) Grade Products)
CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) µ Target products: PD780143(A2), 780144(A2), 780146(A2), 780148(A2) Cautions 1. Be sure to connect the REGC pin of (A2) grade products directly to V 2. The external bus interface function cannot be used with (A2) grade products. Absolute Maximum Ratings (T = 25°C) (1/2) Parameter...
Page 576 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit Output current, low Per pin P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 P60 to P63 Total of...
Page 577 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) X1 Oscillator Characteristics = −40 to +125°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Resonator Recommended Circuit Parameter Conditions MIN.
Page 578 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Ring-OSC Oscillator Characteristics = −40 to +125°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Resonator Parameter Conditions MIN. TYP.
Page 579 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (1/3) = −40 to +125°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP.
Page 580 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (2/3) = −40 to +125°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP.
Page 581 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (3/3) = −40 to +125°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply X1 crystal = 8.38 MHz...
Page 582 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) AC Characteristics (1) Basic operation = −40 to +125°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 583 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) vs. V (X1 Input Clock Operation) 20.0 16.0 10.0 Guaranteed operation range 0.238 Supply voltage V User’s Manual U15947EJ2V0UD...
Page 584 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (2) Serial interface = −40 to +125°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) (a) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions...
Page 585 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (e) 3-wire serial I/O mode with automatic transmit/receive function (SCKA0... internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKA0 cycle time 1200 KCY3 /2 − 100 SCKA0 high-/low-level width KCY3 SIA0 setup time (to SCKA0↑) SIK3 SIA0 hold time (from SCKA0↑) KSI3...
Page 586 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8V 0.8V Test points 0.2V 0.2V Clock Timing (MIN.) X1 input (MAX.) (MIN.) XT1 input (MAX.) TI Timing TIL0 TIH0 Note Note TI00, TI010, TI001 , TI011 TIL5 TIH5 TI50, TI51...
Page 587 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) RESET Input Timing RESET Serial Transfer Timing 3-wire serial I/O mode: KCYm SCK1n SIKm KSIm SI1n Input data KSOm SO1n Output data Remark m = 1, 2 µ n = 0: PD780143(A2), 780144(A2) µ...
Page 588 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) 3-wire serial I/O mode with automatic transmit/receive function: SOA0 SIA0 KSI3, 4 SIK3, 4 KH3, 4 KSO3, 4 SCKA0 KL3, 4 KCY3, 4 STB0 3-wire serial I/O mode with automatic transmit/receive function (busy processing): Note Note Note...
Page 589 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) A/D Converter Characteristics = −40 to +125°C, 3.3 V ≤ V ≤ 5.5 V, 3.3 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP.
Page 590 CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) = −40 to +125°C) LVI Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage 4.56 LVI0 4.36 LVI1 4.16 LVI2 3.96 LVI3 3.76 LVI4 Note 1 Response time Minimum pulse width Reference voltage stabilization wait LWAIT0 Note 2...
Page 591: Chapter 33 Package Drawings
CHAPTER 33 PACKAGE DRAWINGS 80-PIN PLASTIC TQFP (FINE PITCH) (12x12) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 14.0±0.2 its true position (T.P.) at maximum material condition. 12.0±0.2 12.0±0.2 14.0±0.2 1.25 1.25 0.22±0.05 0.08 0.5 (T.P.)
Page 592 CHAPTER 33 PACKAGE DRAWINGS 80-PIN PLASTIC QFP (14x14) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.13 mm of 17.20±0.20 its true position (T.P.) at maximum material condition. 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13 0.65 (T.P.) 1.60±0.20 0.80±0.20...
Page 593: Chapter 34 Recommended Soldering Conditions
CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact an NEC Electronics sales representative. For technical information, see the following website.
Page 594 CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS Table 34-1. Surface Mounting Type Soldering Conditions (2/3) (2) 80-pin plastic TQFP (fine pitch) (12 × 12) µ PD780143GK-×××-9EU, 780144GK-×××-9EU, 780146GK-×××-9EU, 780148GK-×××-9EU, 780143GK(A)-×××-9EU, µ 780144GK(A)-×××-9EU, 780146GK(A)-×××-9EU, 780148GK(A)-×××-9EU, 780143GK(A1)-×××-9EU, µ 780144GK(A1)-×××-9EU, 780146GK(A1)-×××-9EU, 780148GK(A1)-×××-9EU, 780143GK(A2)-×××-9EU, µ 780144GK(A2)-×××-9EU, 780146GK(A2)-×××-9EU, 780148GK(A2)-×××-9EU Soldering Method Soldering Conditions Recommended...
Page 595 CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS Table 34-1. Surface Mounting Type Soldering Conditions (3/3) (3) 80-pin plastic TQFP (fine pitch) (12 × 12) µ PD78F0148M1GK-9EU, 78F0148M2GK-9EU, 78F0148M3GK-9EU, 78F0148M4GK-9EU, 78F0148M5GK-9EU, µ 78F0148M6GK-9EU, 78F0148M1GK(A)-9EU, 78F0148M2GK(A)-9EU, 78F0148M3GK(A)-9EU, µ 78F0148M4GK(A)-9EU, 78F0148M5GK(A)-9EU, 78F0148M6GK(A)-9EU, 78F0148M1GK(A1)-9EU, µ 78F0148M2GK(A1)-9EU, 78F0148M5GK(A1)-9EU, 78F0148M6GK(A1)-9EU Soldering Method Soldering Conditions Recommended...
Page 596: Chapter 35 Cautions For Wait
CHAPTER 35 CAUTIONS FOR WAIT 35.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware.
Page 597: Peripheral Hardware That Generates Wait
CHAPTER 35 CAUTIONS FOR WAIT 35.2 Peripheral Hardware That Generates Wait Table 35-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks. Table 35-1. Registers That Generate Wait and Number of CPU Wait Clocks Peripheral Hardware Register Access...
Page 598: Example Of Wait Occurrence
CHAPTER 35 CAUTIONS FOR WAIT 35.3 Example of Wait Occurrence <1> Watchdog timer <On execution of MOV WDTM, A> Number of execution clocks: 8 (5 clocks when data is written to a register that does not issue a wait (MOV sfr, A).) <On execution of MOV WDTM, #byte>...
Page 599: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the 78K0/KF1. Figure A-1 shows the development tool configuration. • Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/AT compatibles are compatible with PC98-NX series computers.
Page 600: Development Tool Configuration
The C library source file is not included in the software package. The project manager is included in the assembler package. The project manager is only used for Windows. Products other than in-circuit emulators IE-78K0-NS and IE-78K0-NS-A are all sold separately. User’s Manual U15947EJ2V0UD...
Page 601 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/2) (2) When using the in-circuit emulator IE-78K0K1-ET Software package • Software package Language processing software Debugging software • Assembler package • Integrated debugger • C compiler package • System simulator •...
Page 602: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 Development tools (software) common to the 78K/0 Series are combined in this package. 78K/0 Series software package µ Part number: S××××SP78K0 Remark ×××× in the part number differs depending on the host machine and OS used. µ...
Page 603: Language Processing Software
APPENDIX A DEVELOPMENT TOOLS A.2 Language Processing Software RA78K0 This assembler converts programs written in mnemonics into object codes executable Assembler package with a microcontroller. This assembler is also provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with a device file (DF780148) (sold separately).
Page 604: Control Software
APPENDIX A DEVELOPMENT TOOLS Remark ×××× in the part number differs depending on the host machine and OS used. µ S××××RA78K0 µ S××××CC78K0 ×××× Host Machine Supply Medium AB13 PC-9800 series, Windows (Japanese version) 3.5-inch 2HD FD IBM PC/AT compatibles BB13 Windows (English version) AB17...
Page 605: Debugging Tools (Hardware)
IE-78K0-NS-PA This board is connected to the IE-78K0-NS to expand its functions. Adding this board Performance board adds a coverage function and enhances debugging functions such as tracer and timer functions.
Page 606: When Using In-Circuit Emulator Ie-78K0K1-Et
The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using a 78K0/Kx1 product. It corresponds to the integrated debugger (ID78K0-NS). This emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine.
Page 607: Debugging Tools (Software)
Windows-based software. (supporting in-circuit emulators It has improved C-compatible debugging functions and can display the results of tracing IE-78K0-NS, IE-78K0-NS-A, and with the source program using an integrating window function that associates the source IE-78K0K1-ET) program, disassemble display, and memory display with the trace result. It should be used in combination with the device file (sold separately).
Page 608: Embedded Software
APPENDIX A DEVELOPMENT TOOLS A.7 Embedded Software µ The RX78K0 is a real-time OS conforming to the ITRON specifications. RX78K0 Real-time OS A tool (configurator) for generating the nucleus of the RX78K0 and multiple information tables is supplied. Used in combination with an assembler package (RA78K0) and device file (DF780148) (both sold separately).
Page 609: Appendix B Notes On Target System Design
NP-H80GC-TQ 370 mm NP-80GK TGK-080SDW 170 mm NP-H80GK-TQ 370 mm Figure B-1. Distance Between IE System and Conversion Adapter In-circuit emulator IE-78K0-NS, IE-78K0-NS-A, or IE-78K0K1-ET Target system Emulation board IE-780148-NS-EM1 Note 170 mm Emulation probe Conversion adapter NP-80GC, NP-80GC-TQ, NP-H80GC-TQ,...
Page 610: Connection Conditions Of Target System (When Using Np-80Gc-Tq)
APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. Connection Conditions of Target System (When Using NP-80GC-TQ) Emulation board IE-780148-NS-EM1 Emulation probe NP-80GC-TQ 24.8 mm Conversion adapter TGC-080SBP 11 mm 25 mm 21 mm 21 mm 40 mm 34 mm Target system User’s Manual U15947EJ2V0UD...
Page 611: Connection Conditions Of Target System (When Using Np-H80Gc-Tq)
APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-3. Connection Conditions of Target System (When Using NP-H80GC-TQ) Emulation board IE-780148-NS-EM1 Emulation probe NP-H80GC-TQ 25.3 mm Conversion 11 mm adapter TGC-080SBP 25 mm 21 mm 21 mm 45 mm 42 mm Target system User’s Manual U15947EJ2V0UD...
Page 612: Connection Conditions Of Target System (When Using Np-80Gk)
APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-4. Connection Conditions of Target System (When Using NP-80GK) Emulation board IE-780148-NS-EM1 Emulation probe NP-80GK 23 mm Conversion 11 mm adapter TGK-080SDW 18 mm 18 mm 40 mm 34 mm Target system User’s Manual U15947EJ2V0UD...
Page 613 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-5. Connection Conditions of Target System (When Using NP-H80GK-TQ) Emulation board IE-780148-NS-EM1 Emulation probe NP-H80GK-TQ 23 mm Conversion adapter 11 mm TGK-080SDW 18 mm 18 mm 42 mm 45 mm Target system User’s Manual U15947EJ2V0UD...
Page 614: Appendix C Register Index
APPENDIX C REGISTER INDEX C.1 Register Index (In Alphabetical Order with Respect to Register Names) A/D conversion result register (ADCR)........................284 A/D converter mode register (ADM) ..........................281 Analog input channel specification register (ADS) ......................283 Asynchronous serial interface control register 6 (ASICL6) ..................333 Asynchronous serial interface operation mode register 0 (ASIM0) ................303 Asynchronous serial interface operation mode register 6 (ASIM6) ................327 Asynchronous serial interface reception error status register 0 (ASIS0) ..............305...
Page 615 APPENDIX C REGISTER INDEX External interrupt rising edge enable register (EGP)....................437 Input switch control register (ISC) ..........................334 Internal expansion RAM size switching register (IXS)....................497 Internal memory size switching register (IMS) ......................496 Interrupt mask flag register 0H (MK0H) ........................435 Interrupt mask flag register 0L (MK0L)........................435 Interrupt mask flag register 1H (MK1H) ........................435 Interrupt mask flag register 1L (MK1L)........................435 Interrupt request flag register 0H (IF0H) ........................434...
Page 616 APPENDIX C REGISTER INDEX Port register 14 (P14) ..............................126 Port register 2 (P2)..............................126 Port register 3 (P3)..............................126 Port register 4 (P4)..............................126 Port register 5 (P5)..............................126 Port register 6 (P6)..............................126 Port register 7 (P7)..............................126 Power-fail comparison mode register (PFM) .......................285 Power-fail comparison threshold register (PFT) ......................285 Prescaler mode register 00 (PRM00) ..........................181 Prescaler mode register 01 (PRM01) ..........................181 Priority specification flag register 0H (PR0H) ......................436...
Page 617 APPENDIX C REGISTER INDEX 16-bit timer counter 00 (TM00)............................171 16-bit timer counter 01 (TM01)............................171 16-bit timer mode control register 00 (TMC00) ......................174 16-bit timer mode control register 01 (TMC01) ......................174 16-bit timer output control register 00 (TOC00)......................178 16-bit timer output control register 01 (TOC01)......................178 Timer clock selection register 50 (TCL50) ........................216 Timer clock selection register 51 (TCL51) ........................216 Transmit buffer register 10 (SOTB10).........................360...
Page 618: Register Index (In Alphabetical Order With Respect To Register Symbol)
APPENDIX C REGISTER INDEX C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ADCR: A/D conversion result register.......................284 ADM: A/D converter mode register.........................281 ADS: Analog input channel specification register...................283 ADTC0: Automatic data transfer address count register 0 .................381 ADTI0: Automatic data transfer interval specification register 0................388 ADTP0:...
Page 619 APPENDIX C REGISTER INDEX EGN: External interrupt falling edge enable register ..................437 EGP: External interrupt rising edge enable register ..................437 IF0H: Interrupt request flag register 0H......................434 IF0L: Interrupt request flag register 0L ......................434 IF1H: Interrupt request flag register 1H......................434 IF1L: Interrupt request flag register 1L ......................434 IMS: Internal memory size switching register....................496...
Page 620 APPENDIX C REGISTER INDEX Port register 7 ............................126 PCC: Processor clock control register......................143 PFM: Power-fail comparison mode register ....................285 PFT: Power-fail comparison threshold register....................285 PM0: Port mode register 0 ......................123, 184, 366 PM1: Port mode register 1 ..................123, 220, 238, 307, 334, 366 PM12: Port mode register 12 ...........................123 PM14:...
Page 621 APPENDIX C REGISTER INDEX TM50: 8-bit timer counter 50..........................214 TM51: 8-bit timer counter 51..........................214 TMC00: 16-bit timer mode control register 00 ....................174 TMC01: 16-bit timer mode control register 01 ....................174 TMC50: 8-bit timer mode control register 50 ......................218 TMC51: 8-bit timer mode control register 51 ......................218 TMCYC1: 8-bit timer H carrier control register 1 ....................238 TMHMD0:...
Page 622: Appendix D Revision History
APPENDIX D REVISION HISTORY The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters of each edition in which the revision was applied. (1/5) Edition Description Applied to: 1st edition Modification of reset value of the following registers in Table 3-5 Special Function CHAPTER 3 CPU (Modified Register List...
Page 623 APPENDIX D REVISION HISTORY (2/5) Edition Description Applied to: 1st edition Modification of the following contents in CHAPTER 30 ELECTRICAL SPECIFICATIONS CHAPTER 30 (Modified (TARGET VALUES) ELECTRICAL version) • Absolute Maximum Ratings SPECIFICATIONS • X1 Oscillator Characteristics (TARGET VALUES) • Subsystem Clock Oscillator Characteristics •...
Page 624 APPENDIX D REVISION HISTORY (3/5) Edition Description Applied to: 2nd edition Deletion of input switch control register (ISC) from and addition of port registers (P0 to P7, CHAPTER 4 PORT P12 to P14) to 4.3 Registers Controlling Port Function FUNCTIONS Modification of setting of output latch of P40 to P47, P50 to P57, P64, P65, and P67 in and addition of Note 2 to Table 4-5 Settings of Port Mode Register and Output Latch When Using Alternate Function...
Page 625 APPENDIX D REVISION HISTORY (4/5) Edition Description Applied to: 2nd edition Revision of CHAPTER 15 SERIAL INTERFACE UART6 CHAPTER 15 SERIAL INTERFACE UART6 Revision of CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Revision of CHAPTER 17 SERIAL INTERFACE CSIA0 CHAPTER 17 SERIAL INTERFACE CSIA0 Revision of CHAPTER 18 MULTIPLIER/DIVIDER...
Page 626 APPENDIX D REVISION HISTORY (5/5) Edition Description Applied to: 2nd edition Modification of Note 5 in Figure 25-2 Format of Low-Voltage Detection Register CHAPTER 25 LOW- (LVIM) VOLTAGE DETECTOR Addition of Note 2 and Caution to Figure 25-3 Format of Low-Voltage Detection Level Selection Register (LVIS) Modification of Figure 25-4 Timing of Low-Voltage Detector Internal Reset Signal Generation and Figure 25-5 Timing of Low-Voltage Detector Interrupt Signal...

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78kf1

NEC 78K0 User Manual

Chapter 1 Outline

Features

Applications

Ordering Information

Pin Configuration (Top View)

K1 Family Lineup

Block Diagram

Outline of Functions

Chapter 2 Pin Functions

Pin Function List

Description of Pin Functions

Pin I/O Circuits and Recommended Connection of Unused Pins

Chapter 3 Cpu Architecture

Memory Space

Processor Registers

Instruction Address Addressing

Operand Address Addressing

Chapter 4 Port Functions

Port Configuration

Registers Controlling Port Function

Port Function Operations

Chapter 5 External Bus Interface

Registers Controlling External Bus Interface

External Bus Interface Function Timing

Example of Connection with Memory

Chapter 6 Clock Generator

Functions of Clock Generator

Configuration of Clock Generator

Registers Controlling Clock Generator

System Clock Oscillator

Clock Generator Operation

Time Required to Switch between Ring-OSC Clock and X1 Input Clock

Time Required for CPU Clock Switchover

Clock Switching Flowchart and Register Setting

Chapter 7 16-Bit Timer/Event Counters 00 and 01

Functions of 16-Bit Timer/Event Counters 00 and 01

Configuration of 16-Bit Timer/Event Counters 00 and 01

Registers Controlling 16-Bit Timer/Event Counters 00 and 01

Operation of 16-Bit Timer/Event Counters 00 and 01

Cautions for 16-Bit Timer/Event Counters 00 and 01

Chapter 8 8-Bit Timer/Event Counters 50 and 51

Functions of 8-Bit Timer/Event Counters 50 and 51

Configuration of 8-Bit Timer/Event Counters 50 and 51

Registers Controlling 8-Bit Timer/Event Counters 50 and 51

Operations of 8-Bit Timer/Event Counters 50 and 51

Cautions for 8-Bit Timer/Event Counters 50 and 51

Chapter 9 8-Bit Timers H0 and H1

Functions of 8-Bit Timers H0 and H1

Configuration of 8-Bit Timers H0 and H1

Registers Controlling 8-Bit Timers H0 and H1

Operation of 8-Bit Timers H0 and H1

Chapter 10 Watch Timer

Functions of Watch Timer

Configuration of Watch Timer

Register Controlling Watch Timer

Watch Timer Operations

Cautions for Watch Timer

Chapter 11 Watchdog Timer

Functions of Watchdog Timer

Configuration of Watchdog Timer

Registers Controlling Watchdog Timer

Operation of Watchdog Timer

Chapter 12 Clock Output/Buzzer Output Controller

Functions of Clock Output/Buzzer Output Controller

Configuration of Clock Output/Buzzer Output Controller

Register Controlling Clock Output/Buzzer Output Controller

Clock Output/Buzzer Output Controller Operations

Chapter 13 A/D Converter

Functions of A/D Converter

Configuration of A/D Converter

Registers Used in A/D Converter

A/D Converter Operations

How to Read A/D Converter Characteristics Table

Cautions for A/D Converter

Chapter 14 Serial Interface Uart0

Functions of Serial Interface UART0

Configuration of Serial Interface UART0

Registers Controlling Serial Interface UART0

Operation of Serial Interface UART0