Page 1 CMOS 32-BIT SINGLE CHIP MICROCONTROLLER S1C31D50 Technical Manual ® Rev. 1.00 S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 2 Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products.
Page 3 Preface This is a technical manual for designers and programmers who develop a product using the S1C31D50. This document describes the functions of the IC, embedded peripheral circuit operations, and their control methods. Notational conventions and symbols in this manual Register address Peripheral circuit chapters do not provide control register addresses.
Page 4 Overview __________________________________________________________ 4-1 4.2. Bus Access Cycle ____________________________________________________ 4-2 4.3. Flash Memory ______________________________________________________ 4-3 4.3.1. Flash Memory Pin _______________________________________________________ 4-3 4.3.2. Flash Bus Access Cycle Setting _____________________________________________ 4-3 4.3.3. Flash Programming ______________________________________________________ 4-3 S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 5 7.2.3. Pull-Up/Pull-Down ______________________________________________________ 7-2 7.2.4. CMOS Output and High Impedance State ___________________________________ 7-3 7.3. Clock Settings ______________________________________________________ 7-3 7.3.1. PPORT Operating Clock __________________________________________________ 7-3 7.3.2. Clock Supply in SLEEP Mode _______________________________________________ 7-3 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 6 Output Pin and External Connection _________________________________ 10-1 10.2.1. Output Pin ____________________________________________________________ 10-1 10.3. Clock Settings ___________________________________________________ 10-2 10.3.1. RTCA Operating Clock __________________________________________________ 10-2 10.3.2. Theoretical Regulation Function __________________________________________ 10-2 10.4. Operations ______________________________________________________ 10-4 S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 7 Control Registers _________________________________________________ 12-5 UART (UART3) __________________________________________________ 13-1 13.1. Overview _______________________________________________________ 13-1 13.2. Input/Output Pins and External Connections __________________________ 13-2 13.2.1. List of Input/Output Pins ________________________________________________ 13-2 13.2.2. External Connections ___________________________________________________ 13-3 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 8 Terminating Data Transfer in Master Mode ________________________________ 14-11 14.5.5. Data Transfer in Slave Mode ____________________________________________ 14-11 14.5.6. Terminating Data Transfer in Slave Mode __________________________________ 14-12 14.6. Interrupts _____________________________________________________ 14-13 14.7. DMA Transfer Requests ___________________________________________ 14-14 S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 9 10-bit Addressing in Master Mode _______________________________________ 16-11 16.4.5. Data Transmission in Slave Mode_________________________________________ 16-12 16.4.6. Data Reception in Slave Mode __________________________________________ 16-14 16.4.7. Slave Operations in 10-bit Address Mode __________________________________ 16-15 16.4.8. Automatic Bus Clearing Operation ________________________________________ 16-16 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 10 Continuous Data Transmission and Compare Buffers __________________________ 18-6 18.5. Interrupts ______________________________________________________ 18-7 18.6. Application Example: Driving EL Lamp _________________________________ 18-7 18.7. Control Registers _________________________________________________ 18-8 12-bit A/D Converter (ADC12A) ____________________________________ 19-1 19.1. Overview _______________________________________________________ 19-1 S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 11 Clock Setting __________________________________________________________ 21-5 21.4.3. Sound DAC and external Audio AMP Settings ________________________________ 21-5 21.4.4. Sound Play State Transition ______________________________________________ 21-6 21.4.5. Sound Play Configuration________________________________________________ 21-8 21.4.6. Sound Start Command __________________________________________________ 21-9 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 12 I 2 C (I2C) Characteristics __________________________________________ 23-16 23.12. 23.13. 12-bit A/D Converter (ADC12A) Characteristics _______________________ 23-17 23.14. R/F Converter (RFC) Characteristics _________________________________ 23-18 Basic External Connection Diagram ________________________________ 24-1 Package ______________________________________________________ 25-1 S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 13 Appendix _____________________________________________________ 26-1 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 14 1. Overview 1.1. Features The S1C31D50 is a 32-bit ARM® Cortex®-M0+ MCU which integrates a specific hardware block called the HW Processor. The HW Processor can perform 2ch Voice/Audio Play, Voice Speed Conversion, and Self Memory Check without using any CPU resource. The S1C31D50 is suitable for home electronics, white goods, and battery-based products which require voice and audio playback.
Page 15 Reset when the supply voltage detector detects the set voltage level (can be enabled/ disabled using a register). Interrupt Non-maskable interrupt 6 systems (Reset, NMI, HardFault, SVCall, PendSV, SysTic) Programmable interrupt External interrupt: 3 systems Internal interrupt: 27 systems Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 16 TQFP14-80 (12mm x 12mm, 0.5mm pitch) QFP15-100 (14mm x 14mm, 0.5mm pitch) *1 SLEEP mode refers to deep sleep mode in the Cortex®-M0+ processor. *2 HALT mode refers to sleep mode in the Cortex®-M0+ processor. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 17 12bit A/D 16-bit timer #ADTRG Power generator convertor (T16) 8Ch. ADIN00-07 (PWGA) (ADC12A) 1 VREFA0 IR remote REMO controller CLPLS Sound_DAC SDACOUT_P (REMC3) SDACOUT_N 1 Ch. 1Ch. Figure 1.2.1 S1C31D50 Block Diagram Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 18 18 P14/UPMUX/ADIN3 P72/EXCL10 44 17 P13/UPMUX/ADIN4 P73/EXCL11 45 16 P06/UPMUX SWCLK/PD0 46 15 P05/UPMUX SWD/PD1 47 14 P04/UPMUX TEST 48 13 P03/UPMUX 9 10 11 12 Figure 1.3.1.1 S1C31D50 Pin Configuration Diagram (TQFP12-48) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 19 21 P11/UPMUX/ADIN6 P73/EXCL11 61 20 P06/UPMUX SWCLK/PD0 62 19 P05/UPMUX SWD/PD1 63 18 P04/UPMUX TEST 64 17 P03/UPMUX 9 10 11 12 13 14 15 16 Figure 1.3.1.2 S1C31D50 Pin Configuration Diagram (QFP13-64) Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 20 24 P06/UPMUX SWCLK/PD0 78 23 P05/UPMUX SWD/PD1 79 22 P04/UPMUX TEST 80 21 P03/UPMUX 9 10 11 12 13 14 15 16 17 18 19 20 Figure 1.3.1.3 S1C31D50 Pin Configuration Diagram (TQFP14-80) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 21 28 P02/UPMUX P76 99 27 P01/UPMUX 26 P00/UPMUX 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Figure 1.3.1.4 S1C31D50 Pin Configuration Diagram (QFP15-100) Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 22 I/O port ✓ UPMUX User-selected I/O (universal port multiplexer) Hi-Z I/O port UPMUX User-selected I/O (universal port multiplexer) ADIN7 ADC ch.7 Hi-Z I/O port UPMUX User-selected I/O (universal port multiplexer) ADIN6 ADC ch.6 S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 23 User-selected I/O (universal port multiplexer) Hi-Z I/O port ✓ UPMUX User-selected I/O (universal port multiplexer) Hi-Z I/O port ✓ UPMUX User-selected I/O (universal port multiplexer) Hi-Z I/O port ✓ UPMUX User-selected I/O (universal port multiplexer) Seiko Epson Corporation 1-10 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 24 ✓ EXCL00 16-bit PWM timer Ch.0 event counter input 0 Hi-Z I/O port ✓ EXCL01 16-bit PWM timer Ch.0 event counter input 1 Hi-Z I/O port ✓ Hi-Z I/O port ✓ S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 1-11 (Rev. 1.00)
Page 25 I/O port OSC4 OSC3 oscillator circuit output Hi-Z I/O port ✓ Hi-Z I/O port ✓ Note: In the peripheral circuit descriptions, the assigned signal name is used as the pin name. Seiko Epson Corporation 1-12 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 26 16-bit PWM timer Ch.n PWM output / capture input 2 TOUTn3/CAPn3 16-bit PWM timer Ch.n PWM output / capture input 3 Note: Do not assign a function to two or more pins simultaneously. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 1-13 (Rev. 1.00)
Page 27 P06/UPMUX P07/UPMUX ― ― P10/UPMUX/ADIN7 ― ― P11/UPMUX/ADIN6 ― P12/UPMUX/ADIN5 ― P13/UPMUX/ADIN4 P14/UPMUX/ADIN3 P15/UPMUX/ADIN2 P16/UPMUX/ADIN1 P17/UPMUX/ADIN0 P40/VREFA ― ― ― ― ― ― P45/#ADTRG P46/RTC1S ― ― ― ― ― ― Seiko Epson Corporation 1-14 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 28 ― ― ― ― ― P83/EXOSC P84/EXCL00 P85/EXCL01 ― ― ― ― ― ― P72/EXCL10 P73/EXCL11 ― ― ― ― ― PD0/SWCLK PD1/SWD TEST TEST ― ― ― ― ― ― S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 1-15 (Rev. 1.00)
Page 29 VDDQSPI is the dedicate power supply for SPI-Flash interface and P9x PORT. Figure 2.1.1.1 shows the PWGA configuration. PWGA REGMODE[1:0] REGSEL regulator Internal circuits REGDIS VDDQSPI QSPI Interface Figure 2.1.1.1 PWGA Configuration S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 30 The VD1 regulator also supports automatic mode in which the hardware detects a light load condition and automatically switches between normal mode and economy mode. Use the VD1 regulator in automatic mode when no special control is required. Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 31 CLGOSC1.OSC1WT[1:0] bits. Always use the IC in mode0 when V is 3.6 V or higher. • If you use two voltage mode, set mode1 before sleep or halt mode. • S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 32 An internal pull-up resistor is connected to the #RESET pin, so the pin can be left open. For the #RESET pin characteristics, refer to “#RESET pin characteristics” in the “Electrical Characteristics” chapter. Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 33 Note, however, that the software reset operations depend on the peripheral circuit. For more information, refer to “Control Registers” in each peripheral circuit chapter. Note: The MODEN bit of some peripheral circuits does not issue software reset. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 34 Reset request from the CPU Peripheral circuit software Reset state is canceled immediately reset (MODEN and SFTRST after the reset request is canceled. bits. The software reset operations de- pend on the peripheral circuit. Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 35 The oscillator and clock input circuit on/off state can be maintained or changed at SLEEP mode cancelation. • Provides the FOUT function to output an internal clock for driving external ICs or for monitoring the internal state. Figure 2.3.1.1 shows the CLG configuration. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 36 * Indicates the status when the pin is configured for CLG. If the port is shared with the CLG input/output function and other functions, the CLG function must be assigned to the port. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 37 Interrupt control OSC1STPIE OSC1STPIF Feedback Drain circuit OSC2 OSC1STAIE OSC1STAIF resistor R resistor R External drain Interrupt capacitor C Internal drain capacitor C controller Clock oscillator Figure 2.3.3.2 OSC1 Oscillator Circuit Configuration S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 38 For the recommended parts and the oscillation characteristics, refer to the “Basic External Connection Diagram” chapter and the “Electrical Characteristics” chapter, respectively. Seiko Epson Corporation 2-10 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 39 EXOSC has no oscillation stabilization waiting circuit included, therefore, it must be enabled when a stabilized clock is being supplied. For the input clock characteristics, refer to “EXOSC external clock input characteristics” in the “Electrical Characteristics” chapter. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 2-11...
Page 40 Note: The oscillation stabilization waiting time is always expended at start of oscillation even if the os- cillation stabilization waiting completion flag has not be cleared to 0. Seiko Epson Corporation 2-12 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 41 Oscillator circuit enable (CLGOSC.OSC1EN) Oscillation inverter INV1B[1:0] setting gain INV1N[1:0] setting gain Oscillation waveform Startup boosting Normal operation operation Figure 2.3.4.2 Operation Example when the Oscillation Startup Control Circuit is Used S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 2-13 (Rev. 1.00)
Page 42 7. OSC1CLK can be used if the CLGINTF.OSC1STAIF bit = 1 after an interrupt occurs. The setting values of the CLGOSC1.INV1N[1:0], CLGOSC1.CGI1[2:0], CLGOSC1.OSC1WT[1:0] and CLGOSC1.INV1B[1:0] bits should be determined after performing evaluation using the populated circuit board. Seiko Epson Corporation 2-14 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 43 0x0096 to the SYSPROT.PROT[15:0] bits before the register setting can be altered. For the transition between the operating modes including the system clock switching, refer to “Operating Mode.” S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 2-15...
Page 44 (SLEEPDEEP bit = 1) Real-time clock operating clock OSC1CLK * The real-time clock keeps operating in SLEEP mode as the clock is being supplied.. Figure 2.3.4.4 Clock Control Example in SLEEP Mode Seiko Epson Corporation 2-16 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 45 7. The OSC1 oscillation stops if the CLGINTF.OSC1STPIF bit = 1 after an interrupt occurs. If the CLGOSC1.OSDRB bit = 1, the hardware restarts the OSC1 oscillator circuit. Note: Enabling the oscillation stop detection function increase the oscillation stop detector current (I OSD1 S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 2-17 (Rev. 1.00)
Page 46 This mode can be set while no software processing is required and it reduces power consumption as compared with RUN mode. HALT mode is classified into “IOSC HALT,” “OSC1 HALT,” “OSC3 HALT,” and “EXOSC HALT” by the SYSCLK clock source. Seiko Epson Corporation 2-18 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 47 The conditions listed below generate the HALT/SLEEP cancelation signal to cancel HALT or SLEEP mode and put the CPU into RUN mode. • Interrupt request from a peripheral circuit • NMI from the watchdog timer • Reset request S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 2-19 (Rev. 1.00)
Page 48 CPU core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation 2-20 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 49 Bits 3–2 Reserved Bits 1–0 REGMODE[1:0] These bits control the V regulator operating mode. Table 2.6.1 Internal Regulator Operating Mode PWGACTL.REGMODE[1:0] bits Operating mode Economy mode Normal mode Reserved Automatic mode S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 2-21 (Rev. 1.00)
Page 50 Table 2.6.3 SYSCLK Clock Source and Division Ratio Settings CLGSCLK. CLGSCLK.CLKSRC[1:0] bits CLKDIV[1:0] bits IOSCCLK OSC1CLK OSC3CLK EXOSCCLK Reserved 1/16 Reserved Reserved Reserved Reserved CLG Oscillation Control Register Register name Bit name Initial Reset Remarks Seiko Epson Corporation 2-22 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 51 Stop oscillating or clock input Each bit corresponds to the clock source as follows: CLGOSC.EXOSCEN bit: EXOSC clock input CLGOSC.OSC3EN bit: OSC3 oscillator circuit CLGOSC.OSC1EN bit: OSC1 oscillator circuit CLGOSC.IOSCEN bit: IOSC oscillator circuit S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 2-23 (Rev. 1.00)
Page 52 Table 2.6.4 IOSCCLK Frequency Selection IOSCCLK frequency CLGIOSC. VD1 voltage mode = VD1 voltage mode = IOSCFQ[1:0] bits mode0 mode1 Setting prohibited 8 MHz 2.0 MHz 1.8 MHz 1.0 MHz 0.9 MHz Seiko Epson Corporation 2-24 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 53 Table 2.6.5 OSC1 Internal Gate Capacitance Setting CLGOSC1.CGI1[2:0] bits Capacitance Max. ↑ ↓ Min. For more information, refer to “OSC1 oscillator circuit characteristics, Internal gate capacitance C ” in the “Electrical Characteristics” chapter. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 2-25 (Rev. 1.00)
Page 54 These bits set the oscillation stabilization waiting time for the OSC1 oscillator circuit. Table 2.6.8 OSC1 Oscillation Stabilization Waiting Time Setting CLGOSC1.OSC1WT[1:0] bits Oscillation stabilization waiting time 65,536 clocks 16,384 clocks 4,096 clocks Reserved Seiko Epson Corporation 2-26 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 55 The auto-trimming function does not work if the OSC1 oscillator circuit is stopped. Make sure the CLGINTF.OSC1STAIF bit is set to 1 before starting the trimming operation. Be sure to avoid altering the CLGIOSC.OSC3FQ[1:0] bits while the auto-trimming is being executed. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 2-27 (Rev. 1.00)
Page 56 CLGINTF.OSC1STAIF bit: OSC1 oscillation stabilization waiting completion interrupt CLGINTF.IOSCSTAIF bit: IOSC oscillation stabilization waiting completion interrupt Note: The CLGINTF.IOSCSTAIF bit is 0 after system reset is canceled, but IOSCCLK has already been stabilized. Seiko Epson Corporation 2-28 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 57 CLGINTE.OSC3TEDIE bit: OSC3 oscillation auto-trimming completion interrupt CLGINTE.OSC3STAIE bit: OSC3 oscillation stabilization waiting completion interrupt CLGINTE.OSC1STAIE bit: OSC1 oscillation stabilization waiting completion interrupt CLGINTE.IOSCSTAIE bit: IOSC oscillation stabilization waiting completion interrupt S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 2-29 (Rev. 1.00)
Page 58 Disable external output Note: Since the FOUT signal generated is out of sync with writings to the CLGFOUT.FOUTEN bit, a glitch may occur when the FOUT output is enabled or disabled. Seiko Epson Corporation 2-30 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 59 For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, Debug pin pull-up resistors R ” in the “Electrical Characteristics” chapter. R and R are not required when DBG1–2 DBG1 DBG2 using the debug pins as general-purpose I/O port pins. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 60 Memory mapped access area for external Flash memory (1M bytes) (Device size: 32 bits) 0x0004_0000 0x0003_ffff Reserved 0x0003_0000 0x0002_ffff Flash ROM192KB(for Program & Voice Data) (Device size: 32 bits) 0x0000_0000 Figure 4.1.1 Memory Map S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 61 Number of bus access Device size Access size cycles 8 bits 8 bits 16 bits 32 bits 16 bits 8 bits 16 bits 32 bits 32 bits 8 bits 16 bits 32 bits Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 62 The RAM can be used to execute the instruction codes copied from another memory as well as storing variables or other data. This allows higher speed processing and lower power consumption than Flash memory. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 63 4.7. Memory Mapped Access Area For External Flash Memory This area is used to read data from the external Flash memory via the quad synchronous serial interface. For more information, refer to the “Quad Synchronous Serial Interface” chapter. Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 64 REGSEL bit = 0 REGSEL bit = 1 2.1 MHz (max.) 16.6 MHz (max.) 1.05 MHz (max.) 8.4 MHz (max.) Note: Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 65 Figure 5.1.1 shows the configuration of the interrupt system. Clock Generator HALT/SLEEP cancelation signal CPU core Peripheral circuit Interrupt request NVIC Peripheral circuit Interrupt request Watchdog timer Figure 5.1.1 Configuration of Interrupt System S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 66 • 1-day, 1-hour, 1-minute, and 1- second • 1/32-second, 1/8-second, 1/4- second, and 1/2-second • Stopwatch 1 Hz, 10 Hz, and 100 • Alarm • Theoretical regulation completion 0x5c HW Proceesor interrupt Proceesor Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 67 Underﬂow 0x90 T16 CH3 16-bit timer Ch.3 interrupt Underﬂow 0x94 SPI CH1 Synchronous serial interface • End of transmission Ch.1 interrupt • Receive buﬀer full • Transmit buﬀer empty • Overrun error S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 68 • Transmit buﬀer empty 0xb4 REMC IR remote controller • Compare AP interrupt • Compare DB 0xb8 System Reserved *1 Either reset or NMI can be selected as the watchdog timer interrupt via software. Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 69 The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This interrupt takes precedence over other interrupts and is unconditionally accepted by the CPU. For detailed information on generating NMI, refer to the “Watchdog Timer” chapter. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 70 Priority level for each channel is selectable from two levels. • DMA transfers are allowed even if the CPU is placed into HALT mode. Figure 6.1.1 shows the configuration of the DMAC. Table 6.1.1 DMAC Channel Configuration of S1C31D50 Item S1C31D50 Number of channels 4 channels (Ch.0 to Ch.3)
Page 71 256 bytes DMACCPTR.CPTR[31:0] (CPTR[7:0] = 0x00) DMACCPTR.CPTR[31:0] + 0x080 9 to 16 512 bytes DMACCPTR.CPTR[31:0] (CPTR[8:0] = 0x000) DMACCPTR.CPTR[31:0] + 0x100 16 to 32 1,024 bytes DMACCPTR.CPTR[31:0] (CPTR[9:0] = 0x000) DMACCPTR.CPTR[31:0] + 0x200 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 72 Offset Base address set with the DMACCPTR register Figure 6.4.2 Data Structure Address Map (when 4 channels are implemented) The alternate data structure base address can be determined from the DMACACPTR.ACPTR[31:0] bits. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 73: Table Of Contents
Set the size of the data to be read from the transfer source. It should be the same value as the dst_size. Table 6.4.3.4 Size of Data Read from Transfer Source src_size Data size Reserved Word Halfword Byte Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 74 Peripheral scatter-gather transfer (for alternate data structure) Peripheral scatter-gather transfer (for primary data structure) Memory scatter-gather transfer (for alternate data structure) Memory scatter-gather transfer (for primary data structure) Ping-pong transfer Auto-request transfer Basic transfer Stop S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 75 DMA transfer 1 DMA transfer 2 DMA transfer 3 DMA transfer 4 DMA transfer 7 DMA transfer 8 DMACENDIF.ENDIFn DMA transfer request Figure 6.5.2.1 Auto-Request Transfer Operation Example (N = 8, 2 = 2) Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 76 (cycle_ctrl = 0x3, 2R = 4, N = 7) completion interrupt Task E DMA transfer request DMA transfer request DMA transfer completion interrupt (cycle_ctrl = 0x0) Termination Figure 6.5.3.1 Ping-Pong Transfer Operation Example S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 77: Control Data
Transfer destination end pointer Transfer source end pointer Reserved Control data Data structure for Task A Transfer destination end pointer Transfer source end pointer Figure 6.5.4.1 Example of Data Structure Table for Scatter-Gather Transfer Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 78 Copy the data structure for Task D to the alternate data structure. (cycle_ctrl = 0x1, 2R = 4, N = 4) Termination DMA transfer completion interrupt Figure 6.5.4.2 Memory Scatter-Gather Transfer Operation Example S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 79: Dst_Inc
= 0x2 R_power = 0x2 n_minus_1 = Number of tasks × 4 - 1 cycle_ctrl = 0x4 3. The DMA transfer is completed when a DMA transfer completion interrupt occurs. Seiko Epson Corporation 6-10 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 80 Copy the data structure for Task D to the alternate data structure. (cycle_ctrl = 0x1, 2R = 4, N = 4) Task D DMA transfer completion interrupt Figure 6.5.5.1 Peripheral Scatter-Gather Transfer Operation Example S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 6-11 (Rev. 1.00)
Page 81: Src_Size
CPU core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation 6-12 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 82 Control data is being read. Idle Bits 3–1 Reserved Bit 0 MSTENSTAT This bit indicates the DMA controller status. 1 (R): DMA controller is operating. 0 (R): DMA controller is idle. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 6-13 (Rev. 1.00)
Page 83 1 (W): Issue a software DMA transfer request 0 (W): Ineffective Each bit corresponds to a DMAC channel (e.g. bit n corresponds to Ch.n). The high-order bits for the unimplemented channels are ineffective. Seiko Epson Corporation 6-14 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 84 1 (W): Disable DMAC channel (The DMACENSET register is cleared to 0.) 0 (W): Ineffective Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 6-15 (Rev. 1.00)
Page 85 These bits decrease the priority of each channel. 1(W): Decrease priority (The DMACPRSET register is cleared to 0.) 0 (W): Ineffective Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective. Seiko Epson Corporation 6-16 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 86 0 (W): Ineffective 1 (R): Interrupt has been enabled. 0 (R): Interrupt has been disabled. Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 6-17 (Rev. 1.00)
Page 87 0x00 – ERRIECLR – – Bits 31–1 Reserved Bit 0 ERRIECLR This bit disables DMA error interrupts. 1 (W): Disable interrupt (The DMACERRIESET register is cleared to 0.) 0 (W): Ineffective Seiko Epson Corporation 6-18 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 88 Note: ‘x’, which is used in the port names Pxy, register names, and bit names, refers to a port group (x= 0, 1, 2, ··· , d) and ‘y’ refers to a port number (y = 0, 1, 2, ··· , 7). Figure 7.1.1 shows the configuration of PPORT. Table 7.1.1 Port Configuration of S1C31D50 Item S1C31D50...
Page 89 Falling time (port level = high → low) [second] High level Schmitt input threshold voltage [V] Low level Schmitt input threshold voltage [V] : Pull-up/pull-down resistance [W] Pin capacitance [F] : Parasitic capacitance on the board [F] BOARD Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 90 PPORT, the input port function is also deactivated. However, the control registers can be altered. If the PPORTCLK.DBRUN bit = 1, the CLK_PPORT supply is not suspended and the chattering filter will keep operating in a debug state. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 91 When using the Pxy port pin as a general-purpose output pin, perform the following software initial settings: 1. Set the PPORTPxIOEN.PxOENy bit to 1. (Enable output) 2. Set the PPORTPxMODSEL.PxSELy bit to 0. (Enable GPIO function) Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 92 If the PPORTPxMODSEL.PxSELy bit for the port without a GPIO function is set to 0, the port goes into initial status (refer to “Initial Settings”). The GPIO control bits are configured to a read- only bit always read out as 0. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 93 To issue a reset request only when low-level signals longer than the time configured are input, enable the chattering filter function for all the ports used for key-entry reset. The pins configured for key-entry reset can also be used as general-purpose input pins. Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 94 Clearing the PPORTPxINTF.PxIFy bit also clears the PPORTINTFGRP.PxINT bit. If the port is set to interrupt disabled status by the PPORTPxINTCTL. PxIEy bit, the PPORTINTFGRP.PxINT bit will not be set even if the PPORTPxINTF.PxIFy bit is set to 1. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 95 When in- put is disabled (PPORTPxIOEN.PxIENy bit = 0), these bits are always read as 0. When the port is used for a peripheral I/O function, the input value cannot be read out from these bits. Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 96 PPORTPxRCTL.PxRENy bit setting is ineffective regardless of how the PPORTPxIOEN.PxIENy bit is set and the port is not pulled up/down. These bits do not affect the pull-up/down control when the port is used as a peripheral I/O function. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 97 *1: The bit configuration differs depending on the port group. Bits 15–8 Reserved Bits 7–0 PxCHATEN[7:0] These bits enable/disable the chattering filter function. 1 (R/W): Enable (The chattering filter is used.) 0 (R/W): Disable (The chattering filter is bypassed.) Seiko Epson Corporation 7-10 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 98 These bits select the peripheral I/O function to be assigned to each port pin. Table 7.6.1 Selecting Peripheral I/O Function PPORTPxFNCSEL.PxyMUX[1:0] bits Peripheral I/O function Function 3 Function 2 Function 1 Function 0 This selection takes effect when the PPORTPxMODSEL.PxSELy bit = 1. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 7-11 (Rev. 1.00)
Page 99 1/32,768 1/16,384 1/8,192 1/4,096 1/2,048 1/1,024 1/512 1/256 1/128 1/64 1/32 1/16 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Seiko Epson Corporation 7-12 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 100 1 (R): A port generated an interrupt 0 (R): No port generated an interrupt The PPORTINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt is cleared. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 7-13 (Rev. 1.00)
Page 101 – – UPMUX – – – – – – UPMUX – – – – – – UPMUX – – – – – – *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation 7-14 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 102 – – – – UPMUX ADC12A ADIN2 – – – – UPMUX ADC12A ADIN1 – – – – UPMUX ADC12A ADIN0 – – *1: Refer to the “Universal Port Multiplexer” chapter. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 7-15 (Rev. 1.00)
Page 103 – – – – UPMUX – – – – – – UPMUX – – – – – – UPMUX – – – – *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation 7-16 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 104 – – – – UPMUX – – – – – – UPMUX – – – – – – UPMUX – – – – *1: Refer to the “Universal Port Multiplexer” chapter. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 7-17 (Rev. 1.00)
Page 105 – – – – – – – ADC12A #ADTRG – – – – – – RTCA RTC1S – – – – – – – – – – – – – – Seiko Epson Corporation 7-18 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 106 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 7-19 (Rev. 1.00)
Page 107 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Seiko Epson Corporation 7-20 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 108 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 7-21 (Rev. 1.00)
Page 109 – – – – – – T16B Ch.0 EXCL01 – – – – – – – – – – – – – – – – – – – – – – Seiko Epson Corporation 7-22 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 110 – – – – QSPI Ch.0 QSDIO02 – – – – – – QSPI Ch.0 QSDIO03 – – – – – – QSPI Ch.0 #QSPISS0 – – – – – – S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 7-23 (Rev. 1.00)
Page 111 FOUT – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Seiko Epson Corporation 7-24 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 112 – – – – – OSC3 – – – – – – OSC4 – – – – – – – – – – – – – – – – – – S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 7-25 (Rev. 1.00)
Page 113 3–2 KRSTCFG[1:0] R/WP 1–0 CLKSRC[1:0] R/WP PPORTINTFGRP 15–8 – 0x00 – – (P Port Interrupt – – Flag Group Register) PAINT P9INT P8INT P7INT P6INT P5INT P4INT P3INT P2INT P1INT P0INT Seiko Epson Corporation 7-26 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 114 Initialize the peripheral circuit. Set the PPORTPxFNCSEL.PxyMUX[1:0] bits of the I/O port to 0x1. (Select peripheral I/O function 1) Set the PPORTPxMODSEL.PxSELy bit of the I/O port to 1. (Enable peripheral I/O function) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 115 Do not assign a peripheral input function to two or more I/O ports. Although the I/O ports output the same waveforms when an output function is assigned to two or more I/O port, a skew oc- curs due to the internal delay. Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 116 Although WDT2 stops operating when the CLK_WDT2 supply is suspended, the register retains the status before DEBUG mode was entered. If the WDT2CLK.DBRUN bit = 1, the CLK_WDT2 supply is not suspended and WDT2 will keep operating in DE- BUG mode. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 117 1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection) 2. Write 0xa to the WDT2CTL.WDTRUN[3:0] bits. (Stop WDT2) 3. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection) Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 118 If the clock source stops in SLEEP mode, WDT2 stops. To prevent generation of an unnecessary NMI or reset after clearing SLEEP mode, reset WDT2 before executing the slp instruction. WDT2 should also be stopped as required using the WDT2CTL.WDTRUN[3:0] bits. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 119 IOSC OSC1 OSC3 EXOSC 1/65,536 1/128 1/65,536 1/32,768 1/32,768 1/16,384 1/16,384 1/8,192 1/8,192 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 120 Always 0x0 is read if a value other than 0xa is written. Since an NMI or reset may be generated immediately after running depending on the counter value, WDT2 should also be reset concurrently when running WDT2. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 121 These bits set the NMI/reset generation cycle. The value set in this register is compared with the 10-bit counter value while WDT2 is running, and an NMI or reset is generated when they are matched. Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 122 * Indicates the status when the pin is configured for RTCA. If the port is shared with the RTCA output function and other functions, the RTCA function must be assigned to the port. For more information, refer to the “I/O Ports” chapter. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 10-1...
Page 123 32,768/fOSC1 ± ∆T [s] 32,768/fOSC1 [s] RTC1S RTCACTLH.RTCTRMBSY Theoretical regulation Writing to the RTCACTLH.RTCTRM[6:0] bits completion interrupt *∆ T = correction time set in the RTCACTLH.RTCTRM[6:0] bits Figure 10.3.2.1 RTC1S Signal Waveform Seiko Epson Corporation 10-2 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 124 1 Hz counter value at the same timing as when the 1 Hz counter changes to 0x7f. Also an interrupt occurs depending on the counter value at this time. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 10-3 (Rev.
Page 125 3. Write 1 to the RTCAINTF.ALARMIF bit to clear the alarm interrupt flag. 4. Write 1 to the RTCAINTE.ALARMIE bit to enable alarm interrupts. When the real-time clock counter reaches the alarm time set in Step 2, an alarm interrupt occurs. Seiko Epson Corporation 10-4 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 126 If the two read values are the same, assume that the count values are read correctly. ii. If different values are read, perform reading once more and compare the read value with the previous one. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 10-5...
Page 127 25/256 s 25/256 s 26/256 s 26/256 s 25/256 s 25/256 s 26/256 s 26/256 s 26/256 s x 6 + 25/256 x 4 = 1second Figure 10.4.4.1 Stopwatch Count-Up Patterns Seiko Epson Corporation 10-6 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 128 CPU core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 10-7 (Rev.
Page 129 This selection changes the count range of the hour counter. Note, however, that the counter value is not updated automatically, therefore, it must be programmed again. Note: Be sure to avoid writing to this bit when the RTCACTLL.RTCRUN bit = 1. Bit 3 Reserved Seiko Epson Corporation 10-8 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 130 When the real-time clock counter stops counting by writing 0 to this bit, the counter retains the value when it stopped. Writing 1 to this bit again resumes counting from the value retained. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 10-9...
Page 131 00 seconds 01 second · · · · · · · · · 09 seconds 10 seconds · · · · · · · · · 59 seconds Bits 7–0 Reserved Seiko Epson Corporation 10-10 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 132 The RTCAALM2.RTCMIHA[2:0] bits and the RTCAALM2.RTCMILA[3:0] bits set the 10- minute digit and 1-minute digit of the alarm time, respectively. A value within 0 to 59 minutes can be set in BCD code. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 10-11...
Page 133 The stopwatch counter stops in sync with the stopwatch clock after 0 is written to the RT- CASWCTL.SWRUN bit. Therefore, the counter value may be incremented (+1) from the value at writing 0. Seiko Epson Corporation 10-12 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 134 The counter value may not be read correctly while the 1 Hz counter is running. These bits must be read twice and assume the counter value was read successfully if the two read re- sults are the same. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 10-13...
Page 135 10-minute digit and the 1-minute digit of the minute counter, respectively. The setting/read values are a BCD code within the range from 0 to 59. Note: Be sure to avoid writing to the RTCAHUR.RTCMIH[2:0]/RTCMIL[3:0] bits while the RT- CACTLL.RTCBSY bit = 1. Seiko Epson Corporation 10-14 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 136 29 for February in a leap year, or to 30 for April/June/September/November). Note: Be sure to avoid writing to the RTCAMON.RTCDH[1:0]/RTCDL[3:0] bits while the RT- CACTLL.RTCBSY bit = 1. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 10-15 (Rev. 1.00)
Page 137 10-year digit and the 1-year digit of the year counter, respectively. The setting/read values are a BCD code within the range from 0 to 99. Note: Be sure to avoid writing to the RTCAYAR.RTCYH[3:0]/RTCYL[3:0] bits while the RTCACTLL. RTCBSY bit = 1. Seiko Epson Corporation 10-16 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 138 The following shows the correspondence between the bit and interrupt: RTCAINTF. ALARMIF bit: Alarm interrupt RTCAINTF.T1DAYIF bit: 1-day interrupt RTCAINTF.T1HURIF bit: 1-hour interrupt RTCAINTF.T1MINIF bit: 1-minute interrupt RTCAINTF.T1SECIF bit: 1-second interrupt RTCAINTF.T1_2SECIF bit: 1/2-second interrupt RTCAINTF.T1_4SECIF bit: 1/4-second interrupt S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 10-17 (Rev. 1.00)
Page 139 RTCAINTE.ALARMIE bit: Alarm interrupt RTCAINTE.T1DAYIE bit: 1-day interrupt RTCAINTE.T1HURIE bit: 1-hour interrupt RTCAINTE.T1MINIE bit: 1-minute interrupt RTCAINTE.T1SECIE bit: 1-second interrupt RTCAINTE.T1_2SECIE bit: 1/2-second interrupt RTCAINTE.T1_4SECIE bit: 1/4-second interrupt RTCAINTE.T1_8SECIE bit: 1/8-second interrupt Seiko Epson Corporation 10-18 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 140 - Continuous operation is also possible. Figure 11.1.1 shows the configuration of SVD3. Table 11.1.1 SVD3 Configuration of S1C31D50 Item S1C31D50 Power supply voltage to be detected...
Page 141 EXSVD input impedance R . For the EXSVDn pin input voltage range and the EXSVD input impedance, refer to EXSVD “Supply Voltage Detector Characteristics” in the “Electrical Characteristics” chapter. Seiko Epson Corporation 11-2 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 142 CLK_SVD3 supply is suspended, the registers retain the status before DEBUG mode was entered. If the SVD3CLK.DBRUN bit = 1, the CLK_SVD3 supply is not suspended and SVD3 will keep operating in DE- BUG mode. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 11-3 (Rev. 1.00)
Page 143 SVD3INTF.SVDDT bit is set to 1 (low power supply voltage is detected). This mode can keep detecting power supply voltage drop after the voltage detection masking time has elapsed even if the IC is placed into SLEEP status or accidental clock stoppage has occurred. Seiko Epson Corporation 11-4 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 144 SVD3 operating status SVD3INTF.SVDDT Low power supply voltage detection interrupt VSVD : Level set using the SVD3CTL.SVDC[4:0] bits : Voltage detection masking time : Voltage detection operation Figure 11.4.2.1 SVD3 Operations S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 11-5 (Rev. 1.00)
Page 145 SVDMD[1:0] Cleared to 0 to set continuous operation mode. MODEN The set value (1) is retained. SVD3INTF SVDIF The status (1) before being reset is retained. SVD3INTE SVDIE Cleared to 0. Seiko Epson Corporation 11-6 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 146 1/16 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Note: The clock frequency should be set to around 32 kHz. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 11-7 (Rev. 1.00)
Page 147 These bits enable/disable the reset issuance function when a low power supply voltage is detected. 0xa (R/WP): Enable (Issue reset) Other than 0xa (R/WP): Disable (Generate interrupt) For more information on the SVD3 reset issuance function, refer to “SVD3 Reset.” Seiko Epson Corporation 11-8 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 148 • The SVD3 internal circuit is initialized if the SVD3CTL.SVDSC[1:0] bits, SVD3CTL.SVDRE[3:0]bits, or SVD3CTL.SVDMD[1:0] bits are altered while SVD3 is in operation after 1 is written to the SVD3CTL.MODEN bit. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 11-9 (Rev. 1.00)
Page 149 • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 11-10 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 150 • Repeat mode or one-shot mode is selectable. • Can generate counter underflow interrupts. Figure 12.1.1 shows the configuration of a T16 channel. Table 12.1.1 T16 Channel Configuration of S1C31D50 Item S1C31D50 Number of channels 8 channels (Ch.0–Ch.7) Event counter function Not supported (No EXCLm pins are provided.)
Page 151 - 1 x - 2 x - 3 Counter Figure 12.3.4.1 Count Down Timing Note that the EXOSC clock is selected for the channel that does not support the event counter function. Seiko Epson Corporation 12-2 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 152 Underflow cycle T16_nTR register setting Counter Time 0x0000 PRESET = 1 PRUN = 0 Software control PRUN = 1 PRUN = 1 Underflow interrupt Figure 12.4.3.1 Count Operations in Repeat Mode S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 12-3 (Rev. 1.00)
Page 153 CPU core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation 12-4 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 154 (Note 2) When the T16_nCLK.CLKSRC[1:0] bits are set to 0x3, EXCLm is selected for the channel with an event counter function or EXOSC is selected for other channels. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 12-5...
Page 155 This bit retains 1 during presetting and is automatically cleared to 0 after presetting has finished. Bit 0 MODEN This bit enables the T16 Ch.n operations. 1 (R/W): Enable (Start supplying operating clock) 0 (R/W): Disable (Stop supplying operating clock) Seiko Epson Corporation 12-6 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 156 This bit enables T16 Ch.n underflow interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 12-7 (Rev. 1.00)
Page 157 Can issue a DMA transfer request when a receive buffer one byte full or a transmit buffer empty occurs. • Input pin can be pulled up with an internal resistor. • The output pin is configurable as an open-drain output. • Provides the carrier modulation output function. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 13-1 (Rev. 1.00)
Page 158 Figure 13.1.1 shows the UART3 configuration. Table 13.1.1 UART3 Channel Configuration of S1C31D50 Item S1C31D50 Number of channels 3 channels (Ch.0 to Ch.2) UART3 Ch.n BRDIV Baud rate CLK_UART3_n BRT[7:0] generator CLKSRC[1:0] FMD[3:0] CLKDIV[1:0] Clock generator DBRUN CHLN MODEN PREN...
Page 159 UART3_nMOD.INVRX bit and the UART3_nMOD.INVTX bit, respectively, to 1. Note: Unless otherwise specified, this chapter shows input/output signals with non-inverted wave- forms (UART3_nMOD.INVRX bit = 0, UART3_nMOD.INVTX bit =0). S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 13-3 (Rev. 1.00)
Page 160 FMD: UART3_nBR.FMD[3:0] setting value (0 to 15) For the transfer rate range configurable in the UART3, refer to “UART Characteristics, Transfer baud rates U and U ” in the “Electrical Characteristics” chapter. BRT1 BRT2 Seiko Epson Corporation 13-4 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 161 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 st: start bit, sp: stop bit, p: parity bit Figure 13.4.1 Data Format S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 13-5 (Rev. 1.00)
Page 162 Even if transmit data is being output from the USOUTn pin, the next transmit data can be written to the UART3_nTXD register after making sure the UART3_nINTF.TBEIF bit is set to 1. Seiko Epson Corporation 13-6 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 163 UART3_nTXD register address Control data dst_inc 0x3 (no increment) dst_size 0x0 (byte) src_inc 0x0 (+1) src_size 0x0 (byte) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 13-7 (Rev. 1.00)
Page 164 Read receive data (1 byte) from the UART3_nRXD register the UART3_nRXD register Read receive data (1 byte) from the UART3_nRXD register Receive data remained? Receive data remained? Figure 13.5.3.2 Data Reception Flowcharts Seiko Epson Corporation 13-8 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 165 Data transfer control is identical to that for normal interface even if the IrDA interface function is enabled. USINn USOUTn LEDA S1C31 UART3 Infrared communication module Figure 13.5.4.1 Example of Connections with an Infrared Communication Module S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 13-9 (Rev. 1.00)
Page 166 Use the following equations to calculate the setting values for obtaining the desired frequency. ��_��3 [ �� ] �� = (��. 13.2) (�� + 1) × 2 Where CLK_UART3: UART3 operating clock frequency [Hz] CRPER: UART3_nCAWF.CRPER[7:0] setting value (0 to 255) Seiko Epson Corporation 13-10 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 167 When an overrun error occurs, the UART3_nINTF.OEIF bit (overrun error interrupt flag) is set to 1. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 13-11...
Page 168 After a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the DMA control, refer to the “DMA Controller” chapter. Seiko Epson Corporation 13-12 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 169 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Note: The UART3_nCLK register settings can be altered only when the UART3_nCTL.MODEN bit = 0. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 13-13 (Rev. 1.00)
Page 170 This bit sets the USOUTn pin output mode. 1 (R/W): Open-drain output 0 (R/W): Push-pull output Bit 4 IRMD This bit enables the IrDA interface function. 1 (R/W): Enable IrDA interface function 0 (R/W): Disable IrDA interface function Seiko Epson Corporation 13-14 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 171 The UART3_nBR register settings can be altered only when the UART3_nCTL.MODEN bit = 0. • Do not set the UART3_nBR.FMD[3:0] bits to a value other than 0 to 3 when the UART3_nMOD.BRDIV bit = 1. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 13-15 (Rev. 1.00)
Page 172 Bits 15–8 Reserved Bits 7–0 RXD[7:0] The receive data buffer can be read through these bits. The receive data buffer consists of a 2-byte FIFO, and older received data is read first. Seiko Epson Corporation 13-16 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 173 UART3_nINTF.PEIF bit: Parity error interrupt UART3_nINTF.OEIF bit: Overrun error interrupt UART3_nINTF.RB2FIF bit: Receive buffer two bytes full interrupt UART3_nINTF.RB1FIF bit: Receive buffer one byte full interrupt UART3_nINTF.TBEIF bit: Transmit buffer empty interrupt S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 13-17 (Rev. 1.00)
Page 174 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented channels are ineffective UART3 Ch.n Carrier Waveform Register Register name Bit name Initial Reset Remarks Seiko Epson Corporation 13-18 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 175 UART3_nCAWF 15–8 – 0x00 – – 7–0 CRPER[7:0] 0x00 Bits 15–8 Reserved Bits 7–0 CRPER[7:0] These bits set the carrier modulation output frequency. For more information, refer to “Carrier Modulation.” S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 13-19 (Rev. 1.00)
Page 176 Slave mode is capable of being operated in SLEEP mode allowing wake-up by an SPIA interrupt. Input pins can be pulled up/down with an internal resistor. Figure 14.1.1 shows the SPIA configuration. Table 14.1.1 SPIA Channel Configuration of S1C31D50 Item...
Page 177 SDIn #SPISS0 SPICLKn #SPISS1 #SPISS2 #SPISS External SPI master device External SPI slave devices SPICLK SPICLK #SPISS SPICLK Figure 14.2.2.2 Connections between SPIA in Slave Mode and External SPI Master Device Seiko Epson Corporation 14-2 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 178 SPIA_nMOD.PUEN bit to 1. Table 14.2.4.1 Pull-Up or Pull-Down of Input Pins Master mode Slave mode SDIn Pull-up Pull-up SPICLKn – SPIA_nMOD.CPOL bit = 1: Pull-up SPIA_nMOD.CPOL bit = 0: Pull-down #SPISSn – Pull-up S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 14-3 (Rev. 1.00)
Page 179 SPIA keeps operating using the clock supplied from the external SPI master even if all the internal clocks halt during SLEEP mode, so SPIA can receive data and can generate receive buffer full interrupts. Seiko Epson Corporation 14-4 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 180 Writing Dw[7:0] to the SPIA_nTXD register Loading Dr[7:0] to the SPIA_nRXD register Figure 14.4.1 Data Format Selection Using the SPIA_nMOD.LSBFST Bit (SPIA_nMOD.CHLN[3:0] bits = 0x7, SPIA_nMOD.CPOL bit = 0, SPIA_nMOD.CPHA bit = 0) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 14-5 (Rev. 1.00)
Page 181 SPI- CLKn pin, the clock output halts and the SPIA_nINTF.TENDIF bit is set to 1. At the same time SPIA issues an end-of-transmission interrupt request if the SPIA_nINTE.TENDIE bit = 1. Seiko Epson Corporation 14-6 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 182 SPIA_nTXD register Transmit data remained? Wait for an interrupt request (SPIA_nINTF.TBEIF = 1) Negate the slave select signal output from a general-purpose port Figure 14.5.2.2 Data Transmission Flowchart in Master Mode S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 14-7 (Rev. 1.00)
Page 183 Transfer destination SPIA_nTXD register address Control data dst_inc 0x3 (no increment) dst_size 0x1 (haflword) src_inc 0x1 (+2) src_size 0x1 (halfword) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation 14-8 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 184 Data (W) → SPIA_nTXD SPIA_nRXD → Data (R) Software operations SPIA_nRXD → Data (R) 1 (W) → SPIA_nINTF.TENDIF Figure 14.5.3.1 Example of Data Receiving Operations in Master Mode (SPIA_nMOD.CHLN[3:0] bits = 0x7) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 14-9 (Rev. 1.00)
Page 185 0x1 (halfword) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) Table 14.5.3.2 DMA Data Structure Configuration Example (for 16-bit Data Reception) Item Setting example Seiko Epson Corporation 14-10 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 186 Therefore, it is not necessary to write dummy data to the transmit data buffer when performing data reception only. Data transmission/reception can be performed even in SLEEP mode, it makes it possible to • S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 14-11 (Rev. 1.00)
Page 187 1. Wait for an end-of-transmission interrupt (SPIA_nINTF.TENDIF bit = 1). Or determine end of transfer via the received data. 2. Set the SPIA_nCTL.MODEN bit to 0 to disable the SPIA Ch.n operations. Seiko Epson Corporation 14-12 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 188 SPIA_nMOD register #SPISSn CPOL bit CPHA bit SPIA_nINTF.BSY SPICLKn SDOn SPICLKn SDOn SPIA_nINTF.TENDIF Writing data to the SPIA_nTXD register Figure 14.6.1 SPIA_nINTF.BSY and SPIA_nINTF.TENDIF Bit Set Timings (when SPIA_nMOD.CHLN[3:0] bits = 0x7) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 14-13 (Rev. 1.00)
Page 189 After a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the DMA control, refer to the “DMA Controller” chapter. Seiko Epson Corporation 14-14 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 190 SPICLKn frequency = 16-bit timer output frequency / 2 For more information, refer to “SPIA Operating Clock.” Bit 3 LSBFST This bit configures the data format (input/output permutation). 1 (R/W): LSB first S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 14-15 (Rev. 1.00)
Page 191 This bit sets the SPIA operating mode (master mode or slave mode). 1 (R/W): Master mode 0 (R/W): Slave mode Note: The SPIA_nMOD register settings can be altered only when the SPIA_nCTL.MODEN bit = 0. Seiko Epson Corporation 14-16 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 192 SPIA_ nINTF.RBFIF bit = 1 regardless of whether data is being input from the SDIn pin or not. Note that the upper bits that exceed the data bit length configured by the SPIA_nMOD.CHLN[3:0] bits become 0. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 14-17...
Page 193 The following shows the correspondence between the bit and interrupt: SPIA_nINTF.OEIF bit: Overrun error interrupt SPIA_nINTF.TENDIF bit: End-of-transmission interrupt SPIA_nINTF.RBFIF bit: Receive buffer full interrupt SPIA_nINTF.TBEIF bit: Transmit buffer empty interrupt Seiko Epson Corporation 14-18 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 194 (Ch.0– Ch.15) when a receive buffer full state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented channels are ineffective. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 14-19 (Rev. 1.00)
Page 195 Can issue a DMA transfer request when a receive buffer full, a transmit buffer empty, or a memory mapped access (32-bit read) occurs. Figure 15.1.1 shows the QSPI configuration. Table 15.1.1 QSPI Channel Configuration of S1C31D50 Item S1C31D50 Number of channels 1 channels (Ch.0)
Page 196 In this case, GPIO pins other than #QSPISSn can also be used as the slave select output ports to connect the QSPI to more than one external QSPI device. Figures 15.2.2.1 to 15.2.2.7 show connection diagrams between the QSPI in each mode and external QSPI devices. Seiko Epson Corporation 15-2 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 197 External dual-I/O master mode) SPI slave devices QSDIOn0 SDIO0 QSPICLKn SPICK #SPISS SDIO1 SDIO0 SPICK Figure 15.2.2.3 Connections between QSPI in Register Access Master Mode and External Dual-I/O SPI Slave Devices S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-3 (Rev. 1.00)
Page 198 External single-I/O S1C31 QSPI SPI master device (register access master mode) SPICK SPICK #SPISS SPICK Figure 15.2.2.5 Connections between QSPI in Slave Mode and External Single-I/O SPI (Legacy SPI) Master Device Seiko Epson Corporation 15-4 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 199 QSDIOn2 QSDIO2 QSDIOn1 QSDIO1 QSDIOn0 QSDIO0 QSPICLKn QSPICLK External QSPI slave devices #QSPISSn QSDIOn3 QSDIOn2 QSDIOn1 QSDIOn0 QSPICLKn Figure 15.2.2.7 Connections between QSPI in Slave Mode and External QSPI Master Device S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-5 (Rev. 1.00)
Page 200 QSPI_nMOD.PUEN bit to 1. Table 15.2.4.1 Pull-Up or Pull-Down of QSPI Pins Master mode Slave mode QSDIOn[3:0] Pull-up Pull-up QSPI_nMOD.CPOL bit = 1: Pull-up QSPICLKn – QSPI_nMOD.CPOL bit = 0: Pull-down #QSPISSn – Pull-up Seiko Epson Corporation 15-6 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 201 CLK_T16_m supply is not suspended and QSPI Ch.n will keep operating in a debug state. The QSPI in slave mode operates with the external SPI/QSPI master clock input from the QSPICLKn pin regard- less of whether the CPU is placed into debug state or normal operation state. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-7...
Page 202 Writing Dw[7:0] to the QSPI_nTXD register Figure 15.4.1 Data Format Selection for Single Transfer Mode Using the QSPI_nMOD.LSBFST Bit (QSPI_nMOD.TMOD[1:0] bits = 0x0, QSPI_nMOD.CHLN[3:0] bits = 0x7, QSPI_nMOD.CPOL bit = 0, QSPI_nMOD.CPHA bit = 0) Seiko Epson Corporation 15-8 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 203 Loading Dr[15:0] to the QSPI_nRXD register Figure 15.4.3 Data Format Selection for Quad Transfer Mode Using the QSPI_nMOD.LSBFST Bit (QSPI_nMOD.TMOD[1:0] bits = 0x2, QSPI_nMOD.CHLN[3:0] bits = 0x3, QSPI_nMOD.CPOL bit = 0, QSPI_nMOD.CPHA bit = 0) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-9...
Page 204 XIP termination confirmation bit(s) at the beginning of the cycle on one or more data lines. After that, negate the slave select signal. Figures 15.5.2.1 and 15.5.2.2 show Spansion S25FL128S Quad I/O Read command sequences as XIP operation examples. Seiko Epson Corporation 15-10 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 205 32-bit read. An 8 or 16-bit read at the sequential address after a 32-bit read allows zero- wait read if the desired data has already been fetched in the FIFO. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-11 (Rev.
Page 206 Configure the DMA controller and set the following QSPI control bits when using DMA transfer: Write 1 to the DMA transfer request enable bits in the QSPI_nTBEDMAEN, QSPI_nRBFDMAEN, and QSPI_nFRLDMAEN registers. (Enable DMA transfer requests) Seiko Epson Corporation 15-12 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 207 Data (W) → QSPI_nTXD Software operations Data (W) → QSPI_nTXD 1 (W) → QSPI_nINTF.TENDIF Figure 15.5.4.1 Example of Data Sending Operations in Master Mode (QSPI_nMOD.CHDL[3:0] bits = QSPI_nMOD.CHLN[3:0] bits = 0x3) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-13 (Rev. 1.00)
Page 208 Transfer destination QSPI_nTXD register address Control data dst_inc 0x3 (no increment) dst_size 0x1 (haflword) src_inc 0x1 (+2) src_size 0x1 (halfword) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation 15-14 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 209 TMOD[1:0] bits is received when the QSPI_nINTF.RBFIF bit is set to 1, the QSPI_nRXD register is overwritten with the newly received data and the previously received data is lost. In this case, the QSPI_nINTF.OEIF bit is set. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-15...
Page 210 = 1) or a general-purpose port Receive data remained? Negate the slave select signal output from the #QSPISSn pin (QSPI_nCTL.MSTSSO = 1) or a general-purpose port Figure 15.5.5.2 Data Reception Flowcharts in Register Access Master Mode Seiko Epson Corporation 15-16 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 211 The transfer source/destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on DMA, refer to the “DMA Controller” chapter. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-17...
Page 212 16. Disable both the DMA channels using the DMA controller register. 17. Negate the slave select signal by controlling the QSPI_nCTL.MSTSSO bit or the general-purpose output port (if necessary). 15.5.6. Data Reception in Memory Mapped Access Mode Seiko Epson Corporation 15-18 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 213 After that a new address cycle, dummy cycle, and data cycle are executed. The beginning and the end of each address, dummy, or data cycle take a couple of HCLK clocks for handshaking. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-19...
Page 214 QSPI_nMOD register Data cycle 3 Dummy cycle Data cycle 1 (prefetching) (prefetching) CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.1 Data Receiving Operation in Memory Mapped Access Mode - First 32-bit Read Seiko Epson Corporation 15-20 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 215 HRDATA fifo_read_level Data cycle Data cycle QSPI_nMOD register (for n+8) (prefetching)) CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.2 Data Receiving Operation in Memory Mapped Access Mode - 32-bit Sequential Read S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-21 (Rev. 1.00)
Page 216 Figure 15.5.6.3 Data Receiving Operation in Memory Mapped Access Mode - 32-bit Non-Sequential Read Data receiving operations (8/16-bit read) The 8 and 16-bit read operations are the same as the 32-bit read operation except that data are not prefetched into the FIFO. Seiko Epson Corporation 15-22 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 217 HADDR HTRANS HSIZE HREADY HRDATA QSPI_nMOD register Data cycle Dummy cycle CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.4 Data Receiving Operation in Memory Mapped Access Mode - First 8/16-bit Read S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-23 (Rev. 1.00)
Page 218 HCLK HSEL HADDR HTRANS HSIZE HREADY HRDATA Data cycle QSPI_nMOD register CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.5 Data Receiving Operation in Memory Mapped Access Mode - 8/16-bit Sequential Read Seiko Epson Corporation 15-24 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 219 Dummy cycle Data cycle Address cycle (low-order 16 bits) QSPI_ MOD register CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.6 Data Receiving Operation in Memory Mapped Access Mode - 8/16-bit Non-Sequential Read S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-25 (Rev. 1.00)
Page 220 The transfer source/destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation 15-26 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 221 1. Wait for an end-of-transmission interrupt (QSPI_nINTF.TENDIF bit = 1). 2. Set the QSPI_nCTL.MODEN bit to 0 to disable the QSPI Ch.n operations. 3. Stop the 16-bit timer to disable the clock supply to QSPI Ch.n. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-27...
Page 222 When the clock for the first bit is input from the QSPICLKn pin, QSPI starts sending the data currently stored in the shift register even if the QSPI_nINTF.TBEIF bit is set to 1. Seiko Epson Corporation 15-28 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 223 1. Wait for an end-of-transmission interrupt (QSPI_nINTF.TENDIF bit = 1). Or determine end of transfer via the received data. 2. Set the QSPI_nCTL.MODEN bit to 0 to disable the QSPI Ch.n operations. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-29 (Rev. 1.00)
Page 224 The QSPI_nINTF register also contains the BSY and MMABSY bits that indicate the QSPI operating status in register access and memory mapped access modes, respectively. Figure 15.6.1 shows the QSPI_nINTF.BSY, QSPI_ nINTF.MMABSY and QSPI_nINTF.TENDIF bit set timings. Seiko Epson Corporation 15-30 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 225 CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] QSPI_nINTF.MMABSY 1 (W) → QSPI_nMMACFG2.MMAEN 0 (W) → QSPI_nMMACFG2.MMAEN Figure 15.6.1 QSPI_nINTF.BSY, QSPI_nINTF.MMABSY, and QSPI_nINTF.TENDIF Bit Set Timings (when QSPI_nMOD.CHDL[3:0] bits = QSPI_nMOD.CHLN[3:0] bits = 0x3) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-31 (Rev. 1.00)
Page 226 After a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the DMA control, refer to the “DMA Controller” chapter. Seiko Epson Corporation 15-32 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 227 These bits must be set to a value smaller than or equal to the QSPI_nMOD.CHLN[3:0] bit setting. Note: When using the QSPI in slave mode, the QSPI_nMOD.CHDL[3:0] bits should be set to the same value as the QSPI_nMOD.CHLN[3:0] bits. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-33 (Rev. 1.00)
Page 228 0 (R/W): QSPICLKn frequency = 16-bit timer output frequency / 2 For more information, refer to “QSPI Operating Clock.” Bit 3 LSBFST This bit configures the data format (input/output permutation). 1 (R/W): LSB first 0 (R/W): MSB first Bit 2 CPHA Seiko Epson Corporation 15-34 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 229 If the QSPI_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the QSPI_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the QSPI_nCTL.SFTRST bit as well. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-35...
Page 230 QSPI_nINTF.RBFIF bit = 1 regardless of whether data is being input from the QSDIOn pin or not. Note that the upper bits that exceed the data bit length configured by the QSPI_nMOD.CHLN[3:0] bits become 0. Seiko Epson Corporation 15-36 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 231 The following shows the correspondence between the bit and interrupt: QSPI_nINTF.OEIF bit: Overrun error interrupt QSPI_nINTF.TENDIF bit: End-of-transmission interrupt QSPI_nINTF.RBFIF bit: Receive buffer full interrupt QSPI_nINTF.TBEIF bit: Transmit buffer empty interrupt S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-37 (Rev. 1.00)
Page 232 (Ch.0– Ch.15) when a receive buffer full state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented channels are ineffective. Seiko Epson Corporation 15-38 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 233 11 clocks 10 clocks 9 clocks 8 clocks 7 clocks 6 clocks 5 clocks 4 clocks 3 clocks 2 clocks 1 clock Note: These bits specify a number of system clocks. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-39 (Rev. 1.00)
Page 234 RMADR = N 0x N 00000 Memory mapped access area Offset = N 0x000fffff RMADR = 0 0x00000000 (N = QSPI_nRMADRH.RMADR[31:20] setting value) Figure 15.8.1 External Flash Memory Remapping Bits 3–0 Reserved Seiko Epson Corporation 15-40 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 235 7 clocks 6 clocks 5 clocks 4 clocks 3 clocks 2 clocks 1 clock These bits must be set to a value smaller than or equal to the QSPI_nMMACFG2.DUMLN[3:0] bit setting. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-41 (Rev. 1.00)
Page 236 16 clocks 15 clocks 14 clocks 13 clocks 12 clocks 11 clocks 10 clocks 9 clocks 8 clocks 7 clocks 6 clocks 5 clocks 4 clocks 3 clocks 2 clocks Setting prohibited Seiko Epson Corporation 15-42 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 237 Flash memory that has been configured using the QSPI_nMB.XIPEXT[7:0] bits. Note: Slave mode does not support memory mapped access mode, therefore, setting the QSPI_nMMACFG2.MMAEN bit to 1 does not take effect when the QSPI_nMOD.MST bit = 0. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 15-43 (Rev. 1.00)
Page 238 In memory mapped access mode, the mode byte is always output from the LSB first. When using a Flash memory that expects the mode byte to be output from the MSB first, write the mode byte to this register in reverse bit order. Seiko Epson Corporation 15-44 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 239 Can generate receive buffer full, transmit buffer empty, and other interrupts. • Can issue a DMA transfer request when a receive buffer full or a transmit buffer empty occurs. Figure 16.1.1 shows the I2C configuration. Table 16.1.1 I2C Channel Configuration of S1C31D50 Item S1C31D50 Number of channels 3 channels (Ch.0 ,Ch.1 and Ch.2)
Page 240 The internal pull-up resistors for the I/O ports cannot be used for pulling up SDA and SCL. • When the I2C is set into master mode, no other master device can be connected to the I • bus. • Seiko Epson Corporation 16-2 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 241 In slave mode, the I2C Ch.n operates with the external I C master clock input from the SCLn pin regardless of whether the CPU is placed into debug state or normal operation state. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 16-3...
Page 242 This extends the clock to control data transfer during the SCL signal rising/falling period and clock stretching period in which SCL is fixed at low by a slave device. Seiko Epson Corporation 16-4 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 243 I2C_nINTF.NACKIF bit. 8. (When DMA is not used) Repeat Steps 5 and 6 until the end of transmit data. 9. Issue a STOP condition by setting the I2C_nCTL.TXSTOP bit to 1. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 16-5...
Page 244 S: START condition, Sr: Repeated START condition, P: STOP condition, STOPIF = 1 A: ACK, A: NACK, Saddr/W: Slave address + W(0), Data n: 8-bit data Figure 16.4.2.1 Example of Data Sending Operations in Master Mode Seiko Epson Corporation 16-6 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 245 I2C_nTXD register address Control data dst_inc 0x3 (no increment) dst_size 0x0 (byte) src_inc 0x0 (+1) src_size 0x0 (byte) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 16-7 (Rev. 1.00)
Page 246 The I2C Ch.n pulls down SCL to low and enters standby state until data is read out from the I2C_ nRXD register. This reading triggers the I2C Ch.n to start subsequent data reception. Seiko Epson Corporation 16-8 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 247 S: START condition, Sr: Repeated START condition, P: STOP condition, A: ACK, A: NACK, Saddr/W: Slave address + R(1), Data n: 8-bit data Figure 16.4.3.1 Example of Data Receiving Operations in Master Mode S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 16-9...
Page 248 Control data dst_inc 0x0 (+1) dst_size 0x0 (byte) src_inc 0x3 (no increment) src_size 0x0 (byte) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of receive data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation 16-10 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 249 Clear the I2C_nINTF.STARTIF bit by writing 1 after the interrupt has occurred. 9. Write the first address to the I2C_nTXD.TXD[7:1] bits and 1 that represents READ as the data transfer direction to the I2C_nTXD.TXD0 bit. 10. Perform data reception. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 16-11 (Rev. 1.00)
Page 250 I2C_nOADR.OADR[6:0] bits (when the I2C_nMOD.OADR10 bit = 0 (7-bit address mode)) or the I2C_nOADR.OADR[9:0] bits (when the I2C_nMOD.OADR10 bit = 1 (10-bit address mode)), the I2C_nINTF.STARTIF bit and the I2C_nINTF.BSY bit are both set to 1. The I2C Ch.n sets the I2C_nINTF.TR Seiko Epson Corporation 16-12 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 251 Data transmission Wait for an interrupt request (I2C_nINTF.TBEIF = 1 or I2C_nINTF.NACKIF = 1) I2C_nINTF.NACKIF = 1 ? Write data to the I2C_nTXD register Figure 16.4.5.2 Slave Mode Data Transmission Flowchart S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 16-13 (Rev. 1.00)
Page 252 I2C_nCTL.TXNACK bit before the data reception is completed. The I2C_nCTL.TXNACK bit is automatically cleared to 0 after a NACK has been sent. STOP/repeated START condition detection It is the same as the data transmission in slave mode. Seiko Epson Corporation 16-14 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 253 See Figure 16.4.4.1 for the 10-bit address configuration. 10-bit address receiving operations After a START condition is issued, the master sends the first address that includes the two high-order S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 16-15 (Rev. 1.00)
Page 254 If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is regarded as an automatic bus clearing failure. In this case, the I2C Ch.n clears the I2C_nCTL.TXSTART bit to 0 and sets both the I2C_nINTF. ERRIF and I2C_nINTF.STARTIF bits to 1. Seiko Epson Corporation 16-16 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 255 4 <Master mode only> When 1 is written to the I2C_nCTL. I2C_nINTF.ERRIF = 1 TXSTART bit while the I2C_nINTF.BSY bit = 0 (Refer to “Au- Automatic bus clearing I2C_nCTL.TXSTART = 0 tomatic Bus Clearing Operation.”) failure I2C_nINTF.STARTIF = 1 S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 16-17 (Rev. 1.00)
Page 256 CPU core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation 16-18 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 257 (BRT + 3) × 3 fCLK_I2Cn TXSTOP = 1 TXSTOP = 0 RXD[7:0] read (during reception) STOPIF = 1 Slave mode BSY = 0 STOPIF = 1 Figure 16.5.1 START/STOP Condition Interrupt Timings S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 16-19 (Rev. 1.00)
Page 258 After a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the DMA control, refer to the “DMA Controller” chapter. Seiko Epson Corporation 16-20 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 259 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Note: The I2C_nCLK register settings can be altered only when the I2C_nCTL.MODEN bit = 0. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 16-21 (Rev. 1.00)
Page 260 = 1), or the I2C_nOADR.OADR[6:0] bits are effective in 7-bit address mode (I2C_nMOD.OADR10 bit = 0). Note: The I2C_nOADR register settings can be altered only when the I2C_nCTL.MODEN bit = 0. Seiko Epson Corporation 16-22 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 261 0 (R): Software reset has finished. (During normal operation) Setting this bit resets the I2C transmit/receive control circuit and interrupt flags. This bit is automatically cleared after the reset processing has finished. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 16-23 (Rev. 1.00)
Page 262 Cleared by writing to the I2C_nTXD register. Bits 15–13 Reserved Bit 12 SDALOW This bit indicates that SDA is set to low level. 1 (R): SDA = Low level 0 (R): SDA = High level Seiko Epson Corporation 16-24 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 263 I2C_nINTF.NACKIF bit: NACK reception interrupt I2C_nINTF.STOPIF bit: STOP condition interrupt I2C_nINTF.STARTIF bit: START condition interrupt I2C_nINTF.ERRIF bit: Error detection interrupt I2C_nINTF.RBFIF bit: Receive buffer full interrupt I2C_nINTF.TBEIF bit: Transmit buffer empty interrupt S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 16-25 (Rev. 1.00)
Page 264 (Ch.0–Ch.15) when a transmit buffer empty state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented channels are ineffective. Seiko Epson Corporation 16-26 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 265 (Ch.0–Ch.15) when a receive buffer full state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented channels are ineffective. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 16-27 (Rev. 1.00)
Page 266 The capture circuit captures counter values using external/software trigger signals and generates interrupts or DMA requests. (Can be used to measure external event periods/cycles.) Figure 17.1.1 shows the T16B configuration. Table 17.1.1 T16B Channel Configuration of S1C31D50 Item S1C31D50 Number of channels 2 channels (Ch.0 and Ch.1)
Page 267 If the port is shared with the T16B pin and other functions, the T16B input/output function must be assigned to the port before activating T16B. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation 17-2 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 268 Figure 17.3.4.1 Count Timing (During Count Up Operation) Note: When running the counter using the event counter clock, two dummy clocks must be input before the first counting up/down can be performed. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 17-3 (Rev. 1.00)
Page 269 7. Set the following T16B_nCTL register bits: T16B_nCTL.CNTMD[1:0] bits (Select count up/down operation) T16B_nCTL.ONEST bit (Select one-shot/repeat operation) Set the T16B_nCTL.PRESET bit to 1. (Reset counter) Set the T16B_nCTL.RUN bit to 1. (Start counting) Seiko Epson Corporation 17-4 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 270 1 while the counter is running or 0 while the counter is idle. The current count direction can also be checked using the T16B_nCS.UP_DOWN bit. The T16B_nCS.UP_ DOWN bit is set to 1 during count up operation or 0 during count down operation. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 17-5...
Page 271 PRESET = 1 RUN = 1 RUN = 1 0xffff Counter MAX value 0x0000 Time RUN = 0 RUN = 0 Figure 17.4.2.1 Operations in Repeat Up Count and One-shot Up Count Modes Seiko Epson Corporation 17-6 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 272 Data (W) → MC[15:0] RUN = 1 0xffff MAX value Counter 0x0000 Time RUN = 0 RUN = 0 Figure 17.4.2.2 Operations in Repeat Down Count and One-shot Down Count Modes S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 17-7 (Rev. 1.00)
Page 273 Set the T16B_nCCCTLm.CCMD bit to 0 to set the comparator/capture circuit m to comparator mode or 1 to set it to capture mode. Seiko Epson Corporation 17-8 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 274 Compare period during counting down 0x0000 Time CNTMAXIF = 1 CNTZEROIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Figure 17.4.3.1 Operation Examples in Comparator Mode S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 17-9 (Rev. 1.00)
Page 275 (T16B_nMC register) Compare period Counter Compare buffer value 0x0000 Time CNTMAXIF = 1 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 17-10 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 276 (T16B_nMC register) Compare period Counter Compare buffer value 0x0000 Time CNTMAXIF = 1 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 17-11 (Rev. 1.00)
Page 277 (T16B_nMC register) Counter Compare buffer value Compare period 0x0000 Time CNTZEROIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 17-12 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 278 (T16B_nMC register) Counter Compare buffer value Compare period 0x0000 Time CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 17-13 (Rev. 1.00)
Page 279 Compare period during counting down 0x0000 Time CNTMAXIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 17-14 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 280 DMA channel must be enabled to start a DMA transfer in advance so that the setting data will be transferred to the T16B_nCCRm or T16B_nMC register. For more information on DMA, refer to the “DMA Controller” chapter. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 17-15...
Page 281 CMPCAPmIF = 0 CMPCAPmIF = 1 CMPCAPmIF = 1 CAPOWmIF = 1 Counter value CC[15:0] Counter value CC[15:0] Counter value CC[15:0] Figure 17.4.3.3 Operations in Capture Mode (Example in One-shot Up Count Mode) Seiko Epson Corporation 17-16 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 282 Transfer destination Memory address to which the last capture data is stored Control data dst_inc 0x1 (+2) dst_size 0x1 (haflword) src_inc 0x3 (no increment) src_size 0x1 (halfword) R_power 0x0 (arbitrated for every transfer) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 17-17 (Rev. 1.00)
Page 283 The TOUT signal polarity (active level) can be set using the T16B_nCCCTLm.TOUTINV bit. It is set to active high by setting the T16B_nCCCTLm.TOUTINV bit to 0 and active low by setting to 1. Figures 17.4.4.2 and 17.4.4.3 show the TOUT output waveforms. Seiko Epson Corporation 17-18 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 284 Software control mode (0x0) Set mode (0x1) Toggle/reset mode (0x2) Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 17-19 (Rev. 1.00)
Page 285 Toggle/reset mode (0x2) Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Figure 17.4.4.2 TOUT Output Waveform (T16B_nCCCTLm.TOUTMT bit = 0) Seiko Epson Corporation 17-20 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 286 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 17-21 (Rev. 1.00)
Page 287 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 17-22 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 288 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Figure 17.4.4.3 TOUT Output Waveform (T16B_nCCCTL0.TOUTMT bit = 1, T16B_nCCCTL1.TOUTMT bit = 0) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 17-23 (Rev. 1.00)
Page 289 After a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the DMA control, refer to the “DMA Controller” chapter. Seiko Epson Corporation 17-24 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 290 1/128 1/128 1/128 1/64 1/64 1/64 1/32 1/32 1/32 1/16 1/16 1/16 (Note) The oscillator circuits/external inputs that are not supported in this IC cannot be selected as the clock source. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 17-25 (Rev. 1.00)
Page 291 1 (R): Resetting in progress 0 (R): Resetting finished or normal operation In up mode or up/down mode, the counter is cleared to 0x0000 by writing 1 to this bit. In Seiko Epson Corporation 17-26 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 292 T16B_nMC.MC[15:0] bits. If the T16B_nCTL.MODEN bit = 0 when writing to the T16B_nMC.MC[15:0] bits, set the T16B_nCTL.MODEN bit to 1 until the T16B_nCS.BSY bit is set to 0 from 1. Do not set the T16B_nMC.MC[15:0] bits to 0x0000. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 17-27 (Rev. 1.00)
Page 293 This bit indicates the currently set count direction. 1 (R): Count up 0 (R): Count down Bit 0 This bit indicates the counter operating status. 1 (R): Running 0 (R): Idle Seiko Epson Corporation 17-28 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 294 T16B_nINTF.CAPOW0IF bit: Capture 0 overwrite interrupt T16B_nINTF.CMPCAP0IF bit: Compare/capture 0 interrupt T16B_nINTF.CNTMAXIF bit: Counter MAX interrupt T16B_nINTF.CNTZEROIF bit: Counter zero interrupt Note: The configuration of the T16B_nINTF.CAPOWmIF and T16B_nINTF.CMPCAPmIF bits de- S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 17-29 (Rev. 1.00)
Page 295 T16B_nINTE.CNTMAXIE bit: Counter MAX interrupt T16B_nINTE.CNTZEROIE bit: Counter zero interrupt Notes: The configuration of the T16B_nINTE.CAPOWmIE and T16B_nINTE.CMPCAPmIE bits depends on the model. The bits corresponding to the comparator/capture circuits that do Seiko Epson Corporation 17-30 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 296 Up/down mode Bits 11–10 CAPIS[1:0] These bits select the trigger signal for capturing (see Table 17.7.4). The T16B_nCCCTLm.CAPIS[1:0] bits are control bits for capture mode and are ineffective in comparator mode. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 17-31 (Rev. 1.00)
Page 297 These bits configure how the TOUTnm signal waveform is changed by the comparator MATCH and counter MAX/ZERO signals. The T16B_nCCCTLm.TOUTMD[2:0] bits are control bits for comparator mode and are ineffective in capture mode. Seiko Epson Corporation 17-32 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 298 T h e s i g n a l b e c o m e s in a c t i v e by t h e M AT C H m o r MATCHm+1 signal. TOUTnm+ The signal becomes inactive by the MATCHm+1 or MATCHm signal. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 17-33 (Rev. 1.00)
Page 299 CCMD This bit selects the operating mode of the comparator/capture circuit m. 1 (R/W): Capture mode (T16B_nCCRm register = capture register) 0 (R/W): Comparator mode (T16B_nCCRm register = compare data register) Seiko Epson Corporation 17-34 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 300 In capture mode, this register is configured as the capture register and the counter value captured by the capture trigger signal is loaded. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 17-35 (Rev. 1.00)
Page 301 (Ch.0–Ch.15) when the counter value reaches the compare data or is captured. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented channels are ineffective. Seiko Epson Corporation 17-36 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 302 Output signal inverting function supporting various formats. • EL lamp drive waveform can be generated for an application example. Figure 18.1.1 shows the REMC3 configuration. Table 18.1.1 REMC3 Channel Configuration of S1C31D50 Item S1C31D50 Number of channels 1 transmitter channel...
Page 303 SLEEP mode and REMC3 stops with the register settings maintained at those before entering SLEEP mode. After the CPU returns to normal mode, CLK_REMC3 is supplied and the REMC3 operation resumes. Seiko Epson Corporation 18-2 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 304 Terminating data transmission The following shows a procedure to terminate data transmission. 1. Wait for a compare DB interrupt (REMC3INTF.DBIF bit = 1). 2. Set the REMC3DBCTL.PRUN bit to 0. (Stop counting) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 18-3 (Rev. 1.00)
Page 305 REMC3CARR.CRDTY[7:0] bits, the carrier signal waveform is inverted. When the counter value is matched with the REMC3CARR.CRPER[7:0] bits, the carrier signal waveform is inverted and the counter is reset to 0x00. Data signal Seiko Epson Corporation 18-4 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 306 REMC3DBCTL.PRUN bit. When the counter is set to one-shot mode (REMC3DBCTL.TRMD bit = 1), the counter stops automatically when the counter value is matched with the REMC3DBLEN.DBLEN[15:0] bit-setting value. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 18-5...
Page 307 (REMC3INTF. APLENBSY bit and REMC3INTF.DBLENBSY bit) become effective. The flag is set to 1 when the setting value is written to the register and cleared to 0 when the written value is transferred to the buffer. Seiko Epson Corporation 18-6 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 308 The REMO and CLPLS signals are output from the respective pins while the REMC3DBCTL.PRUN bit = 1. The difference between the setting values of the REMC3DBLEN.DBLEN[15:0] bits and REMC3APLEN.APLEN[15:0] bits becomes the CLPLS pulse width (high period). S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 18-7...
Page 309 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Note: The REMC3CLK register settings can be altered only when the REMC3DBCTL.MODEN bit = Seiko Epson Corporation 18-8 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 310 For more information, refer to “Continuous Data Transmission and Compare Buffers.” Note: The REMC3DBCTL.BUFEN bit must be set to 0 when setting the data signal duty and cycle for the first time. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 18-9 (Rev. 1.00)
Page 311 REMC3APLEN. APLEN[15:0] bit-setting value. The data signal duty ratio is determined by this setting and the REMC3DBLEN.DBLEN[15:0] bit-setting. (See Figure 18.4.3.3.) Before this register can be rewritten, the REMC3DBCTL.MODEN bit must be set to 1. Seiko Epson Corporation 18-10 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 312 The following shows the correspondence between the bit and interrupt: REMC3INTF.DBIF bit: Compare DB interruptREMC3INTF.APIF bit: Compare AP interrupt. These interrupt flags are also cleared to 0 when 1 is written to the REMC3DBCTL.REMCRST bit. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 18-11...
Page 313 This bit enables carrier modulation. 1 (R/W): Enable carrier modulation 0 (R/W): Disable carrier modulation (output data signal only) Note: When carrier modulation is disabled, the REMC3DBCTL.REMOINV bit should be set to 0. Seiko Epson Corporation 18-12 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 314 Can generate conversion completion and overwrite error interrupts. • Can issue a DMA transfer request when a conversion has completed. Figure 19.1.1 shows the ADC12A configuration. Table 19.1.1 ADC12A Configuration of S1C31D50 Item S1C31D50 Number of channels 1 channel (Ch.0) Number of analog signal inputs per channel Ch.0: 8 inputs (ADIN00–ADIN07)
Page 315 When the CLK_T16_k supply stops during A/D conversion (e.g., when the CPU enters SLEEP or DEBUG mode), correct conversion results cannot be obtained even if the clock supply is resumed after that. In this case, perform A/D conversion again. Seiko Epson Corporation 19-2 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 316 Set the interrupt enable bits in the ADC12A_nINTE register to 1. (Enable interrupts) 7. Configure the DMA controller and set the following ADC12A control bit when using DMA transfer: Write 1 to the DMA transfer request enable bit in the ADC12A_nDMAEN register. (Enable DMA S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 19-3...
Page 317 The ADC12A stops operating after the A/D conversion currently being executed has completed. The ADC12A_nCTL.ADST bit must be cleared by writing 0 even if A/D conversion is completed and automatically stopped. Seiko Epson Corporation 19-4 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 318 Sampling Sampling Sampling A/D conversion operations Conversion Conversion Conversion ADINn2 ADINn2 ADINn2 ADINn2 ADINn2 ADINn2 ADC12A_nADD.ADD[15:0] ADINn2 ADINn3 ADINn4 conversion result conversion result conversion result Cleared ADC12A_nINTF.AD2CIF Overwrite ADC12A_nINTF.AD3CIF ADC12A_nINTF.AD4CIF ADC12A_nINTF.OVIF S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 19-5 (Rev. 1.00)
Page 319 Transfer destination Memory address to which the last A/D converted data is stored Control data dst_inc 0x1 (+2) dst_size 0x1 (haflword) src_inc 0x3 (no increment) src_size 0x1 (halfword) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation 19-6 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 320 After a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the DMA control, refer to the “DMA Controller” chapter. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 19-7...
Page 321 The data written to the ADC12A_nCTL.ADST bit must be retained for one or more CLK_T16_k clock cycles when 1 is written or two or more CLK_T16_k clock cycles when 0 is written. Bit 0 MODEN Seiko Epson Corporation 19-8 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 322 This does not affect the conversion results. ADC12A_nADD.ADD[15:0] bits Left justified (ADC12A_nTRG.STMD bit = 1) (MSB) 12-bit conversion result (LSB) Right justified (ADC12A_nTRG.STMD bit = 0) (MSB) 12-bit conversion result (LSB) Figure 19.7.1 Conversion Data Alignment S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 19-9 (Rev. 1.00)
Page 323 These bits set the analog input signal sampling time. Table 19.7.3 Sampling Time Settings Sampling time ADC12A_nTRG.SMPCLK[2:0] bits (Number of CLK_T16_k cycles) 11 cycles 10 cycles 9 cycles 8 cycles 7 cycles 6 cycles 5 cycles 4 cycles Seiko Epson Corporation 19-10 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 324 0 (W): Ineffective The following shows the correspondence between the bit and interrupt: ADC12A_nINTF.OVIF bit: A/D conversion result overwrite error interrupt ADC12A_nINTF.ADmCIF bit: Analog input signal m A/D conversion completion interrupt S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 19-11 (Rev. 1.00)
Page 325 ADC12A Ch.n Result Register Register name Bit name Initial Reset Remarks ADC12A_nADD 15–0 ADD[15:0] 0x0000 – Bits 15–0 ADD[15:0] The A/D conversion results are set to these bits. Seiko Epson Corporation 19-12 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 326 Can generate reference oscillation completion, sensor (A and B) oscillation completion, measurement counter overflow error, and time base counter overflow error interrupts. Figure 20.1.1 shows the RFC configuration. Table 20.1.1 RFC Channel Configuration of S1C31D50 Item S1C31D50 Number of channels 1 channel (Ch.0)
Page 327 Figure 20.2.2.1 Connection Example in Resistive Sensor DC Oscillation Mode SENBn SEN1 SENAn REFn RFINn : Reference resistor : Resistive sensor (AC bias) SEN1 : Reference capacitor S1C31 RFC Figure 21.2.2.2 Connection Example in Resistive Sensor AC Oscillation Mode Seiko Epson Corporation 20-2 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 328 TCCLK supply is suspended, the output pin and registers retain the status before DEBUG mode was entered. If the RFC_nCLK.DBRUN bit = 1, the TCCLK supply is not suspended and the RFC will keep operating in DEBUG mode. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 20-3...
Page 329 The counter values should be corrected via software after the reference and sensor oscillations are completed according to the sensor characteristics to determine the value being currently detected by the sensor. Time base counter (TC) Seiko Epson Corporation 20-4 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 330 RFC_nINTF.OVMCIF bit and terminate measurement as an error or retry after altering the measurement counter initial value. 9. Read the RFC_nMCH and RFC_nMCL registers (measurement counter) and correct the results depending on the sensor to obtain the detected value. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 20-5 (Rev. 1.00)
Page 331 TC[23:0] = 0x000000 SREF = 1 SSENx = 1 ESENxIF = 1, SSENx = 0 Start sensor oscillation Start reference oscillation Software settings Figure 20.4.4.1 Counter Operations During Reference/Sensor Oscillation Forced termination Seiko Epson Corporation 20-6 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 332 RFC_nCTL.RFCLKMD bit to 1 changes the output clock to the divided-by-two RFCLK clock. Writing 1 Writing 0 RFC_nCTL.CONEN RFC_nTRG.SSENA, SSENB, SREF RFINn pin RFCLKOn pin (RFC_nCTL.RFCLKMD = 0) RFCLKOn pin (RFC_nCTL.RFCLKMD = 1) Figure 20.4.5.1 CR Oscillation Clock (RFCLK) Waveform S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 20-7 (Rev. 1.00)
Page 333 CPU core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation 20-8 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 334 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Note: The RFC_nCLK register settings can be altered only when the RFC_nCTL.MODEN bit = 0. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 20-9 (Rev. 1.00)
Page 335 0 (R/W): Disable RFC operations (The operating clock is stopped.) Note: If the RFC_nCTL.MODEN bit is altered from 1 to 0 during R/F conversion, the counter value being converted cannot be guaranteed. R/F conversion cannot be resumed. Seiko Epson Corporation 20-10 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 336 SSENB bit to start oscillation, be sure to avoid having more than one bit set to 1. • Be sure to clear the interrupt flags (RFC_nINTF.EREFIF bit, RFC_nINTF.ESENAIF bit, RFC_nINTF.ESENBIF bit, RFC_nINTF.OVMCIF bit, and RFC_nINTF.OVTCIF bit) before starting oscillation using this register. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 20-11 (Rev. 1.00)
Page 337 The time base counter must be set from the low-order value (RFC_nTCL.TC[15:0] bits) first when data is set using a 16-bit access instruction. The counter may not be set to the correct value if the high-order value (RFC_nTCH.TC[23:16] bits) is written first. Seiko Epson Corporation 20-12 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 338 Time base counter overflow error interrupt RFC_nINTE.OVMCIE bit: Measurement counter overflow error interrupt RFC_nINTE.ESENBIE bit: Sensor B oscillation completion interrupt RFC_nINTE.ESENAIE bit: Sensor A oscillation completion interrupt RFC_nINTE.EREFIE bit: Reference oscillation completion interrupt S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 20-13 (Rev. 1.00)
Page 339 “Memory Check” function By only command set, HW Processor works by itself. (not required CPU resource) The features of the Sound Play are listed below. • EPSON High quality & High compress algorithm Sampling Frequency: 15.625kHz Bitrate: 16/24/32/40 kbps •...
Page 340 Enable Control PORT pull-down(if AMP Enable is Sleep) Please check AMP Enable specification 510Ω 510Ω Enable SDACOUT_N S1C31D50 39uF 39uF Audio AMP 510Ω 510Ω SDACOUT_P 39uF 39uF Figure 21.2.2.2 Differential Mode Connection Seiko Epson Corporation 21-2 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 341 Set ROMADDR Set KEYCODE Set INTMASK” HWLIBEN = 1 HWLIBEN = 1 in HWLIB Control Register in HWLIB Control Register “Sound Play” Function “Memory Check” Function Figure 21.3.1 Function Configuration Flow S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-3 (Rev. 1.00)
Page 342 Sound Play Configuration Sound Play Command Control Sound DAC & External Audio AMP Setting(Close) - Sound DAC Control - External AMP Enable Control Figure 21.4.1.1 Standard “Sound Play Function” Mode Flow Seiko Epson Corporation 21-4 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 343 Set the SDAC_0.DAT register to 0x0000. Set the SDAC_0.CLK register to 0x0102. Disable the Audio AMP. (if necessary) Note Regarding external Audio AMP control(wake-up time, enable control etc), please check and follow Audio AMP specification. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-5 (Rev. 1.00)
Page 344 After setting “Mute” command, the state is moved to “sp_state_mute”. After setting “Release Mute” command, the state is moved to “sp_state_play”, or after finishing the play or setting “Sound Stop” command, the state is moved to “sp_state_idle”. Figure 21.4.4.1 shows Sound Play State Transition. Seiko Epson Corporation 21-6 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 345 Set FUNCTION to “Sound Play” Control Register HWPEN = 1, in HW Processor Control Register sp_state_init Sound Play Function sp_state_idle Command:”Pause” Command”:Mute” sp_state_pause sp_state_mute sp_state_play Command:”Release Mute” Command:”Release Pause” Figure 21.4.4.1 Sound Play State Transition S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-7 (Rev. 1.00)
Page 346 Cortex Enable HW Processor Enable HWPCTL.HWPEN HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 Check STATE_0 = "sp_state_idle" Check STATE_1 = "sp_state_idle" Sound Play Function Figure 21.4.5.1 Sound Play Configuration Flow Seiko Epson Corporation 21-8 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 347 HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 Check STATE_x = "sp_state_play", if necessary HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 Check STATE_x = "sp_state_idle" Figure 21.4.6.1 “Sound Start” Command Flow S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-9 (Rev. 1.00)
Page 348 Sound Play Function Registers(See Table 21.4.14.1) Cortex Set HW Processor Set HWPCMDTRG.HWP0TRG HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 Check STATE_x = "sp_state_idle" Figure 21.4.7.3 “Sound Stop” Command Flow. Seiko Epson Corporation 21-10 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 349 “MUTE after current phrase” command MUTE here The output sound is “the temperature is set at” Figure 21.4.8.2 Mute timing after “Mute after current phrase” Command Figure 21.4.8.3 shows “Mute” command flow. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-11 (Rev. 1.00)
Page 350 Even release muting at big sample value, smooth function avoids the noise. Figure 21.4.9.1 shows smooth function after “Release Mute” command. Smooth function Release Mute command Figure 21.4.9.1 Smooth Function after “Release Mute” Command Figure 21.4.9.2 shows “Release Mute” command flow. Seiko Epson Corporation 21-12 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 351 Sound Play Function Registers(See Table 21.4.14.1) Cortex Set HW Processor Set HWPCMDTRG.HWP0TRG HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 check STATE_x = "sp_state_play", if necessary Figure 21.4.9.2 “Release Mute” Command Flow. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-13 (Rev. 1.00)
Page 352 Sound Play Function Registers(See Table 21.4.14.1) Cortex Set HW Processor Set HWPCMDTRG.HWP0TRG HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 check STATE_x = "sp_state_pause", if necessary Figure 21.4.10.3 “Pause” Command Flow. Seiko Epson Corporation 21-14 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 353 Sound Play Function Registers(See Table 21.4.14.1) Cortex Set HW Processor Set HWPCMDTRG.HWP0TRG HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 check STATE_x = "sp_state_play", if necessary Figure 21.4.11.2 “Release Pause” command flow. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-15 (Rev. 1.00)
Page 354 When this bit is enabled, the interrupt generated when the state moves to “sp_state_mute” is masked. Figure 21.4.13.1 shows “Sound Play Interrupt Masking” flow. Wait STATE_x = "sp_state_idle" Wait STATUS.READY = sp_status_ready Set INTMASK to 0x000x Figure 21.4.13.1 “Sound Play Interrupt Masking” Flow. Seiko Epson Corporation 21-16 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 355 • SENTENCE_0 cortex sets Ch0 Sentence Number to play. • SENTENCE_1 cortex sets Ch1 Sentence Number to play. Please set SENTENCE Number to play listed on EPSON Voice Data Creation PC Tool(ESPER2). • VOLUME_0 cortex sets Ch0 Volume. • VOLUME_1 cortex sets Ch1 Volume •...
Page 356 VOLUME_1 0x1A VOLUME 15-0 0x01 ... -63.5db 0x00 ... No sound REPEAT_0 0x1C REPEAT 15-0 0x00: Inhibit 0x01-0xFE: Repeat times REPEAT_1 0x1E REPEAT 15-0 0xFF: Forever loop until “Sound Stop” command Seiko Epson Corporation 21-18 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 357 1xxx_xxxx_xxxx_xxxx: error_others STATUS 0x46 Reserved 15-9 SOUNDOUT 1: ON 0: OFF Reserved READY 1: Ready 0: Not Ready(Busy) VERSION 0x4C MAJOR Major Version 15-8 MINOR Minor Version S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-19 (Rev. 1.00)
Page 358 HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 Check STATE_x = "sp_state_play", if necessary HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 Check STATE_x = "sp_state_idle" Figure 21.4.15.1 Sound PLAY-FINISH Flow Seiko Epson Corporation 21-20 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 359 Sound Play Function Registers(See Table 21.4.14.1) Cortex Set HW Processor Set HWPCMDTRG.HWP0TRG HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 Check STATE_x = "sp_state_idle" Figure 21.4.15.2 Sound PLAY-STOP Flow S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-21 (Rev. 1.00)
Page 360 Sound Play Function Registers(See Table 21.4.14.1) Cortex Set HW Processor Set HWPCMDTRG.HWP0TRG HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 check STATE_x = "sp_state_play", if necessary Figure 21.4.15.3 Sound Mute-Release Mute Flow Seiko Epson Corporation 21-22 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 361 Sound Play Function Registers(See Table 21.4.14.1) Cortex Set HW Processor Set HWPCMDTRG.HWP0TRG HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 check STATE_x = "sp_state_play", if necessary Figure 21.4.15.4 Sound PAUSE-Release PAUSE Flow S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-23 (Rev. 1.00)
Page 362 HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 Check STATE_CH0 = "sp_state_idle" HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 Check STATE_CH1 = "sp_state_idle" Figure 21.4.15.5 Sound PAUSE-Release PAUSE Flow Seiko Epson Corporation 21-24 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 363 21.5.2. Clock Setting On Memory Check Function, any operating clock can be supplied. For detail of the system clock settings, refer to “2. Clock Generator” in the “Power Supply, Reset, and Clocks” chapter. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-25...
Page 364 “mc_state_crc”, after finishing the Flash check or setting “Memory Check Stop” command, the state is moved to “mc_state_idle”. Figure 21.5.3.1 shows Memory Check State Transition Seiko Epson Corporation 21-26 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 365 HWPEN = 1, in HW Processor Control Register HWPEN = 0, in HW Processor Control Register mc_state _init Memory Check Function mc_state _idle mc_state mc_state mc_state mc_state _checksum _crc _ram_rw _ram_march_c Figure 21.5.3.1 Memory Check State Transition S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-27 (Rev. 1.00)
Page 366 - Set HWPINTE.HWPIE = 1 Cortex Enable HW Processor Enable HWPCTL.HWPEN HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 Check STATE = "mc_state_idle" Memory Check Function Figure 21.5.4.1 Memory Check Configuration Flow Seiko Epson Corporation 21-28 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 367 HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 Check STATE = "mc_state_idle" Check PROCESSING bit field in STATUS register Check RESULT register if error is occurred Figure 21.5.5.1 “RAM Check R/W Start” Command Flow S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-29 (Rev. 1.00)
Page 368 HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 Check STATE = "mc_state_idle" Check PROCESSING bit field in STATUS register Check RESULT register if error is occurred Figure 21.5.6.1 “RAM Check March-C Start” Command Flow Seiko Epson Corporation 21-30 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 369 HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 Check STATE = "mc_state_idle" Check STATUS register Get RESULT register Compare with original checksum value Figure 21.5.7.1 “FLASH CHECKSUM Start” Command Flow S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-31 (Rev. 1.00)
Page 370 HW Processor interrupts to cortex Wait HWPINTF.HWP0IF = 1 Check STATE = "mc_state_idle" Check STATUS register Get RESULT register Compare with original CRC value Figure 21.5.8.1 “FLASH CRC Start” Command Flow Seiko Epson Corporation 21-32 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 371 “mc_state_ram_march_c”, “mc_state_checksum” or “mc_state_crc” is masked. Figure 21.5.10.1 shows “Memory Check Interrupt Masking” flow. Wait STATE_x = "mc_state_idle" Wait STATUS.READY = mc_status_ready Set INTMASK to 0x000x Figure 21.5.10.1 “Memory Check Interrupt Masking” Flow S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-33 (Rev. 1.00)
Page 372 HW Processor status whether ready or busy cortex can set the command ready status. • RESULT cortex reads HW Processor Result • VERSION cortex reads HW Processor Version Table 21.5.11.1 shows Memory Check Function registers. Seiko Epson Corporation 21-34 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 373  If a ERROR is occurred, 1 ERROR address is set RESULT 0x48 RESULT 31-0 FLASH CHECKSUM, FLASH CRC” is completed:  calculation result(16bit) is set MAJOR 15-8 Major Version VERSION 0x4C MINOR Minor Version S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-35 (Rev. 1.00)
Page 374 Initial Reset Remarks HWPINTE 15–1 – 0x00 – – HWPIE Bits 15–1 Reserved Bit 0 HWPIE This bit enables the HW Processor interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Seiko Epson Corporation 21-36 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 375 Bit 0 HWP0TRG This bit indicates the HW Processor command trigger. 1 (R): Setting in progress 0 (R): Ready to set the command trigger 1(W): Set the command trigger 0(W): Setting prohibited S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-37 (Rev. 1.00)
Page 376 Bits 3–2 Reserved Bits 1-0 CLKSRC[1:0] These bits select the clock source of SDAC. SDACCLK CLKSRC[1:0] SDACCLK CLKDIV[1:0] IOSC reserved OSC3 EXOSC reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Seiko Epson Corporation 21-38 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 377 Bits 15–10 Reserved Bits 9–0 These bits is stored the sound data. *This register is used by the HW Processor. This register should not be written while the HW Processor is enabled. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 21-39 (Rev. 1.00)
Page 378 This bit enables the SDAC data request interrupt. 0 (R/W): Disable interrupt *This register is used by the HW Processor. This register should not be written while the HW Processor is enabled. Seiko Epson Corporation 21-40 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 379 16-bit Timer (T16) Ch.7 0x0020 07a0–0x0020 07bc 12-bit A/D Converter (ADC12A) Ch.0 0x0020 0840–0x0020 0850 R/F Converter (RFC) Ch.0 0x0020 0860–0x0020 086c Sound DAC 0x0020 08a0–0x0020 08aa HW Processor 0x0020 1000–0x0020 2014 DMA Controller (DMAC) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 380 – OSDRB R/WP OSDEN R/WP OSC1BUP R/WP CLGOSC1 OSC1SELCR R/WP 0x0020 (CLG OSC1 – 0046 10–8 CGI1[2:0] R/WP Control Register) 7–6 INV1B[1:0] R/WP 5–4 INV1N[1:0] R/WP 3–2 – – 1–0 OSC1WT[1:0] R/WP Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 381 FOUTEN 0x0020 0080 Cache Controller (CACHE) Address Register name Bit name Initial Reset Remarks 15–8 – 0x00 – CACHECTL 7–2 – 0x00 – 0x0020 (CACHE Control – 0080 – – Register) CACHEEN S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 382 – – Alarm Register) 6–4 RTCMIHA[2:0] 3–0 RTCMILA[3:0] 15–12 BCD10[3:0] 11–8 BCD100[3:0] – RTCASWCTL 7–5 – – 0x0020 (RTCA Stopwatch 00c6 SWRST Read as 0. Control Register) 3–1 – – – SWRUN Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 383 RTCTRMIF SW1IF Cleared by writing 1. SW10IF SW100IF 11–9 – – – ALARMIF RTCAINTF T1DAYIF 0x0020 (RTCA Interrupt 00d0 T1HURIF Flag Register) T1MINIF T1SECIF Cleared by writing 1. T1_2SECIF T1_4SECIF T1_8SECIF T1_32SECIF S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 384 0104 In- terrupt Flag 7–1 – 0x00 – Register) SVDIF Cleared by writing 1. SVD3INTE 15–8 – 0x00 – 0x0020 (SVD3 Interrupt 7–1 – 0x00 – – 0106 En- able SVDIE Register) Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 385 Flash Controller (FLASHC) Address Register name Bit name Initial Reset Remarks 15–9 – 0x00 – FLASHCWAIT (reserved) R/WP 0x0020 (FLASHC Flash – 01b0 Read Cycle 7–2 – 0x00 – Register) 1–0 RDWAIT[1:0] R/WP S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 386 – 020c 7–0 P0SEL[7:0] 0x00 Select Register) 15–14 P07MUX[1:0] 13–12 P06MUX[1:0] 11–10 P05MUX[1:0] PPORTP0FNCSEL 9–8 P04MUX[1:0] 0x0020 (P0 Port Function – 020e 7–6 P03MUX[1:0] Select Register) 5–4 P02MUX[1:0] 3–2 P01MUX[1:0] 1–0 P00MUX[1:0] Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 387 – 021c 7–0 P1SEL[7:0] 0x00 Select Register) 15–14 P17MUX[1:0] 13–12 P16MUX[1:0] 11–10 P15MUX[1:0] PPORTP1FNCSEL 9–8 P14MUX[1:0] 0x0020 (P1 Port Function – 021e 7–6 P13MUX[1:0] Select Register) 5–4 P12MUX[1:0] 3–2 P11MUX[1:0] 1–0 P10MUX[1:0] S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation (Rev. 1.00)
Page 388 022c 7–0 P2SEL[7:0] 0x00 Select Register) 15–14 P27MUX[1:0] 13–12 P26MUX[1:0] 11–10 P25MUX[1:0] PPORTP2FNCSEL 9–8 P24MUX[1:0] 0x0020 (P2 Port Function – 022e 7–6 P23MUX[1:0] Select Register) 5–4 P22MUX[1:0] 3–2 P21MUX[1:0] 1–0 P20MUX[1:0] Seiko Epson Corporation B-10 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 389 023c 7–0 P3SEL[7:0] 0x00 Select Register) 15–14 P37MUX[1:0] 13–12 P36MUX[1:0] 11–10 P35MUX[1:0] PPORTP3FNCSEL 9–8 P34MUX[1:0] 0x0020 (P3 Port Function – 023e 7–6 P33MUX[1:0] Select Register) 5–4 P33MUX[1:0] 3–2 P31MUX[1:0] 1–0 P30MUX[1:0] S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-11 (Rev. 1.00)
Page 390 024c 7–0 P4SEL[7:0] 0x00 Select Register) 15–14 P47MUX[1:0] 13–12 P46MUX[1:0] 11–10 P45MUX[1:0] PPORTP4FNCSEL 9–8 P44MUX[1:0] 0x0020 (P4 Port Function – 024e 7–6 P43MUX[1:0] Select Register) 5–4 P42MUX[1:0] 3–2 P41MUX[1:0] 1–0 P40MUX[1:0] Seiko Epson Corporation B-12 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 391 025c 7–0 P5SEL[7:0] 0x03 Select Register) 15–14 P57MUX[1:0] 13–12 P56MUX[1:0] 11–10 P55MUX[1:0] PPORTP5FNCSEL 9–8 P55MUX[1:0] 0x0020 (P5 Port Function – 025e 7–6 P53MUX[1:0] Select Register) 5–4 P52MUX[1:0] 3–2 P51MUX[1:0] 1–0 P50MUX[1:0] S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-13 (Rev. 1.00)
Page 392 026c 7–0 P6SEL[7:0] 0x00 Select Register) 15–14 P67MUX[1:0] 13–12 P66MUX[1:0] 11–10 P65MUX[1:0] PPORTP6FNCSEL 9–8 P64MUX[1:0] 0x0020 (P6 Port Function – 026e 7–6 P63MUX[1:0] Select Register) 5–4 P62MUX[1:0] 3–2 P61MUX[1:0] 1–0 P60MUX[1:0] Seiko Epson Corporation B-14 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 393 027c 7–0 P7SEL[7:0] 0x00 Select Register) 15–14 P77MUX[1:0] PPORTP7FNCSEL 0x0020 (P7 Port Function 13–12 P76MUX[1:0] 027e Select Register) 11–10 P75MUX[1:0] 9–8 P74MUX[1:0] – 7–6 P73MUX[1:0] 5–4 P72MUX[1:0] 3–2 P71MUX[1:0] 1–0 P70MUX[1:0] S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-15 (Rev. 1.00)
Page 394 028c 7–0 P8SEL[7:0] 0x00 Select Register) 15–14 P87MUX[1:0] 13–12 P86MUX[1:0] 11–10 P85MUX[1:0] PPORTP8FNCSEL 9–8 P84MUX[1:0] 0x0020 (P8 Port Function – 028e 7–6 P83MUX[1:0] Select Register) 5–4 P82MUX[1:0] 3–2 P81MUX[1:0] 1–0 P80MUX[1:0] Seiko Epson Corporation B-16 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 395 Select Register) 5–0 P9SEL[5:0] 0x00 15–14 – – 13–12 – – 11–10 P95MUX[1:0] PPORTP9FNCSEL 9–8 P94MUX[1:0] 0x0020 (P9 Port Function – 029e 7–6 P93MUX[1:0] Select Register) 5–4 P92MUX[1:0] 3–2 P91MUX[1:0] 1–0 P90MUX[1:0] S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-17 (Rev. 1.00)
Page 396 Select Register) 6–0 PASEL[6:0] 0x00 15–14 – – 13–12 PA6MUX[1:0] 11–10 PA5MUX[1:0] PPORTPAFNCSEL 9–8 PA4MUX[1:0] 0x0020 (PA Port Function – 02ae 7–6 PA3MUX[1:0] Select Register) 5–4 PA2MUX[1:0] 3–2 PA1MUX[1:0] 1–0 PA0MUX[1:0] Seiko Epson Corporation B-18 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 397 – 02dc Select Register) 5–0 PDSEL[5:0] 15–12 – 0x00 – 11–10 PD5MUX[1:0] 9–8 PD4MUX[1:0] PPORTPDFNCSEL 0x0020 (Pd Port Function 7–6 PD3MUX[1:0] – 02de Select Register) 5–4 PD2MUX[1:0] 3–2 PD1MUX[1:0] 1–0 PD0MUX[1:0] S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-19 (Rev. 1.00)
Page 398 3–2 KRSTCFG[1:0] R/WP 1–0 CLKSRC[1:0] R/WP 15–11 – 0x00 – PAINT P9INT P8INT P7INT PPORTINTFGRP P6INT 0x0020 (P Port Interrupt – 02e2 Flag Group P5INT Register) P4INT P3INT P2INT P1INT P0INT Seiko Epson Corporation B-20 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 399 Port Multiplexer 7–5 P10PPFNC[2:0] Setting Register) 4–3 P10PERICH[1:0] 2–0 P10PERISEL[2:0] 15–13 P13PPFNC[2:0] 12–11 P13PERICH[1:0] UPMUXP1MUX1 10–8 P13PERISEL[2:0] 0x0020 (P12–13 Universal – 030a Port Multiplexer 7–5 P12PPFNC[2:0] Setting Register) 4–3 P12PERICH[1:0] 2–0 P12PERISEL[2:0] S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-21 (Rev. 1.00)
Page 400 Port Multiplexer 7–5 P30PPFNC[2:0] Setting Register) 4–3 P30PERICH[1:0] 2–0 P30PERISEL[2:0] 15–13 P33PPFNC[2:0] 12–11 P33PERICH[1:0] UPMUXP3MUX1 10–8 P33PERISEL[2:0] 0x0020 (P32–33 Universal – 031a Port Multiplexer 7–5 P32PPFNC[2:0] Setting Register) 4–3 P32PERICH[1:0] 2–0 P32PERISEL[2:0] Seiko Epson Corporation B-22 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 401 Port Multiplexer 7–5 P34PPFNC[2:0] Setting Register) 4–3 P34PERICH[1:0] 2–0 P34PERISEL[2:0] 15–13 P37PPFNC[2:0] 12–11 P37PERICH[1:0] UPMUXP3MUX3 10–8 P37PERISEL[2:0] 0x0020 (P36–37 Universal – 031e Port Multiplexer 7–5 P36PPFNC[2:0] Setting Register) 4–3 P36PERICH[1:0] 2–0 P36PERISEL[2:0] S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-23 (Rev. 1.00)
Page 402 H0/S0 Interrupt Flag UART3_0RXD register. Register) OEIF H0/S0 Cleared by writing 1. RB2FIF H0/S0 Cleared by reading the UART3_0RXD register. RB1FIF H0/S0 Cleared by writing to the TBEIF H0/S0 UART3_0TXD register. Seiko Epson Corporation B-24 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 403 (UART3 Ch.0 0x0020 Receive Buffer – 0392 One Byte Full 3–0 RB1FDMAEN[3:0] DMA Request Enable Register) UART3_0CAWF 15–8 – 0x00 – (UART3 Ch.0 0x0020 Carrier – 0394 7–0 CRPER[7:0] 0x00 Waveform Register) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-25 (Rev. 1.00)
Page 404 7–1 – 0x00 – 03aa Interrupt Flag UFIF Cleared by writing 1. Register) T16_1INTE 15–8 – 0x00 – 0x0020 (T16 Ch.1 7–1 – 0x00 – – 03ac Interrupt Enable UFIE Register) Seiko Epson Corporation B-26 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 405 – 03bc Empty DMA 3–0 TBEDMAEN[3:0] Request Enable Register) SPIA_0RBFDMAEN 15–8 – 0x00 – (SPIA Ch.0 7–4 – – 0x0020 Receive Buffer Full – 03be DMA Request 3–0 RBFDMAEN[3:0] Enable Register) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-27 (Rev. 1.00)
Page 406 NACKIF H0/S0 Cleared by writing 1. Flag Register) STOPIF H0/S0 STARTIF H0/S0 ERRIF H0/S0 Cleared by reading the RBFIF H0/S0 I2C_0RXD register. Cleared by writing to the TBEIF H0/S0 I2C_0TXD register. Seiko Epson Corporation B-28 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 407 – 03d4 Empty DMA 3–0 TBEDMAEN[3:0] Request Enable Register) I2C_0RBFDMAEN 15–8 – 0x00 – (I2C Ch.0 Receive 7–4 – – 0x0020 Buffer Full DMA – 03d6 Request Enable 3–0 RBFDMAEN[3:0] Register) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-29 (Rev. 1.00)
Page 408 – – – – – – – – – CAPOW3IF T16B_0INTF CMPCAP3IF 0x0020 (T16B Ch.0 CAPOW2IF 040a Interrupt Flag Cleared by writing 1. CMPCAP2IF Register) CAPOW1IF CMPCAP1IF CAPOW0IF CMPCAP0IF CNTMAXIF CNTZEROIF Seiko Epson Corporation B-30 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 409 – 0x0020 (T16B Ch.0 – 0418 Compare/ Capture TOUTMT 1 Control Register) TOUTO 4–2 TOUTMD[2:0] TOUTINV CCMD T16B_0CCR1 0x0020 (T16B Ch.0 15–0 CC[15:0] 0x0000 – 041a Compare/ Capture 1 Data Register) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-31 (Rev. 1.00)
Page 410 CC[15:0] 0x0000 – 042a Compare/ Capture 3 Data Register) T16B_0CC3DMAEN 15–8 – 0x00 – (T16B Ch.0 7–4 – – 0x0020 Compare/ Capture – 042c 3 DMA Request 3–0 CC3DMAEN[3:0] Enable Register) Seiko Epson Corporation B-32 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 411 UP_DOWN 15–14 – – – CAPOW5IF CMPCAP5IF CAPOW4IF CMPCAP4IF CAPOW3IF T16B_1INTF CMPCAP3IF 0x0020 (T16B Ch.1 CAPOW2IF 044a Interrupt Flag Cleared by writing 1. CMPCAP2IF Register) CAPOW1IF CMPCAP1IF CAPOW0IF CMPCAP0IF CNTMAXIF CNTZEROIF S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-33 (Rev. 1.00)
Page 412 1 Control Register) TOUTO 4–2 TOUTMD[2:0] TOUTINV CCMD T16B_1CCR1 0x0020 (T16B Ch.1 15–0 CC[15:0] 0x0000 – 045a Compare/ Capture 1 Data Register) 15–8 – 0x00 – 0x0020 T16B_1CC1DMAEN – 045c 7–4 – – Seiko Epson Corporation B-34 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 413 CC[15:0] 0x0000 – 046a Compare/ Capture 3 Data Register) T16B_1CC3DMAEN 15–8 – 0x00 – (T16B Ch.1 7–4 – – 0x0020 Compare/ Capture – 046c 3 DMA Request 3–0 CC3DMAEN[3:0] Enable Register) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-35 (Rev. 1.00)
Page 414 7–1 – 0x00 – 048a Interrupt Flag Cleared by UFIF Register) writing 1. T16_3INTE 15–8 – 0x00 – 0x0020 (T16 Ch.3 7–1 – 0x00 – – 048c Interrupt Enable UFIE Register) Seiko Epson Corporation B-36 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 415 7–1 – 0x00 – 04aa Interrupt Flag Cleared by UFIF Register) writing 1. T16_4INTE 15–8 – 0x00 – 0x0020 (T16 Ch.4 7–1 – 0x00 – – 04ac Interrupt Enable UFIE Register) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-37 (Rev. 1.00)
Page 416 7–1 – 0x00 – 04ca Interrupt Flag Cleared by UFIF Register) writing 1. T16_5INTE 15–8 – 0x00 – 0x0020 (T16 Ch.5 7–1 – 0x00 – – 04cc Interrupt Enable UFIE Register) Seiko Epson Corporation B-38 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 417 – 04dc Empty DMA 3–0 TBEDMAEN[3:0] Request Enable Register) SPIA_2RBFDMAEN 15–8 – 0x00 – (SPIA Ch.2 Receive 7–4 – – 0x0020 Buffer Full DMA – 04de Request Enable 3–0 RBFDMAEN[3:0] Register) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-39 (Rev. 1.00)
Page 418 – 0x00 – 0x0020 (UART3 Ch.1 – 0608 Trans- mit Data 7–0 TXD[7:0] 0x00 Register) UART3_1RXD 15–8 – 0x00 – 0x0020 (UART3 Ch.1 – 060a Receive Data 7–0 RXD[7:0] 0x00 Register) Seiko Epson Corporation B-40 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 419 (UART3 Ch.1 0x0020 Receive Buffer – 0612 One Byte Full 3–0 RB1FDMAEN[3:0] DMA Request Enable Register) UART3_1CAWF 15–8 – 0x00 – 0x0020 (UART3 Ch.1 – 0614 Carrier Waveform 7–0 CRPER[7:0] 0x00 Register) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-41 (Rev. 1.00)
Page 420 – 0x00 – 0x0020 (UART3 Ch.2 – 0628 Trans- mit Data 7–0 TXD[7:0] 0x00 Register) UART3_2RXD 15–8 – 0x00 – 0x0020 (UART3 Ch.2 – 062a Receive Data 7–0 RXD[7:0] 0x00 Register) Seiko Epson Corporation B-42 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 421 (UART3 Ch.2 0x0020 Receive Buffer – 0632 One Byte Full 3–0 RB1FDMAEN[3:0] DMA Request Enable Register) UART3_2CAWF 15–8 – 0x00 – 0x0020 (UART3 Ch.2 – 0634 Carrier Waveform 7–0 CRPER[7:0] 0x00 Register) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-43 (Rev. 1.00)
Page 422 7–1 – 0x00 – 066a Interrupt Flag Cleared by UFIF Register) writing 1. T16_6INTE 15–8 – 0x00 – 0x0020 (T16 Ch.6 7–1 – 0x00 – – 066c Interrupt Enable UFIE Register) Seiko Epson Corporation B-44 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 423 – 067c Empty DMA 3–0 TBEDMAEN[3:0] Request Enable Register) SPIA_1RBFDMAEN 15–8 – 0x00 – (SPIA Ch.1 Receive 7–4 – – 0x0020 Buffer Full DMA – 067e Request Enable 3–0 RBFDMAEN[3:0] Register) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-45 (Rev. 1.00)
Page 424 7–1 – 0x00 – 068a Interrupt Flag Cleared by UFIF Register) writing 1. T16_2INTE 15–8 – 0x00 – 0x0020 (T16 Ch.2 7–1 – 0x00 – – 068c Interrupt Enable UFIE Register) Seiko Epson Corporation B-46 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 425 (QSPI Ch.0 – 069a Interrupt Enable TENDIE Register) RBFIE TBEIE QSPI_0TBEDMAEN 15–8 – 0x00 – (QSPI Ch.0 7–4 – – 0x0020 Transmit Buffer – 069c Empty DMA 3–0 TBEDMAEN[3:0] Request Enable Register) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-47 (Rev. 1.00)
Page 426 DATTMOD[1:0] 0x0020 Memory Mapped 5–4 DUMTMOD[1:0] – 06a6 Access Con- 3–2 ADRTMOD[1:0] figuration Register ADRCYC MMAEN QSPI_0MB 15–8 XIPACT[7:0] 0x00 0x0020 (QSPI Ch.0 Mode – 06a8 7–0 XIPEXT[7:0] 0x00 Byte Register) Seiko Epson Corporation B-48 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 427 NACKIF H0/S0 Flag Register) Cleared by writing 1. STOPIF H0/S0 STARTIF H0/S0 ERRIF H0/S0 Cleared by reading the RBFIF H0/S0 I2C_1RXD register. Cleared by writing to the TBEIF H0/S0 I2C_1TXD register. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-49 (Rev. 1.00)
Page 428 – 06d4 Empty DMA 3–0 TBEDMAEN[3:0] Request Enable Register) I2C_1RBFDMAEN 15–8 – 0x00 – (I2C Ch.1 Receive 7–4 – – 0x0020 Buffer Full DMA – 06d6 Request Enable 3–0 RBFDMAEN[3:0] Register) Seiko Epson Corporation B-50 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 429 NACKIF H0/S0 Cleared by writing 1. Flag Register) STOPIF H0/S0 STARTIF H0/S0 ERRIF H0/S0 Cleared by reading the RBFIF H0/S0 I2C_2RXD register. Cleared by writing to the TBEIF H0/S0 I2C_2TXD register. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-51 (Rev. 1.00)
Page 430 – 06f4 Empty DMA 3–0 TBEDMAEN[3:0] Request Enable Register) I2C_2RBFDMAEN 15–8 – 0x00 – (I2C Ch.2 Receive 7–4 – – 0x0020 Buffer Full DMA – 06f6 Request Enable 3–0 RBFDMAEN[3:0] Register) Seiko Epson Corporation B-52 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 431 CRDTY[7:0] 0x00 0x0020 (REMC3 Carrier – 0730 Waveform 7–0 CRPER[7:0] 0x00 Register) 15–9 – 0x00 – REMC3CCTL OUTINVEN 0x0020 (REMC3 Carrier – 0732 Modulation 7–1 – 0x00 – Control Register) CARREN S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-53 (Rev. 1.00)
Page 432 7–1 – 0x00 – 078a Interrupt Flag UFIF Cleared by writing 1. Register) T16_7INTE 15–8 – 0x00 – 0x0020 (T16 Ch.7 7–1 – 0x00 – – 078c Interrupt Enable UFIE Register) Seiko Epson Corporation B-54 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 433 7–4 – – 0x0020 – 07ac Request Enable 3–0 ADCDMAEN[3:0] Register 0) ADC12A_0DMAEN1 15–8 – 0x00 – (ADC12A Ch.0 7–4 – – 0x0020 – 07ae Request Enable 3–0 ADCDMAEN[3:0] Register 1) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-55 (Rev. 1.00)
Page 434 Register 6) ADC12A_0DMAEN7 15–8 – 0x00 – (ADC12A Ch.0 7–4 – – 0x0020 – 07ba Request Enable 3–0 ADCDMAEN[3:0] Register 7) ADC12A_0ADD 0x0020 (ADC12A Ch.0 15–0 ADD[15:0] 0x0000 – 07bc Result Register) Seiko Epson Corporation B-56 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 435 OVMCIF 084e Interrupt Flag ESENBIF Register) ESENAIF EREFIF 15-8 – 0x00 – – – RFC_0INTE OVTCIE Cleard by writing 1. 0x0020 (RFC Ch.0 OVMCIE 0850 Interrupt Enable ESENBIE Register) ESENAIE EREFIE S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-57 (Rev. 1.00)
Page 436 SDAC Data – 0866 Register 15–2 – 0x00 – 0x0020 SDAC Interrupt ERRIF – 0868 Flag Register DATREQIF 15–2 – 0x00 – 0x0020 SDAC Interrupt ERRIE – 086a Enable Register DATREQIE Seiko Epson Corporation B-58 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 437 HWP1IF(ERRIF) – 08a4 Register HWP0IF(STIF) HW Processor 15–1 – 0x00 – 0x0020 Interrupt Enable – 08a6 HWPIE Register HW Processor 15–1 0x00 – – 0x0020 Command – 08a8 HWP0TRG Trigger Register S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-59 (Rev. 1.00)
Page 438 – 3–0 ENSET[3:0] 31–24 – – – 23–16 – – – DMACENCLR 0x0020 (DMAC Enable 15–8 – – – – 102c Clear Register) 7–4 – – – 3–0 ENCLR[3:0] – – Seiko Epson Corporation B-60 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 439 Register) ERRIESET 31–24 – 0x00 – DMACERRIECLR 23–16 – 0x00 – (DMAC Error 0x0020 Interrupt 15–8 – 0x00 – – 2014 Enable Clear 7–1 – 0x00 – Register) ERRIECLR – – S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation B-61 (Rev. 1.00)
Page 440 *2 R are not required when using the debug pins as general-purpose I/O ports. DBG1–2 *3 C should be connected only when the V voltage is not stable. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 23-1 (Rev. 1.00)
Page 441 *1 OSC1 oscillator: CLGOSC1.OSC1SELCR bit = 0, CLGOSC1.INV1N[1:0] bits = 0x0, CLGOSC1.CGI1[2:0] bits = 0x0, CLGOSC1. OSDEN bit = 0, C = 0 pF, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), C = 7 pF) *2 OSC1 oscillator: CLGOSC1.OSC1SELCR bit = 1...
Page 442 IOSC = OFF, OSC1 = 32.768 kHz, OSC3 = OFF, Typ. value Current consumption-temperature characteristic In HALT mode (OSC3 operation) OSC3 = ON, OSC1 = 32.768kHz, IOSC = OFF, Typ. Value S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 23-3 (Rev. 1.00)
Page 443 RUN mode (OSC3 operation) IOSC = OFF, OSC1 = 32.768 kHz, OSC3 = OFF, Typ. value IOSC = OFF, OSC1 = 32.768 kHz, OSC3 = ON (CR oscillator), Typ. Value Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL 23-4 (Rev. 1.00)
Page 444 = 0 V, Ta = -40 to 85 °C Item Symbol Condition Min. Typ. Max. Unit – – µs Reset hold time RSTR *1 Time until the internal reset signal is negated after the reset request is canceled. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 23-5 (Rev. 1.00)
Page 445 PWGACTL.REGSEL bit = 0 IOSC oscillation frequency-temperature characteristic = 1.8 to 5.5 V, PWGACTL.REGSEL bit = 1, Typ. value = 1.8 to 5. 5 V, PWGACTL.REGSEL bit = 0, Typ. value Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL 23-6 (Rev. 1.00)
Page 446 CLGOSC1.OSC1SELCR bit = 1 31.04 32.96 OSC1I oscillation frequency *1 CLGOSC1.CGI1[2:0] bits = 0x0, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R1 = 50 kW (Max.), CL = 7 pF) S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 23-7 (Rev. 1.00)
Page 447 High level Schmitt input threshold voltage V 0.2 × V – 0.5 × V Low level Schmitt input threshold voltage – – Schmitt input hysteresis voltage EXOSC = EXOSC = EXOSC EXOSCH EXOS Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL 23-8 (Rev. 1.00)
Page 448 Low level output current VOL = 0.1 × VDD – – Leakage current ILEAK -150 – Input pull-up resistance RINU KΩ Input pull-down resistance RIND KΩ Pin capacitance – – High level Low level S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 23-9 (Rev. 1.00)
Page 449 4.61 SVD3CTL.SVDC[4:0] bits = 0x1b 4.49 4.72 SVD3CTL.SVDC[4:0] bits = 0x1c 4.58 4.82 SVD3CTL.SVDC[4:0] bits = 0x1d 4.68 4.92 SVD3CTL.SVDC[4:0] bits = 0x1e 4.78 5.02 SVD3CTL.SVDC[4:0] bits = 0x1f 4.88 5.13 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL 23-10 (Rev. 1.00)
Page 450 *1 If CLK_SVD3 is configured in the neighborhood of 32 kHz, the SVD3INTF.SVDDT bit is masked during the t period and it SVDEN retains the previous value. CLK_SVD3 SVD3CTL.MODEN SVD3CTL.SVDC[4:0] 0x1e 0x10 Invalid Valid Invalid Valid SVD3INTF.SVDDT SVDEN S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 23-11 (Rev. 1.00)
Page 451 = 1.8 to 5.5 V, V = 0 V, Ta = -40 to 85 °C Item Symbol Condition Min. Typ. Max. Unit Transfer baud rate Normal mode – 460,800 BRT1 IrDA mode – 115,200 BRT2 Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL 23-12 (Rev. 1.00)
Page 452 = Pin load Master and slave modes SCYC SCKL SCKH SPICLKn (CPOL, CPHA) = (1, 0) or (0, 1) SPICLKn (CPOL, CPHA) = (1, 1) or (0, 0) SDIn SDOn Slave mode S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 23-13 (Rev. 1.00)
Page 453 #SPISSn SPICLKn (CPOL, CPHA) = (0, 1) SPICLKn (CPOL, CPHA) = (1, 0) SDIn Hi-Z SDOn Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL 23-14 (Rev. 1.00)
Page 454 QSDIOn[3:0] output stop time = 15 pF 3.0 to 5.5 V mode0 – – 1.8 to 3.0 V mode0 – – 1.8 to 3.6 V mode1 – – *1 C = Pin load S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 23-15 (Rev. 1.00)
Page 455 – – µs tBUF tSU:DAT SDIn tSU:DAT tSU:STA tSU:STO tHIGH tHD:STA SDOn tHD:STA tLOW S: START condition 1/fSCL Sr: Repeated START condition 9th clock cycle 1st clock cycle P: STOP condition Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL 23-16 (Rev. 1.00)
Page 456 *3 The error will be increased according to the potential difference between V and VREFAn. A/D converter current consumption-power supply voltage characteristic , ADIN = V /2, f = 100 ksps, Ta = 25 °C, Typ. value REFA REFA S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 23-17 (Rev. 1.00)
Page 457 = 100 kW, Ta = 25 °C, Typ. value 1,000 1,000 3.6 V 1.8 V 3.6 V 1.8 V ∆f /∆IC ∆f /∆IC RFCLK RFCLK 1,000 10,000 1,000 10,000 100,000 [kΩ] [pF] Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL 23-18 (Rev. 1.00)
Page 458 = 1,000 pF, Typ. value = 1,000 pF, Ta = 25 °C, Typ. value 1,800 = 3.6 V 1,600 1.8 V 1,400 1,200 1,000 = 3.6 V 1.8 V 1,000 10,000 Ta [°C] [kHz] RFCLK S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 23-19 (Rev. 1.00)
Page 459 *2: For Flash programming (when VPP is generated internally) *3: When OSC1 crystal oscillator is selected *4: When OSC3 crystal/ceramic oscillator is selected [ ]: Do not mount components if unnecessary. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 24-1 (Rev. 1.00)
Page 460 Symbol Name Recommended components X'tal1 32 kHz crystal resonator C-002RX (R = 50 kW (Max.), C = 7 pF) manufactured by Seiko Epson Corporation OSC1 gate capacitor Trimmer capacitor or ceramic capacitor OSC1 drain capacitor Ceramic capacitor X’tal3 Crystal resonator...
Page 461 25. Package TQFP12-48PIN S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 25-1 (Rev. 1.00)
Page 462 QFP13-64PIN Seiko Epson Corporation 25-2 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 463 TQFP14-80PIN S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 25-3 (Rev. 1.00)
Page 464 QFP15-100PIN Seiko Epson Corporation 25-4 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 465 To reduce current consumption, set the MODEN bits of unnecessary peripheral circuits to 0. Note that the real-time clock has no MODEN bit, therefore, current consumption does not vary if it is counting or idle. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 26-1...
Page 466 Continuous operation mode (SVD3CTL.SVDMD[1:0] bits = 0x0) always detects the power supply voltage, therefore, it increases current consumption. Set the supply voltage detector to intermittent operation mode or turn it on only when required. Seiko Epson Corporation 26-2 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 467 Failure to observe precautions (1) to (3) adequately may lead to noise in OSC1CLK and jitter in OSC3CLK. Noise in the OSC1CLK will destabilize timers that use OSC1CLK as well as CPU Core operations. Jitter in the OSC3 output will reduce operating frequencies. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 26-3...
Page 468 • The SEG/COM lines and voltage boost/reduce capacitor drive lines are more likely to generate noise, therefore keep a distance between the lines and pins susceptible to noise. Seiko Epson Corporation 26-4 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 469 Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same potential as the IC GND. S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 26-5 (Rev. 1.00)
Page 470 Execute the resending process via software after executing the receive error handler with a parity check. For details of the pin functions and the function switch control, see the “I/O Ports” chapter. For the UART control and details of receive errors, see the “UART” chapter. Seiko Epson Corporation 26-6 S1C31D50 TECHNICAL MANUAL (Rev. 1.00)
Page 471 Revision History Code No. Page Contents 413699400 New establishment S1C31D50 TECHNICAL MANUAL Seiko Epson Corporation 26-1 (Rev. 1.00)
Page 472 Epson Europe Electronics GmbH Riesstrasse 15, 80992 Munich, Germany Phone: +49-89-14005-0 FAX: +49-89-14005-110 Epson Taiwan Technology & Trading Ltd. 15F, No.100, Songren Rd, Sinyi Dist, Taipei City 110. Taiwan Phone: +886-2-8786-6688 Epson Singapore Pte., Ltd. 1 HarbourFront Place, #03-02 HarbourFront Tower One, Singapore 098633...

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